Semiconductor device

Abstract

Some embodiments of the present disclosure provide a semiconductor device with reduced resistance in a conductive path from a gate to a contact. In one embodiment, a semiconductor device includes a multi-gate structure over a semiconductor substrate and including a top inner gate portion, a source / drain feature laterally adjacent to the multi-gate structure, an interlayer dielectric layer over the multi-gate structure and the source / drain feature, a source / drain contact extending through the interlayer dielectric layer to the source / drain feature, and a side pad on the source / drain contact, the side pad extending to a lowest edge in contact with the source / drain feature, where the lowest edge is over the top inner gate portion.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to semiconductor devices having conductive paths with reduced resistance. Background Technology

[0002] The electronics industry has experienced a growing demand for smaller and faster electronic devices capable of supporting increasingly complex and sophisticated functions. Consequently, the semiconductor industry has seen a continuous trend towards manufacturing low-cost, high-efficiency, and low-power integrated circuits (ICs). To date, these demands have been largely met by shrinking the size of semiconductor ICs (e.g., the smallest feature size), thereby increasing production efficiency and reducing associated costs. However, such size reduction also increases the complexity of semiconductor manufacturing processes. Therefore, continued advancements in semiconductor ICs and devices require similar advancements in semiconductor manufacturing processes and technologies.

[0003] Multi-gate devices have been introduced to improve gate control by increasing gate channel coupling, reducing off-state current, and mitigating the short-channel effect (SCE). One such multi-gate device is the fin field-effect transistor (FinFET). FinFET gets its name from the fin structure formed on and extending from the substrate, which forms the field-effect transistor channel. Another multi-gate device is the gate-all-around (GAA) transistor, introduced to address the performance challenges associated with FinFET. GAA devices are named for their gate structure that extends completely around the channel, providing better electrostatic control than FinFET. Both FinFET and GAA devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes. Furthermore, the three-dimensional structure of these devices allows for aggressive size reduction while maintaining gate control and mitigating the short-channel effect. Utility Model Content

[0004] According to some embodiments of the present disclosure, a semiconductor device includes a multi-gate structure located above a semiconductor substrate and including a top inner gate portion, a source / drain feature laterally adjacent to the multi-gate structure, an interlayer dielectric layer located above the multi-gate structure and the source / drain feature, a source / drain contact extending through the interlayer dielectric layer to the source / drain feature, and a side pad located on the source / drain contact, the side pad extending to a lowest edge that contacts the source / drain feature, wherein the lowest edge is located above the top inner gate portion.

[0005] According to some embodiments of this disclosure, a semiconductor device includes a source / drain feature adjacent to a gate, wherein the gate is located at a first vertical height above the uppermost surface of a semiconductor fin. The semiconductor device also includes a first dielectric material above the source / drain feature, a capping layer above the first dielectric material, a second dielectric material above the capping layer, and an opening having sidewalls extending through the second dielectric material, the capping layer, and the first dielectric material to the source / drain feature. The semiconductor device also includes side pads on the sidewalls of the opening, wherein the side pads extend to a lowest edge contacting the source / drain feature, the lowest edge being located at a second vertical height, and the second vertical height being at or above the first vertical height.

[0006] According to some embodiments of this disclosure, a semiconductor device includes a source / drain feature located above a semiconductor substrate and adjacent to a fin structure, a first dielectric material located above the source / drain feature, a capping layer located above the first dielectric material, a second dielectric material located above the capping layer, and a source / drain contact extending through the second dielectric material, the capping layer, and the first dielectric material and electrically connected to the source / drain feature. The semiconductor device also includes a sidewall located on the sidewall of the source / drain contact and extending to a lowest edge that contacts the source / drain feature, wherein the lowest edge is located above the uppermost semiconductor surface of the fin structure. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 This is a plan view of the layout of a multi-gate device according to some embodiments;

[0009] Figure 2 A flowchart illustrating a method according to some embodiments;

[0010] Figures 3 to 26 According to some embodiments, in accordance with Figure 2A perspective or cross-sectional view of a semiconductor device during the continuous manufacturing phase of a method;

[0011] Figure 27 Transmission electron microscope (TEM) images of semiconductor devices according to some embodiments.

[0012] [Symbol Explanation]

[0013] 8-8: Line

[0014] 10:Substrate

[0015] 11: Unit

[0016] 20: Active Zone

[0017] 30: Gate line

[0018] 100: Device

[0019] 200: Device

[0020] 202:Substrate

[0021] 209: Horizontal plane

[0022] 212: Epitaxial Stacking

[0023] 214: Epitaxial layer

[0024] 216: Epitaxial layer

[0025] 217: Masking layer

[0026] 218: First mask layer

[0027] 219: Second masking layer

[0028] 220: Fins

[0029] 220a: Partial

[0030] 221: Shallow trench isolation features

[0031] 222: Sacrificial gate structure

[0032] 223: Sacrificial gate dielectric

[0033] 224: Sacrificial gate electrode

[0034] 225: Masking layer

[0035] 226: Masking layer

[0036] 227: Masking layer

[0037] 230: Spacer

[0038] 231: Lining layer

[0039] 232: Main spacer layer

[0040] 233: Bottom gap surface

[0041] 234: Recess / gap

[0042] 235: Fin section

[0043] 300: Isolation layer

[0044] 400: Source / Drain Characteristics

[0045] 401: Source / Drain Characteristics

[0046] 402: Source / Drain Characteristics

[0047] 440: Pad

[0048] 450: Dielectric

[0049] 499: Gate cavity

[0050] 500: Gate structure

[0051] 501: Gate Structure

[0052] 502: Gate structure

[0053] 503: Gate Structure

[0054] 540: Gate dielectric layer

[0055] 550: Gate electrode material

[0056] 551: Inner gate portion

[0057] 552: Inner gate portion

[0058] 553: Inner gate portion

[0059] 555: External gate portion

[0060] 560: Semiconductor Nanosheets

[0061] 561: Nanosheets

[0062] 562: Nanosheets

[0063] 563: Nanosheets

[0064] 565: Upper surface

[0065] 599: Upper surface

[0066] 600: Floor

[0067] 700: Interlayer dielectric layer

[0068] 720: Opening

[0069] 730: Sidewall

[0070] 740: Opening

[0071] 750: Sidewall

[0072] 780: Opening

[0073] 781: Opening

[0074] 782: Opening

[0075] 783: Opening

[0076] 790: Sidewall

[0077] 799: Surface

[0078] 800: Dielectric material / side pad

[0079] 801: Bottom Edge

[0080] 900: Conductive interconnect / Metallic interconnect

[0081] 910: Upper part

[0082] 920: Dielectric layer

[0083] 930: Dielectric layer

[0084] 950: Metal interconnect layer

[0085] 1000: Method

[0086] 2161: Hole

[0087] 2162: Internal spacers

[0088] 2169: Gap

[0089] H1: Distance / Height

[0090] H2: Distance / Height

[0091] H3: Distance / Height

[0092] H5: Height

[0093] S1010: Steps

[0094] S1020: Steps

[0095] S1030: Steps

[0096] S1040: Steps

[0097] S1050: Steps

[0098] S1060: Steps

[0099] S1070: Steps

[0100] S1080: Steps

[0101] S1090: Steps

[0102] S1100: Steps

[0103] S1110: Steps

[0104] S1120: Steps

[0105] S1130: Steps

[0106] S1140: Steps

[0107] S1150: Steps

[0108] S1160: Steps

[0109] S1170: Steps

[0110] S1171: Steps

[0111] S1172: Steps

[0112] S1180: Steps

[0113] S1181: Steps

[0114] S1182: Steps

[0115] S1190: Steps

[0116] S1200: Steps

[0117] W5: Width Detailed Implementation

[0118] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0119] Furthermore, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0120] In some embodiments herein, a “material layer” is a layer comprising at least 50 wt% of the identified material, such as at least 60 wt%, at least 75 wt%, at least 90 wt%, or substantially 100 wt% of the identified material. A layer referred to as “material” comprises at least 50 wt% of the identified material, such as at least 60 wt%, at least 75 wt%, at least 90 wt%, or substantially 100 wt% of the identified material. For example, in some embodiments, a titanium nitride layer and a layer of titanium nitride are each at least 50 wt%, at least 60 wt%, at least 75 wt%, at least 90 wt%, or at least 95 wt% of titanium nitride, or substantially 100 wt% of titanium nitride.

[0121] For the sake of brevity, the known techniques associated with the manufacture of conventional semiconductor devices are not described in detail herein. Furthermore, the various tasks and processes described herein can be incorporated into more comprehensive procedures or processes with additional functionality not described in detail herein. Specifically, the various processes in the manufacture of semiconductor devices are well known, and therefore, for the sake of brevity, many known processes will be mentioned only briefly or omitted entirely without providing well-known process details. It will be readily apparent to those skilled in the art upon fully reading this disclosure that the structures disclosed herein can be used with various techniques and can be incorporated into various semiconductor devices and products. Furthermore, it should be noted that semiconductor device structures include a variety of numbers of components, and a single component shown in the figures may represent multiple components.

[0122] Figure 1 The illustration shows unit cell 11, that is, a portion of the semiconductor substrate 10 in the semiconductor device 100. As shown, parallel active regions 20 are spaced apart from each other and extend in the Y direction. Furthermore, parallel gate lines 30 are spaced apart from each other and extend in the X direction perpendicular to the Y direction. Example: The gate lines 30 are formed of a conductive material such as metal, and the gate lines 30 form the gate structure of the device 100.

[0123] Semiconductor device 100 may be a multi-gate device 100. In various embodiments, multi-gate device 100 may include a FinFET device, a GAA transistor, or other types of multi-gate device. Multi-gate device 100 is formed above substrate 10.

[0124] Multi-gate device 100 may include a P-type metal-oxide-semiconductor device 100 or an N-type metal-oxide-semiconductor multi-gate device 100. Due to the finned structure of the device, specific examples may be presented herein and referred to as FinFET device 100. An embodiment of a multi-gate transistor referred to herein as GAA device 100 is also presented herein. GAA device 100 includes any device in which a gate structure or a portion of a gate structure is formed on four sides of a channel region (e.g., surrounding a portion of the channel region). Devices presented herein also include embodiments in which the channel region is disposed in a nanosheet channel, nanowire channel, strip channel, and / or other suitable channel configuration. Here, the terms "nanosheet" or "nanosheet channel" are intended to include nanowire channel and strip channel configurations.

[0125] In some embodiments, substrate 10 may be a semiconductor substrate, such as a silicon substrate. Substrate 10 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. Depending on design requirements known in the art, substrate 10 may include various doping configurations. Substrate 10 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, substrate 10 may include compound semiconductors and / or alloy semiconductors. Furthermore, substrate 10 may, where appropriate, include epitaxial layers, be strainable to enhance performance, may include silicon-on-insulator (SOI) structures, and / or have other suitable enhancing features.

[0126] This document presents device embodiments that may have one or more channel regions (e.g., nanosheets) associated with a gate structure. For example, a vertically spaced stack of nanosheet channels may be provided. However, those skilled in the art will recognize that the teachings can be applied to a single channel (e.g., a single nanosheet) or any number of channels. Those skilled in the art will recognize other instances of semiconductor devices that may benefit from the manner of this disclosure.

[0127] In some embodiments, conductive interconnects are formed that contact the source / drain features. As used herein, "source / drain region" or "source / drain feature" may individually or collectively represent the source or drain, depending on the context.

[0128] Furthermore, source / drain interconnects to channel regions (such as nanosheet channels or nanosheet channel stacks) are provided with conductive paths that reduce resistance. Specifically, the method presented in this paper avoids or reduces dielectric obstruction to the direct, shortest conductive path from the source / drain interconnects to the channel regions, particularly the uppermost nanosheet channels.

[0129] The sidewalls of the source / drain interconnect can be insulated using dielectric pads or dielectric layers. To avoid or reduce dielectric resistance to the conductive path, embodiments herein provide for limiting the sidewall dielectric pads to a location at or above the uppermost nanosheet channel. This provides a direct lateral horizontal path from the source / drain interconnect to the uppermost nanosheet channel without dielectric resistance.

[0130] In some embodiments, the source / drain features are exposed by etching through an overlying dielectric material to form a cavity. The depth of the etching process is limited by performing a two-step etching process, which includes a first etching that stops above the source / drain features and a second etching that stops above the source / drain features. The selectivity of the second etching limits the etching of the source / drain features. For example, in some embodiments, the second etching may etch silicon nitride at a faster rate than silicon, silicon germanium, silicon phosphorus, or other source / drain feature materials. In some embodiments, the second etching may etch silicon oxide at a faster rate than silicon, silicon germanium, silicon phosphorus, or other source / drain feature materials. Because the depth of etching into the source / drain features is limited, the sidewalls of the cavity do not extend beyond the height of the uppermost channel region. Therefore, the sidewall pads formed in the cavity do not extend beyond the height of the uppermost channel region and are not located in the direct conductive path between the uppermost channel region and the interconnects formed in and below the cavity.

[0131] In some embodiments, the methods described herein prevent current crowding. Therefore, device performance is improved or enhanced compared to devices where dielectric sidewall pads block the conductive path.

[0132] In some embodiments, the etching of the epitaxial material is minimized during the process of forming the conductive interconnect cavities. Specifically, higher etch selectivity of oxides to silicon or higher etch selectivity of nitrides to silicon minimizes the etching of the epitaxial material.

[0133] By minimizing the epitaxial depression, subsequent dielectric deposition processes can position the bottom of the dielectric sidewall layer at or above the top nanosheet channel. Preventing the dielectric sidewall layer from being directly between the top nanosheet channel and the conductive interconnect provides lower resistance and prevents current buildup. Deeper etching of the epitaxial material would result in the dielectric sidewall layer being deposited at a height below the top nanosheet, blocking current flow into the top nanosheet and creating higher resistance. The embodiments described herein avoid forming such high-resistance structures.

[0134] Therefore, embodiments of this invention can position dielectric sidewall pads around the bottom edge of the conductive interconnect at the location of or above the top nanosheet. Embodiments of this invention can provide current flowing into the top nanosheet without current accumulation. Embodiments of this invention can provide lower resistance of the nanosheet channels. Embodiments of this invention can utilize etch-selective feature openings to provide a first etch rate for silicon oxide, a second etch rate for silicon nitride, and a third etch rate for the epitaxial material (such as silicon, silicon-germanium, silicon-phosphorus, etc.), wherein the first etch rate is faster or higher than the second etch rate, and the second etch rate is faster or higher than the third etch rate. This minimizes epitaxial depressions.

[0135] The embodiments disclosed herein offer advantages over the prior art. Although it should be understood that other embodiments may offer different advantages, not all advantages need not be discussed herein, nor are all specific advantages of all embodiments required.

[0136] refer to Figure 2 The diagram illustrates a method 1000 for manufacturing a semiconductor device 200 (such as a multi-gate device 100) according to various embodiments. The method 1000 is discussed below with reference to a GAA device having channel regions, where the channel regions may be referred to as nanosheets or nanochannels and may include various geometries (e.g., cylindrical, strip-shaped) and sizes. However, it should be understood that the form of method 1000 can be similarly applied to other types of multi-gate devices without departing from the scope of this disclosure. In some embodiments, method 1000 can be used to manufacture the device referenced above. Figure 1 The multi-gate device 100 is described. Therefore, one or more states discussed above with reference to the multi-gate device 100 can also be applied to method 1000. It should be understood that method 1000 includes steps characterized by a complementary metal-oxide-semiconductor (CMOS) technology process flow, and therefore, it is only briefly described herein. In addition, additional steps may be performed before, after, and / or during method 1000.

[0137] The following text is for reference only. Figures 3 to 26 Method 1000 is described as follows. Figures 3 to 26 A perspective view of the multi-gate device 200 is provided, along with... Figure 1 A cross-sectional view of a multi-gate device 200 whose planes are substantially parallel to the planes defined by the X-axis and Z-axis, and along the planes with... Figure 1 A cross-sectional view of a multi-gate device 200 whose planes defined by the Y-axis and Z-axis are substantially parallel, illustrating the various manufacturing stages according to method 1000.

[0138] Furthermore, the semiconductor device 200 may include various other devices and features, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random-access memory (SRAM), and / or other logic circuits, but simplified for a better understanding of the concepts of this disclosure. In some embodiments, the semiconductor device 200 includes a plurality of interconnectable semiconductor devices (e.g., transistors), including p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), etc. It should also be noted that the process steps of method 1000 (including any descriptions given with reference to the figures) are merely illustrative and are not intended to limit the specific enumerations in the claims.

[0139] In step S1010, method 1000 provides substrate 202, such as Figure 3 As shown in the figure. In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. Substrate 202 may include multiple layers, including conductive or insulating layers formed on the semiconductor substrate. Depending on design requirements known in the art, substrate 202 may include various doping configurations. For example, different doping distributions (e.g., p-wells, n-wells) may be formed in regions on substrate 202 designed for different device types (e.g., n-type field-effect transistors, p-type field-effect transistors). Suitable doping may include ion implantation and / or diffusion processes of dopants, such as boron (B) for p-wells and phosphorus (P) for n-wells. In some embodiments, substrate 202 includes a single-crystal semiconductor layer at least on its surface portion. Substrate 202 may include single-crystal semiconductor materials, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Alternatively, substrate 202 may include compound semiconductors and / or alloy semiconductors. In the illustrated embodiment, substrate 202 is made of crystalline Si.

[0140] like Figure 3 As shown, in step S1020, method 1000 ( Figure 2One or more epitaxial layers are formed over a substrate 202. In some embodiments, an epitaxial stack 212 is formed on the substrate 202. The epitaxial stack 212 includes an epitaxial layer 214 of a first composition inserted by an epitaxial layer 216 of a second composition. The first composition and the second composition may be different. Embodiments may include those that provide a first composition and a second composition with different oxidation rates and / or etch selectivity. In one embodiment, epitaxial layer 214 is SiGe and epitaxial layer 216 is silicon. In embodiments where epitaxial layer 214 comprises SiGe and epitaxial layer 216 comprises silicon, the silicon oxidation rate is less than the SiGe oxidation rate. It should be noted that Figure 3 The illustration shows three epitaxial layers 214 and 216, which are for illustrative purposes only and are not intended to limit the specific contents listed in the claims. It will be understood that any number of epitaxial layers can be formed in the epitaxial stack 212, the number of layers depending on the desired number of channel regions of the GAA device 200. In some embodiments, the number of epitaxial layers 216 is between 2 and 10, such as 6 or 7.

[0141] In some embodiments, epitaxial layer 214 has a thickness ranging from about 5 nanometers to about 15 nanometers. The thickness of epitaxial layer 214 may be substantially uniform. In some embodiments, epitaxial layer 216 has a thickness ranging from about 5 nanometers to about 15 nanometers. In some embodiments, the thickness of the stacked epitaxial layers 216 is substantially uniform. As described in more detail below, epitaxial layer 216 may be used as a channel region for a subsequently formed multi-gate device and has a thickness selected based on device performance considerations. Epitaxial layer 214 may be used to define the gap between adjacent channel regions for a subsequently formed multi-gate device and has a thickness selected based on device performance considerations.

[0142] By way of example, the epitaxial growth of the epitaxial stack 212 can be performed using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. In some embodiments, the epitaxial growth layer (such as epitaxial layer 216) comprises the same material as the substrate 202. In some embodiments, the epitaxially grown epitaxial layers 214 and 216 comprise materials different from the substrate 202. As stated above, in at least some embodiments, epitaxial layer 214 comprises epitaxially grown Si 1-x Ge xThe epitaxial layer 214 comprises an epitaxially grown silicon (Si) layer (where x is from about 10% to about 55%), and the epitaxial layer 216 comprises an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either epitaxial layer 214 or epitaxial layer 216 may comprise other materials, such as germanium, compound semiconductors (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), alloy semiconductors (such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and / or GaInAsP), or combinations thereof. As discussed, the materials of epitaxial layer 214 and epitaxial layer 216 may be selected based on providing different oxidation and etch selectivity properties. In many embodiments, epitaxial layer 214 and epitaxial layer 216 are substantially dopant-free (i.e., having about 0 cm⁻¹). -3 To approximately 1×10 17 cm -3 The concentration of exogenous dopant is controlled, for example, no intentional doping is performed during the epitaxial growth process. In some embodiments, the bottom and top layers of the epitaxial stack 212 are SiGe layers (not shown). In an alternative embodiment, the bottom layer of the epitaxial stack 212 is a Si layer, and the top layer of the epitaxial stack 212 is a SiGe layer (not shown).

[0143] like Figures 3 to 4 As shown, in step S1030, method 1000 ( Figure 2 Patterning the epitaxial stack 212 to form semiconductor fins 220. In some embodiments, step S1030 includes forming a masking layer 217 on the epitaxial stack 212, such as... Figure 3As shown in the diagram, mask layer 217 includes a first mask layer 218 and a second mask layer 219. The first mask layer 218 is an example of a pad oxide layer made of silicon oxide, which can be formed by thermal oxidation. The second mask layer 219 is an example of silicon nitride (SiN), which can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes, including low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition (PECVD). Mask layer 217 is patterned into a mask pattern using patterning steps including photolithography and etching. Step S1030 then involves patterning the epitaxial stack 212 via openings defined in the patterned mask layer 217 in an etching process such as dry etching (e.g., reactive-ion etching, RIE), wet etching, and / or other suitable processes. The stacked epitaxial layers 214 and 216 are thus patterned into fins 220. Although Figure 4 The diagram illustrates the formation of one fin 220, but any suitable number of fins can be formed. Grooves are etched between adjacent fins 220.

[0144] In various embodiments, each fin 220 includes an upper portion of staggered epitaxial layers 214 and 216, and a bottom portion formed by etching the substrate 202. Each fin 220 protrudes upward from the substrate 202 in the Z direction and extends longitudinally in the Y direction. The sidewalls of each fin 220 may be straight or inclined (not shown). Figure 4 In the middle, the additional fins will be spaced apart along the X direction. The fins 220 can have the same width or different widths.

[0145] like Figure 5 As shown, in step S1040, method 1000 ( Figure 2Shallow trench isolation (STI) features 221 (also referred to as STI features) are formed in the adjacent trenches of each fin 220 using a dielectric layer. The shallow trench isolation features 221 are formed by first filling the trenches around each fin 220 with a dielectric material layer to cover the top surface and sidewalls (not shown) of the fin 220. The dielectric material layer may include one or more dielectric materials. Suitable dielectric materials for the dielectric layer may include silicon oxide, silicon nitride, silicon carbide, fluorosilicate glass (FSG), low dielectric constant dielectric materials, and / or other suitable dielectric materials. The dielectric material can be deposited using any suitable technique, including thermal growth, flowable chemical vapor deposition (FCVD), high-density plasma chemical vapor deposition (HDP-CVD), PVD, ALD, and / or spin coating techniques. Next, the dielectric material layer is planarized using, for example, chemical mechanical planarization (CMP) until the top surface of the masking layer 217 is exposed, and the dielectric material layer is recessed to form a shallow trench isolation feature 221 (also known as an STI feature), such as... Figure 5 As shown in the illustration. In the illustrated embodiment, a shallow trench isolation feature 221 is formed on substrate 202. Any suitable etching technique can be used to recess the shallow trench isolation feature 221, including dry etching, wet etching, RIE and / or other etching methods, and in the example embodiment, anisotropic dry etching is used to selectively remove the dielectric material of the shallow trench isolation feature 221 without etching the fins 220. Masking layer 217 (e.g. Figure 4 The mask layer 217 (shown in the diagram) can also be removed before, during, and / or after the shallow trench isolation feature 221 is recessed. In some embodiments, the mask layer 217 is removed by a CMP process performed before the shallow trench isolation feature 221 is recessed. In some embodiments, the mask layer 217 is removed by an etchant used to recess the shallow trench isolation feature 221.

[0146] like Figure 6 As shown, in step S1050, method 1000 ( Figure 2A sacrificial gate structure 222 (dummy gate structure) is formed. The sacrificial gate structure 222 is formed above the portion of the fin 220 that will become the channel region. The sacrificial gate structure 222 may extend above multiple adjacent fins (not shown). The sacrificial gate structure 222 is located directly above and defines the channel region that will form the GAA device. Each component of the sacrificial gate structure 222 includes a sacrificial gate dielectric 223 and a sacrificial gate electrode 224 above the sacrificial gate dielectric 223. As shown, the sacrificial gate structures 222 extend longitudinally in the X direction and are spaced apart in the Y direction.

[0147] The sacrificial gate structure 222 is formed by first depositing a sacrificial gate dielectric layer on the fin 220. Then, a sacrificial gate electrode layer is deposited on the sacrificial gate dielectric layer and over the fin 220. The sacrificial gate dielectric layer includes silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the thickness of the sacrificial gate electrode layer is in the range of about 100 nanometers to about 200 nanometers. The sacrificial gate electrode 224 includes silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate dielectric layer is in the range of about 1 nanometer to about 5 nanometers. In some embodiments, a planarization step is performed on the sacrificial gate electrode layer. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD (including LPCVD and PECVD), PVD, ALD, or other suitable processes. A masking layer 225 is formed over the sacrificial gate electrode layer. The masking layer 225 may include a masking layer 226 such as silicon oxide and a masking layer 227 such as silicon nitride. Subsequently, a patterning step is performed on the mask layer 225 to pattern the sacrificial gate electrode layer and the sacrificial gate dielectric layer into a sacrificial gate structure 222, which includes a sacrificial gate dielectric 223 and a sacrificial gate electrode 224.

[0148] As shown in the figure, fins 220 are partially exposed between and on the opposite sides of the sacrificial gate structures 222 to define the source / drain (S / D) region. In embodiments of this disclosure, the source and drain are interchangeable and have substantially the same structure.

[0149] Still referencing Figure 6 In step S1060, method 1000 ( Figure 2 Spacers 230 are formed on the sidewalls of the sacrificial gate structure 222 and the sidewalls of the fin 220 by depositing spacer material and then etching. Spacers 230 may include spacer materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, each of the spacers 230 includes multiple layers, such as a liner layer 231 and a main spacer layer 232 on the sidewall of the liner layer 231.

[0150] By way of example, spacer 230 can be formed by depositing spacer material, including a pad material layer and a dielectric material layer, over the sacrificial gate structure 222 using processes such as subatmospheric CVD (SACVD), flowable CVD, ALD, PVD, or other suitable processes.

[0151] like Figure 7 As shown, in step S1070, after depositing the pad material layer and dielectric material layer, an etchback process is performed (e.g., anisotropically) to expose and remove the portion 220a (e.g., the S / D region) of the fin 220 adjacent to the sacrificial gate structure 222 and not covered by the sacrificial gate structure 222. The pad material layer and dielectric material layer may be retained on the sidewalls of the sacrificial gate structure 222 as gate sidewall spacers 230, and on the sidewalls of the fin as fin sidewall spacers 230. In some embodiments, the etchback process may include a wet etching process, a dry etching process, a multi-step etching process, and / or a combination thereof. The spacers 230 may have a thickness ranging from about 5 nanometers to about 20 nanometers.

[0152] Cross-reference Figure 7 and Figure 8 along Figure 7 The cross-sectional view (i.e., the X-section cross-sectional view) taken from line 8-8 in step S1070, method 1000 ( Figure 2 This will cause the portion of fin 220 not covered by sacrificial gate structure 222 to be recessed, forming a gap or recess 234 in the S / D region. It should be noted that... Figure 7 Only one adjacent portion of the sacrificial gate structure 222 and the fin 220 is shown, thus allowing for a clearer view. Figure 6 Etching of the S / D region between the sacrificial gate structure 222. Figure 8 For along Figure 7 The cross-sectional view of line 8-8 is shown, but it does not depict the three sacrificial gate structures 222 and the fins 220 located under the sacrificial gate structures 222.

[0153] like Figure 8 As most clearly shown, the stacked epitaxial layers 214 and 216 are etched to the bottom gap surface 233 formed by the fins 220. In many embodiments, step S1070 forms the gaps 234 by a suitable etching process, such as a dry etching process, a wet etching process, or a combination thereof. As a result of the etching process, the fin segments 235 of the upper portion of the fins 220 are defined and separated from each other by the gaps 234.

[0154] like Figure 8 The text further illustrates that method 1000 ( Figure 2This includes lateral etching of the second epitaxial layer 216 in step S1080. In an example embodiment, the SiGe etch-back process is removed to create a lateral recess in the epitaxial layer 216. Thus, a recess 2161 is formed laterally adjacent to the epitaxial layer 216 and vertically adjacent to the epitaxial layer 214.

[0155] like Figure 9 As shown, method 1000 ( Figure 2 This includes step S1090, in which an internal spacer 2162 is formed in a recess 2161 that is laterally adjacent to the epitaxial layer 216. Figure 9 This is an X-section cross-sectional view. In the example embodiment, the internal spacer 2162 can be formed of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonoxynitride, and / or other suitable dielectric materials. The internal spacer 2162 can be formed by ALD or any other suitable method. As shown, after depositing the material forming the internal spacer 2162, the material of the internal spacer 2162 can be trimmed from the sidewalls of the epitaxial layer 214.

[0156] refer to Figure 10 Method 1000 ( Figure 2 Continuing in step S1100, an isolation layer 300 is formed over the semiconductor substrate 202. Specifically, the isolation layer 300 is formed on the bottom gap surface 233 of the gap 234. In an example embodiment, the isolation layer 300 is formed by an atomic layer deposition process.

[0157] Figure 10 This is an X-section cross-sectional view. As shown, the isolation layer 300 can completely cover the bottom gap surface 233, so that any part of the semiconductor substrate 202 between the bottom internal spacers 2162 is covered. Therefore, each part of the isolation layer 300 extends from one sacrificial gate structure 222 to the adjacent sacrificial gate structure 222.

[0158] In an example embodiment, the isolation layer 300 is a dielectric material with a large band gap. For example, the isolation layer 300 may be formed of a material with a band gap of at least 4 eV, such as at least 4.5 eV, at least 5 eV, at least 5.5 eV, at least 6 eV, at least 6.5 eV, at least 7 eV, at least 7.5 eV, at least 8 eV, at least 8.5 eV, or at least 8.9 eV.

[0159] In some embodiments, the isolation layer 300 is formed of silicon nitride (SiN) and has a band gap of about 5 eV. In some embodiments, the isolation layer 300 is formed of silicon oxide (SiO) and has a band gap of about 8.9 eV. In example embodiments, the isolation layer 300 is formed of silicon oxide, silicon nitride, or a combination thereof.

[0160] In an example embodiment, the isolation layer comprises multiple sublayers, making the isolation layer a multi-film structure. These sublayers can be deposited individually. The thickness and order of the sublayers within the multi-film structure can be designed to provide a desired bandgap, a desired dielectric constant, and facilitate epitaxial growth of materials forming source / drain regions over the isolation layer, as described below.

[0161] In the example embodiment, the isolation layer 300 has a small dielectric constant (or relative permittivity). In the example embodiment, the isolation layer has a dielectric constant of less than 10, such as less than 7.5, less than 5, or less than 4.

[0162] Although Figures 9 to 10 An isolation layer 300 is described after the formation of the internal spacer 2162, but it is conceivable that the isolation layer 300 and the internal spacer 2162 are formed simultaneously.

[0163] In step S1110, the method can continue to form source / drain characteristics 400, such as Figure 11 As shown in the image. Figure 11 This is an X-section cross-sectional view. In an example embodiment, the source / drain feature 400 is formed by epitaxial growth. For example, step S1110 may include selectively growing epitaxial material over the isolation layer 300 to form the source / drain feature 400. In an example embodiment, the source / drain feature 400 is a strained source / drain feature 400.

[0164] Epitaxial materials may include one or more layers of Si, SiP, SiC, and SiCP for n-type channel FETs, or one or more layers of Si, SiGe, and Ge for p-type channel FETs. For p-type channel FETs, the source / drain may also contain boron (B). The source / drain epitaxial layers can be formed using epitaxial growth methods such as CVD, ALD, or molecular beam epitaxy.

[0165] exist Figure 12 In this method 1000, step S1120 includes forming a dielectric 450 over the source / drain feature 400. Specifically, the dielectric 450 fills the gap 234. In an example embodiment, the dielectric 450 is a first interlayer dielectric layer (ILD). The dielectric 450 may be silicon oxide or other suitable dielectric material.

[0166] Figure 12 This is a cross-sectional view of the X-section. Although Figure 12 Not shown, but a pad may be formed above the source / drain feature 400 before the deposition of dielectric 450. In some embodiments, the pad may be silicon nitride or other suitable material.

[0167] like Figure 13 The diagram further illustrates that method 1000 includes step S1130, exposing and removing the sacrificial gate structure 222. Specifically, a chemical mechanical planarization process may be performed to remove the masking layer 225 and expose the sacrificial gate electrode 224. Furthermore, the sacrificial gate electrode 224 is removed to form a gate cavity 499. As shown, the gate cavity 499 is defined by spacers 230 and an uppermost epitaxial layer 214. Figure 13 This is a cross-sectional view of the X-section.

[0168] exist Figure 14 In method 1000, in step S1140, the second epitaxial layer 216 is removed. Therefore, gaps 2169 are formed between the first epitaxial layers 214. In this way, the first epitaxial layers 214 are formed as vertically spaced semiconductor nanosheets 560. Figure 14 This is a cross-sectional view of the X-section.

[0169] exist Figure 15 In the method 1000, step S1150 includes completing a replacement metal gate process to form a gate structure 500, such as gate structure 501, gate structure 502 and gate structure 503. Figure 15 This is a cross-sectional view of the X-section.

[0170] In an example embodiment, the replacement metal gate process includes forming a gate dielectric layer 540 in the gate cavity 499 and the gap 2169, and forming a gate electrode material 550 over the gate dielectric layer 540 to fill the gate cavity 499 and the gap 2169.

[0171] Example: A gate dielectric layer 540 is conformally deposited in the gate cavity 499 and the gap 2169. The gate dielectric layer 540 can be formed on the semiconductor nanosheet 560, and the gate electrode material 550 can be formed on the gate dielectric layer 540. Thus, each semiconductor nanosheet 560 is encapsulated in the gate dielectric layer 540 and surrounded by the gate electrode material 550.

[0172] According to some embodiments, the gate dielectric layer 540 comprises silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric layer 540 is a high dielectric constant material, and in these embodiments, the gate dielectric layer 540 may have a dielectric constant (k value) greater than about 7.0, and may include metal oxides or silicates such as Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. Methods for forming the gate dielectric layer 540 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0173] Gate electrode material 550 is deposited above gate dielectric layer 540 and fills the remainder of gate cavity 499. Gate electrode material 550 may be a metal-containing material, such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multiple layers thereof. For example, although a single gate electrode material is shown, any number of work function tuning layers may be deposited.

[0174] like Figure 15 As shown, the replacement metal gate process further includes removing excess portions of the gate dielectric layer 540 and gate electrode material 550 located above the top surface of the interlayer dielectric 450. For example, a planarization process, such as a CMP process, can be performed to remove the excess portions of the gate dielectric layer 540 and gate electrode material 550. Thus, device 200 has an upper surface 599. The remaining portions of the gate dielectric layer 540 and gate electrode material 550 thus form the replacement gate structure 500 of the resulting device 200. The gate dielectric layer 540 and gate electrode material 550 can be collectively referred to as a "gate," "gate stack," or "gate structure." Each gate structure 500 can extend along the sidewalls of the channel region of the fin structure.

[0175] exist Figure 16 The method may include forming a dielectric material over the device 200 in step S1160. For example, a layer 600, such as a contact etch stop layer (CESL) or a capping layer, may be formed over the upper surface 599. In an example embodiment, layer 600 has a vertical thickness of 1 to 5 nanometers in the Z direction. Figure 16 This is a cross-sectional view of the X-section.

[0176] Step S1160 further includes forming a second interlayer dielectric layer 700 over layer 600. In some embodiments, the second interlayer dielectric layer 700 is silicon oxide or other suitable material. In some embodiments, the second interlayer dielectric layer 700 and the first interlayer dielectric 450 are the same material, such as silicon oxide.

[0177] exist Figure 17 and Figure 18 In the method 1000, step S1171 includes performing a first etching process to form an upper opening 720 above the selected source / drain feature 400. Figure 17 This is a cross-sectional view of the X-section, and Figure 18 for Figure 17 The manufacturing stage and a Y-section view along the two source / drain features 400. As shown, the upper opening 720 is defined by the sidewall 730 formed by the interlayer dielectric layer 700 and layer 600.

[0178] It should be noted that, Figure 17 and Figure 18 In this configuration, dielectric pad 440 is located below and around dielectric 450, that is, dielectric pad 440 is located between dielectric 450 and source / drain features 400 and between dielectric 450 and gate dielectric layer 540. In some embodiments, dielectric pad 440 and layer 600 are made of the same material, such as silicon nitride.

[0179] In the example embodiment, the first etching process has etch selectivity, thus removing layer 600 at a faster or higher etch rate than dielectric 450. In the example embodiment, the first etching process has etch selectivity, thus removing layer 600 at a faster or higher etch rate than interlayer dielectric layer 700. Utilizing the selected etch selectivity, as shown, the first etching process can be performed to stop at the upper surface 599 of dielectric 450.

[0180] like Figure 18 As shown, in the example embodiment, the source / drain feature 400 may include an n-type epitaxial material source / drain feature 401 and a p-type epitaxial material source / drain feature 402.

[0181] exist Figure 19 and Figure 20 In the method 1000, step S1172 includes performing a second etching process to form a lower opening 740 above the selected source / drain feature 400. Figure 19 This is a cross-sectional view of the X-section, and Figure 20 for Figure 19 The manufacturing stage and the Y-section cross-section of the two source / drain features at 400.

[0182] As shown in the figure, the second etching process etches the dielectric 450 to form a lower opening 740 defined by sidewalls 750. The upper opening 720 and the lower opening 740 together define an opening 780 above the selected source / drain feature 400. Similarly, the lower sidewall 750 and the upper sidewall 730 together define an opening sidewall 790.

[0183] The second etching process may stop on the source / drain feature 400 and / or on the pad 440 surrounding the source / drain feature 400.

[0184] In the example embodiment, the second etching process has etch selectivity, thus removing the dielectric 450 and / or pad 440 at a faster or higher etch rate than the material of the source / drain feature 400. Utilizing the selected etch selectivity, the second etching process can be performed to stop at the pad 440 and / or dielectric 450 while minimizing material removal from the source / drain feature 400.

[0185] In summary, the first etching process in step S1171 and the second etching process in step S1172 represent step S1170, which forms an opening 780 over the selected source / drain feature 400. As described, the first etching process selectively removes layer 600 relative to dielectric 450 and stops at dielectric 450. Furthermore, the second etching process selectively removes dielectric 450 or pad 440 relative to the epitaxial source / drain feature 400.

[0186] In some embodiments, a first etching process is performed at a first temperature and a first power, and a second etching process is performed at a second temperature and a second power, wherein the first temperature is lower than the second temperature and the first power is greater than the second power.

[0187] For example, in some embodiments, the first etching process is a soft-landing etching process. In some embodiments, the first etching process is a plasma etching process performed using a gas mixture including C4F8, C4F6, O2, Ar, He, N2, and / or other suitable gases. In some embodiments, the first etching process is a plasma etching process performed at a first pressure of 3 millitorr (mT) to 100 millitorr. In some embodiments, the first etching process is a plasma etching process performed at a first power of 0 watt (W) to 500 watts. In some embodiments, the first etching process is a plasma etching process performed at a first plasma frequency of 0.8 megahertz (MHz) to 60 MHz.

[0188] In some embodiments, the second etching process is high-temperature plasma etching. For example, in some embodiments, the wafer temperature during the second etching process is 80°C to 200°C. In some embodiments, the second etching process is a plasma etching process performed with a gas mixture including C4F8, C4F6, O2, Ar, He, N2, and / or other suitable gases. In some embodiments, the second etching process is a plasma etching process performed at a second pressure of 3 mTorr to 100 mTorr. In some embodiments, the second etching process is a plasma etching process performed with a second power of 0 watts to 500 watts. In some embodiments, the second etching process is a plasma etching process performed with a second plasma frequency of 0.8 MHz to 60 MHz.

[0189] In some embodiments, the second power is greater than the first power. For example, the second power may be 20 to 150 watts greater than the first power.

[0190] In some embodiments, such as for higher aspect ratio etching, the second plasma frequency is lower than the first plasma frequency. For example, the first plasma frequency may be from 27 MHz to 40 MHz, and the second plasma frequency may be from 2 MHz to 40 MHz.

[0191] Figure 21 For being in Figures 19 to 20 A perspective view of the device 200 during the manufacturing stage. As shown, a plurality of openings 780 are formed above the device 200, including a first opening 781 similar to the opening 780 located above the n-type epitaxial material source / drain feature 401 and the p-type epitaxial material source / drain feature 402.

[0192] exist Figure 21 In the figure, opening 780 is depicted extending deeper into the space between the two source / drain features 401 and 402. However, as shown, the opening sidewall 790 still extends downward to and terminates at source / drain features 401 and 402. Openings 782 and 783 may be separated from opening 781 in the Y direction and separated from each other in the X direction.

[0193] exist Figure 22 In this method 1000, step S1181 involves depositing a dielectric material 800 over the device 200. Specifically, the dielectric material 800 may be conformally deposited over an opening 780, including on the sidewalls 790 of the opening 780 and over the exposed surfaces 799 of selected source / drain features 400. In some embodiments, the dielectric material is silicon nitride or other suitable dielectric material. Figure 22 This is a cross-sectional view of the X-section.

[0194] exist Figure 23 In this method 1000, step S1182 includes etching dielectric material 800 over the top of the second interlayer dielectric layer 700 and over the surface 799 of the selected source / drain feature 400. For example, directional etching can be performed such that dielectric material 800 remains on the sidewall 790 of the opening 780. After etching, dielectric material 800 can be formed in a ring shape and lined with the periphery of the opening 780. Figure 23 This is a cross-sectional view of the X-section.

[0195] In some embodiments, the dielectric material 800 is a silicon nitride redistribution (SNR) layer or pad.

[0196] like Figure 23As shown, the dielectric material 800 extends downward in the vertical Z direction to and terminates at the bottom edge 801. The bottom edge 801 is located in the Z direction at a first vertical distance or height H1 from the horizontal plane 209 defined by, for example, device 200.

[0197] Furthermore, the semiconductor nanosheet 560 includes a topmost nanosheet 561, which has a topmost surface 565 in the Z direction at a second vertical distance or height H2. Because the etching process used to form the opening 780 minimizes the amount of recess in the source / drain feature 400, the first distance H1 is equal to or greater than the second distance H2. For example, the first distance H1 may be greater than the second distance H2 by a third vertical distance or height H3. In some embodiments, the third distance H3 is 0 nanometers to 12 nanometers, such as 1 nanometer to 6 nanometers.

[0198] In summary, the deposition process of step S1181 and the etching process of step S1182 represent step S1180, which forms a sidewall layer or side pad 800 in the opening 780 above the selected source / drain feature 400 and on the opening sidewall 790.

[0199] exist Figure 24 In the method 1000, step S1190 is to form a conductive interconnect 900 in the opening 780. Figure 25 for Figure 24 Y-section view of device 200.

[0200] As shown in the figure, step S1190 may include silicided the upper portion 910 of the source / drain feature 400 and depositing conductive material over the source / drain feature 400 to form a conductive interconnect 900 or a source / source contact. In some embodiments, the conductive material includes a metal, such as tungsten (W) or other suitable materials. Figure 24 This is a cross-sectional view of the X-section.

[0201] exist Figure 26 In this method 1000, further processing is performed in step S1200. Figure 26 This is a perspective view of device 200. For example, further processing may include forming additional dielectric layers 920 and 930 over device 200. Additionally, an additional metal interconnect layer 950 may be formed. Further processing may include other back end of line (BEOL) processes.

[0202] Figure 27This is a schematic image of a semiconductor device 200 formed according to method 1000 using a transmission electron microscope (TEM). As shown, the device 200 includes three nanosheets: a top or uppermost nanosheet 561, a bottom or lowermost nanosheet 563, and a middle nanosheet 562.

[0203] In some embodiments, the uppermost nanosheet 561, the middle nanosheet 562, and the lowermost nanosheet 563 may independently have a vertical height of 3 to 15 nanometers and a lateral width of 9 to 100 nanometers.

[0204] Furthermore, the device 200 includes a gate, wherein the gate includes an uppermost or top inner gate portion 551 located directly below the nanosheet 561, a middle inner gate portion 552 located directly below the nanosheet 562, and a lowermost inner gate portion 553 located directly below the nanosheet 563. Additionally, the gate includes an outer gate portion 555 located directly above the nanosheet 562.

[0205] The outer gate portion 555 has a lateral width W5 in the Y direction. In some embodiments, the width W5 is 9 nanometers to 100 nanometers. The outer gate portion 555 has a vertical height H5 in the Z direction. In some embodiments, the height H5 is 5 nanometers to 30 nanometers. Each inner gate portion 551, inner gate portion 552, and inner gate portion 553 may independently have a vertical height of 3 nanometers to 15 nanometers and a lateral width of 9 nanometers to 100 nanometers.

[0206] The uppermost surface 565 is located at a vertical distance H3 from the bottom edge 801 of the side liner 800.

[0207] In some embodiments, the uppermost inner gate portion 551 is located at a depth of 8 nanometers to 16 nanometers below the upper surface 565. In some embodiments, the middle inner gate portion 552 is located at a depth of 20 nanometers to 30 nanometers below the upper surface 565. In some embodiments, the lowermost inner gate portion 553 is located at a depth of 32 nanometers to 50 nanometers below the upper surface 565.

[0208] In some embodiments, the middle height of the uppermost inner gate portion 551 is located at a depth of 3 to 22 nanometers below the upper surface 565.

[0209] like Figure 26 As shown, the upper portion 910 of the source / drain feature 400 is converted to silicide. The upper portion 910 may include titanium, titanium silicide, and titanium nitride. In some embodiments, the upper portion 910 may have a 5 angstrom (Å) diameter. (Up to 120 angstroms in vertical height.)

[0210] like Figure 26 The diagram further illustrates that each inner gate portion is surrounded by an internal spacer 2162. In some embodiments, the internal spacer 2162 is formed of SiO, SiN, SiOC, SiOCN, or other suitable materials. In some embodiments, the internal spacer 2162 has a lateral width of 1 nanometer to 12 nanometers.

[0211] In the embodiments described herein, the source / drain feature 400 is exposed by performing a two-step etching process to prevent blockage of the conductive flow path between the metal interconnect 900 to the source / drain feature 400 and the uppermost nanosheet 561. The second etching step selectively etches the dielectric (dielectric 450 and / or pad 440) at a faster rate than the silicon material of the source / drain feature 400. Therefore, the sidewall 790 of the opening 780 terminates at the source / drain feature 400, rather than extending into it. Then, before forming the metal interconnect 900, a side pad 800 (SNR layer) is formed in the opening 780 on the sidewall 790. The side pad 800 terminates at a bottom edge 801, which is located at or above the height of the uppermost nanosheet 561. Therefore, the side liner 800 will not be located in the direct flow path between the metal interconnect 900 and the uppermost nanosheet 561. For example, the side liner 800 will not be located in the horizontal flow path between the metal interconnect 900 and the uppermost nanosheet 561.

[0212] In one embodiment, a method of manufacturing a semiconductor device is provided, including forming an epitaxial feature adjacent to a gate, wherein the gate is at a first vertical height above the uppermost surface of a semiconductor fin. The method includes forming a first dielectric material over the epitaxial feature, forming a capping layer over the first dielectric material, forming a second dielectric material over the capping layer, forming an opening with sidewalls over the epitaxial feature, and forming a side layer over the sidewalls of the opening, wherein the side layer extends to a lowest edge at a second vertical height, the second vertical height being located at or above the first vertical height.

[0213] In some embodiments of the method, forming an opening over an epitaxial feature includes performing a first etching process that selectively removes a capping layer relative to a first dielectric material, wherein the first etching process stops at the first dielectric material, and performing a second etching process that selectively removes the first dielectric material relative to the epitaxial feature.

[0214] In some embodiments of the method, a first etching process is performed at a first temperature and a first power, and a second etching process is performed at a second temperature and a second power, wherein the first temperature is lower than the second temperature and the first power is greater than the second power.

[0215] In some embodiments, the method further includes forming a pad over the epitaxial feature, and forming an opening over the epitaxial feature includes exposing the pad.

[0216] In some embodiments of the method, the cover layer and the pad are made of the same material.

[0217] In some embodiments, the method further includes converting the upper portion of the epitaxial feature into a metal silicide and forming a metal contact in the opening.

[0218] In some embodiments of the method, forming an opening over an epitaxial feature includes performing a first etching process that selectively removes a capping layer, wherein the first etching process stops at a first dielectric material, and performing a second etching process that stops at the epitaxial feature.

[0219] In some embodiments of the method, the second vertical height is 0 to 12 nanometers higher than the first vertical height.

[0220] In some embodiments of the method, forming a side layer above the sidewall of the opening includes depositing the side layer above the top surface of the second dielectric material, above the sidewall, and above the top surface of the epitaxial feature, and performing directional etching to remove the side layer from the top surface of the second dielectric material and the top surface of the epitaxial feature.

[0221] In some embodiments of the method, the side layer is a silicon nitride redistribution layer.

[0222] In another embodiment, a method of manufacturing a semiconductor device is provided, including forming a structure over a semiconductor substrate, forming a first dielectric material over the structure, forming a capping layer over the first dielectric material, forming a second dielectric material over the capping layer, performing a first etching process that selectively removes the capping layer compared to the first dielectric material, wherein the first etching process stops at the first dielectric material, and performing a second etching process that selectively removes the first dielectric material compared to the structure, wherein the second etching process stops at the structure.

[0223] In some embodiments, the method further includes forming a liner over the structure.

[0224] In some embodiments of the method, the liner and the cover layer are made of the same material.

[0225] In some embodiments of the method, a semiconductor substrate defines a horizontal plane. A structure is adjacent to a fin structure, the fin structure having a first vertical distance above the horizontal plane at its uppermost semiconductor surface. A first etching process and a second etching process form a cavity above the structure, and the cavity has sidewalls formed of a first dielectric material, a capping layer, and a second dielectric material. The method further includes forming a silicon nitride redistribution layer above the sidewalls of the cavity, the silicon nitride redistribution layer extending to its lowest edge at a minimum vertical distance from the horizontal plane, and the minimum vertical distance being greater than the first vertical distance.

[0226] In some embodiments, the method further includes converting the upper portion of the structure into a metal silicide and forming metal contacts in the cavity.

[0227] In another embodiment, a semiconductor device includes a multi-gate structure above a semiconductor substrate and including a top inner gate portion, a source / drain feature laterally adjacent to the multi-gate structure, an interlayer dielectric layer above the multi-gate structure and the source / drain feature, a source / drain contact extending through the interlayer dielectric layer to the source / drain feature, and a side pad on the source / drain contact extending to a lowest edge that contacts the source / drain feature, wherein the lowest edge is located above the top inner gate portion.

[0228] In some embodiments of the semiconductor device, the top inner gate portion has an uppermost surface and the lowest edge is located above the uppermost surface of the top inner gate portion.

[0229] In some embodiments of a semiconductor device, a multi-gate structure has an outer gate portion above a top inner gate portion, wherein the uppermost surface of the outer gate portion is spaced apart from the uppermost surface of the top inner gate portion, and the lowest edge of the side pad is located below the uppermost surface of the multi-gate structure.

[0230] In some embodiments of the semiconductor device, the side pads are silicon nitride redistribution layers.

[0231] In some embodiments of a semiconductor device, a multi-gate structure has an outer gate portion above a top inner gate portion, a top nanosheet separating the outer gate portion from the top inner gate portion, the outer gate portion having a vertical thickness of 5 nanometers to 30 nanometers, the top nanosheet having a vertical thickness of 3 nanometers to 15 nanometers, and the top inner gate portion having a vertical thickness of 3 nanometers to 15 nanometers.

[0232] In another embodiment, a semiconductor device includes a source / drain feature adjacent to a gate, wherein the gate is located at a first vertical height above the uppermost surface of a semiconductor fin. The semiconductor device also includes a first dielectric material above the source / drain feature, a capping layer above the first dielectric material, a second dielectric material above the capping layer, and an opening having sidewalls extending through the second dielectric material, the capping layer, and the first dielectric material to the source / drain feature. The semiconductor device also includes side pads on the sidewalls of the opening, wherein the side pads extend to a lowest edge contacting the source / drain feature, the lowest edge being located at a second vertical height, and the second vertical height being at or above the first vertical height.

[0233] In some embodiments of the semiconductor device, the second vertical height is 0 to 12 nanometers higher than the first vertical height.

[0234] In another embodiment, a semiconductor device includes a source / drain feature located above a semiconductor substrate and adjacent to a fin structure, a first dielectric material located above the source / drain feature, a capping layer located above the first dielectric material, a second dielectric material located above the capping layer, and a source / drain contact extending through the second dielectric material, the capping layer, and the first dielectric material and electrically connected to the source / drain feature. The semiconductor device also includes a sidewall of the source / drain contact extending to a lowest edge that contacts the source / drain feature, wherein the lowest edge is located above the uppermost semiconductor surface of the fin structure.

[0235] In some embodiments of the semiconductor device, the semiconductor substrate defines a horizontal plane, the uppermost semiconductor surface of the fin structure is located at a first vertical distance above the horizontal plane, and the lowest edge to which the side pad extends is at a minimum vertical distance from the horizontal plane, and the minimum vertical distance is greater than the first vertical distance.

[0236] In some embodiments of the semiconductor device, the semiconductor device further includes a metal silicide layer located between the source / drain features and the source / drain contacts, wherein side pads contact the top surface of the metal silicide layer.

[0237] The foregoing outlines features of some embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized by comprising: including: a multi-gate structure over a semiconductor substrate and comprising a top inner gate portion; a source / drain feature laterally adjacent to the multi-gate structure; an interlayer dielectric layer over the multi-gate structure and the source / drain feature; a source / drain contact extending through the interlayer dielectric layer to the source / drain feature; and a side spacer over the source / drain contact and extending to a lowest edge in contact with the source / drain feature, wherein the lowest edge is over the top inner gate portion. wherein:

2. The semiconductor device according to claim 1, wherein the top inner gate portion has an uppermost surface; and the lowest edge is over the uppermost surface of the top inner gate portion. wherein:

3. The semiconductor device according to claim 1, wherein the multi-gate structure has an outer gate portion over the top inner gate portion, wherein the outer gate portion has an uppermost surface spaced apart from the uppermost surface of the top inner gate portion; and the lowest edge of the side spacer is below the uppermost surface of the multi-gate structure. wherein:

4. The semiconductor device according to claim 1, wherein the multi-gate structure has an outer gate portion over the top inner gate portion; and a top nanosheet separates the outer gate portion from the top inner gate portion. wherein:

5. The semiconductor device according to claim 4, wherein the outer gate portion has a vertical thickness of 5 nm to 30 nm; the top nanosheet has a vertical thickness of 3 nm to 15 nm; and the top inner gate portion has a vertical thickness of 3 nm to 15 nm. including:

6. A semiconductor device, characterized by comprising: a source / drain feature adjacent to a gate, wherein the gate is at a first vertical height over an uppermost surface of a semiconductor fin; a first dielectric material over the source / drain feature; a cap layer over the first dielectric material; a second dielectric material over the cap layer; an opening extending through the second dielectric material, the cap layer, and the first dielectric material to the source / drain feature, wherein the opening has a sidewall; and a side spacer over the sidewall of the opening, wherein the side spacer extends to a lowest edge in contact with the source / drain feature, the lowest edge is at a second vertical height, and the second vertical height is at or above the location of the first vertical height. wherein the second vertical height is 0 nm to 12 nm higher than the first vertical height.

7. The semiconductor device according to claim 6, wherein including:

8. A semiconductor device, characterized by comprising: a source / drain feature over a semiconductor substrate and adjacent to a fin structure; a first dielectric material over the source / drain feature; a cap layer over the first dielectric material; a second dielectric material over the cap layer; a source / drain contact extending through the second dielectric material, the cap layer, and the first dielectric material and electrically connected to the source / drain feature; and a side spacer over a sidewall of the source / drain contact and extending to a lowest edge in contact with the source / drain feature, wherein the lowest edge is over an uppermost semiconductor surface of the fin structure. wherein: the semiconductor substrate defines a horizontal plane; 9. The semiconductor device according to claim 8, wherein the uppermost semiconductor surface of the fin structure is at a first vertical distance above the horizontal plane; ​ ​ The lowest edge to which the side spacer extends is a minimum vertical distance from the horizontal plane; and The minimum vertical distance is greater than the first vertical distance.

10. The semiconductor device according to claim 8, wherein Further comprising a metal silicide layer between the source / drain feature and the source / drain contact, wherein the side spacer contacts a top surface of the metal silicide layer.

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