Middle-high voltage shielding grid power MOSFET layout and MOSFET
By setting spaced trench regions in the layout of the shielded gate power MOSFET and optimizing the trench interval distance, the risk of leakage current was resolved, and charge balance optimization and breakdown voltage improvement were achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-08
- Publication Date
- 2026-03-17
AI Technical Summary
In existing shielded gate power MOSFET layout designs, when the source polysilicon electrode, gate, and source are connected and isolated, the trench distance between the termination region and the cell region is 0, which increases the risk of leakage.
In the layout of a shielded gate power MOSFET, multiple first trench regions and second trench regions are set at intervals. The second trench region has a gate contact hole region, and the first trench region is on the periphery. The trench region between the terminal region and the nearest cell region is set with a first distance to optimize charge balance and avoid tip discharge.
By optimizing the trench interval distance, charge balance is improved, tip discharge is avoided, breakdown voltage is increased, and IDSS is optimized.
Smart Images
Figure CN224007000U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor technology, and in particular relates to a layout of a medium- and high-voltage shielded gate power MOSFET and the MOSFET itself. Background Technology
[0002] Current shielded-gate power MOSFET layout designs require the source polysilicon electrode, gate, and source to be connected separately, and the source polysilicon electrode to be isolated from the gate. Before design optimization, such as... Figure 1 As shown, the distance between the first trench area, which is closest to the cell area, and the second trench area of the cell area is 0, which increases the risk of leakage. Summary of the Invention
[0003] To solve or alleviate the above-mentioned technical problems, in a first aspect, embodiments of this application provide a layout of a medium-high voltage shielded gate power MOSFET, including a cell region and a termination region;
[0004] The terminal region includes a plurality of first trench regions spaced apart, and the cell region includes a plurality of second trench regions spaced apart, wherein a gate contact hole region is provided in the second trench region;
[0005] The first trench area is located outside the second trench area;
[0006] There is a first distance between the first trench region of the terminal region that is closest to the cell region and the second trench region of the cell region.
[0007] In a preferred embodiment of this application, the distance between the second trenches is a second distance, and the first distance is less than the second distance.
[0008] In a preferred embodiment of this application, the first distance is 65%-75% of the second distance.
[0009] Secondly, embodiments of this application provide a medium-to-high voltage shielded gate power MOSFET, fabricated using the layout described in any one of the first aspects.
[0010] Compared with the prior art, the medium-high voltage shielded gate power MOSFET layout and MOSFET provided in this application can optimize charge balance and avoid tip discharge by changing the distance between the first trench region closest to the cell region and the second trench region of the cell region, thereby optimizing IDSS and improving breakdown voltage. Attached Figure Description
[0011] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:
[0012] Figure 1 This is a layout of a medium-to-high voltage shielded gate power MOSFET in the prior art;
[0013] Figure 2 This is a layout of a medium-to-high voltage shielded gate power MOSFET provided in an embodiment of this application. Detailed Implementation
[0014] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.
[0015] like Figure 2 As shown, this application embodiment provides a medium-to-high voltage shielded gate power MOSFET layout, including cell regions and termination regions;
[0016] The terminal region includes a plurality of first communication regions 1 spaced apart, and the cell region includes a plurality of second communication regions 1 spaced apart. A gate contact hole region 3 is provided in the second communication region 2.
[0017] The first communication area 1 is located outside the second communication area 2;
[0018] The first communication area 1, which is closest to the cell area in the terminal area, and the second communication area 2 in the cell area have a first distance D1 between them.
[0019] Preferably, the distance between the second communication points 2 is the second distance D2, and the first distance D1 is less than the second distance D2.
[0020] Preferably, the first distance D1 is 65%-75% of the second distance D2.
[0021] Secondly, embodiments of this application provide a medium-to-high voltage shielded gate power MOSFET, fabricated using the layout described in any one of the first aspects.
[0022] This application provides a medium-to-high voltage shielded gate power MOSFET layout and MOSFET. By changing the distance between the first trench region 1, which is closest to the cell region, and the second trench region 2, which is closest to the cell region, the charge balance can be optimized, tip discharge can be avoided, thereby optimizing IDSS and improving breakdown voltage.
[0023] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A medium-high voltage shielded gate power MOSFET layout, characterized in that, a cell region and a terminal region; the terminal region comprises a plurality of first trench regions arranged at intervals, and the cell region comprises a plurality of second trench regions arranged at intervals, and the second trench regions are provided with gate contact hole regions; the first trench regions are arranged at the periphery of the second trench regions; the first distance between the first trench region closest to the cell region of the terminal region and the second trench region of the cell region.
2. A medium-high voltage shielded gate power MOSFET layout as defined in claim 1, wherein, the distance between the second trenches is a second distance, and the first distance is less than the second distance.
3. A medium-high voltage shielded gate power MOSFET layout as claimed in claim 2, characterized in that, the first distance is 65%-75% of the second distance.
4. A medium-high voltage shielded gate power MOSFET, characterized by, a layout is prepared by any one of claims 1 to 3.