High-mobility array circuit and liquid crystal display panel
By connecting adjacent row gate scan lines in the liquid crystal display panel to form a dual gate scan line, and connecting the source data lines at odd and even intervals, a high mobility of the liquid crystal display panel is achieved, improving charging efficiency and display performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-17
- Publication Date
- 2026-03-20
AI Technical Summary
Due to material limitations, existing LCD panels have limited mobility improvements, resulting in a decline in display quality.
By electrically connecting adjacent row gate scan lines to form a dual-gate scan line, and by electrically connecting the source data lines to the sources of the column pixels on both sides at odd and even intervals, data writing and charging of two rows of pixels can be achieved in a single scan.
It greatly improves charging efficiency, doubles the number of display lines at the same frequency, and doubles the frequency at the same resolution.
Smart Images
Figure CN224020433U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the drive scanning technical field of liquid crystal display panel, especially relates to an array circuit and liquid crystal display panel of high mobility. BACKGROUND
[0002] The mobility of a liquid crystal display screen refers to the ability of charge carriers (such as electrons or holes) in a liquid crystal material to move under the action of an electric field, usually represented by μ, with units of cm² / (V·s). Here is a detailed introduction about it: mobility reflects the efficiency of charge carriers conducting within the liquid crystal material. The higher the mobility, the faster the charge carriers move under the action of an electric field, and the faster the liquid crystal molecules respond to changes in the electric field. As a result, the liquid crystal display screen can display and switch images faster, resulting in faster response time, higher refresh rate, and better image display.
[0003] Different liquid crystal materials have different molecular structures and physical properties, such as molecular size, shape, polarity, etc. These factors will affect the mobility of charge carriers. Generally speaking, liquid crystal materials with regular molecular structure, good symmetry, and moderate polarity have relatively high charge carrier mobility.
[0004] However, due to the inherent characteristics of the material, the frequency cannot be further improved beyond a certain limit. SUMMARY
[0005] The existing liquid crystal display panel has limited mobility due to material limitations, resulting in a decline in display quality.
[0006] To address the above problems, a high-mobility array circuit and liquid crystal display panel are proposed. By electrically connecting adjacent row gate scan lines, a double-gate scan line that can scan two rows sequentially is formed. The source data lines are electrically connected to the source electrodes of the column pixels on both sides with odd and even intervals. Single scanning can charge and write data to two rows of pixels, greatly improving the charging efficiency. Under the same frequency conditions, the number of display rows can be doubled, and under the same resolution conditions, the frequency can be doubled.
[0007] In a first aspect, a high-mobility array circuit includes:
[0008] a pixel array;
[0009] a plurality of row gate scan lines;
[0010] a plurality of source data lines;
[0011] The pixel array is arranged by R pixels, G pixels, and B pixels in a plurality of pixel units;
[0012] The gate of the row pixel in the pixel array is electrically connected with a corresponding row gate scanning line respectively, and adjacent row gate scanning lines are electrically connected to form a first double-gate scanning line.
[0013] The source of each group of the source data lines is electrically connected with the source of the column pixel on both sides in an odd-even interval.
[0014] In a first possible implementation manner of the high-mobility array circuit, the array circuit further comprises:
[0015] A second timing control unit;
[0016] The second timing control unit is electrically connected with the plurality of groups of source data lines, and is configured to charge the plurality of groups of source data lines simultaneously when the row gate scanning line is scanned.
[0017] In the second possible implementation manner of the first aspect of the utility model, the array circuit further comprises:
[0018] A first timing control unit;
[0019] The first timing control unit is electrically connected with the plurality of first double-gate scanning lines, and is configured to drive the corresponding two rows of pixels.
[0020] In a second aspect, a high-mobility array circuit comprises:
[0021] A pixel array;
[0022] A plurality of row gate scanning lines;
[0023] A plurality of source data lines;
[0024] The pixel array is arranged by R pixels, G pixels and B pixels in a plurality of pixel units;
[0025] The gate of the row pixel in the pixel array is electrically connected with the row gate scanning line on both sides respectively, and adjacent row gate scanning lines are staggered electrically connected to form a second double-gate scanning line;
[0026] The source of the same column pixel in the pixel array is electrically connected with the source data line on both sides in an odd-even interval.
[0027] In a first possible implementation manner of the high-mobility array circuit of the second aspect of the utility model, the array circuit further comprises:
[0028] A fourth timing control unit;
[0029] The fourth timing control unit is electrically connected with the odd column source data line and the even column source data line, and is used for driving the odd column source data line and the even column source data line to charge simultaneously when the row gate scanning line scans.
[0030] In combination with the first possible implementation manner of the second aspect of the utility model, in the second possible implementation manner, the array circuit further comprises:
[0031] A third timing control unit;
[0032] The third timing control unit is electrically connected with a plurality of second double gate scanning lines, and is used for driving corresponding two rows of pixels.
[0033] In a third aspect, a liquid crystal display panel comprises the high mobility array circuit of the first aspect or the second aspect.
[0034] The high mobility array circuit and the liquid crystal display panel of the utility model can greatly improve the charging efficiency, can realize that the number of display rows is doubled under the condition that the frequency is the same, and can improve the frequency by one time under the condition that the resolution is the same. BRIEF DESCRIPTION OF DRAWINGS
[0035] In order to more clearly illustrate the technical scheme in the embodiments of the utility model, the drawings needed to be used in the embodiment description will be briefly introduced, and obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings can also be obtained according to these drawings without creative labor.
[0036] Figure 1 It is the array circuit schematic diagram of single gate driving in prior art;
[0037] Figure 2 It is the array circuit schematic diagram of double gate driving in prior art;
[0038] Figure 3 It is the array circuit schematic diagram of single gate driving in the application;
[0039] Figure 4 It is the array circuit schematic diagram of double gate driving in the application. DETAILED DESCRIPTION
[0040] The technical solutions of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, other embodiments obtained by those skilled in the art without creative effort are all within the scope of protection of this utility model.
[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0042] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0043] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0044] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0045] Existing LCD panels, due to material limitations, have limited mobility improvements, leading to a decline in display quality. For example... Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of a single-gate driven array circuit in the prior art. Figure 2 This is a schematic diagram of a dual-gate driven array circuit in the prior art; Figure 1 and Figure 2The diagrams show array circuits with single-gate and dual-gate driving. Assuming each row takes T charging time and there are a total of 800 rows, it would take 800T to complete charging.
[0046] To address the above problems, a high mobility array circuit and a liquid crystal display panel are proposed.
[0047] First Embodiment
[0048] Firstly, a high-mobility array circuit, such as Figure 3 , Figure 3 This is a schematic diagram of the single-gate driven array circuit of this application, including a pixel array, multiple row gate scan lines, and multiple sets of source data lines. The pixel array is composed of R pixels, G pixels, and B pixels from multiple pixel units. The gates of the row pixels in the pixel array are electrically connected to the corresponding row gate scan lines, and adjacent row gate scan lines are electrically connected to form a first dual-gate scan line 100. Each set of source data lines is electrically connected to the sources of the column pixels on both sides at odd and even intervals. By electrically connecting adjacent row gate scan lines to form a dual-gate scan line that can scan two rows sequentially, and by electrically connecting the source data lines to the sources of the column pixels on both sides at odd and even intervals, data can be written and charged for the pixels of two rows in a single scan, greatly improving charging efficiency. At the same frequency, the number of display rows can be doubled, and at the same resolution, the frequency can be doubled.
[0049] In this embodiment, the R pixels, G pixels, and B pixels of the pixel unit form a pixel array, the gate scan line is electrically connected to the gate of the corresponding row pixel, and the source data line is electrically connected to the source of the corresponding column pixel.
[0050] In this embodiment, a single-gate drive scanning method is used, but by connecting the gate scan lines of adjacent row pixels together, two rows are scanned simultaneously using a first timing control unit (not shown in the figure). Furthermore, in this embodiment, dual-source data lines are used for data writing and charging, such as... Figure 3 Odd-numbered column source data lines (S1, S2, S3, ...) and even-numbered column source data lines (S1', S2', S3', ...) are used as a group of two source data lines, which are electrically connected to the source poles of the column pixels on both sides, thus realizing the scanning of two rows of pixels in one operation.
[0051] Furthermore, the array circuit also includes a second timing control unit (not shown in the figure); the second timing control unit (not shown in the figure) is electrically connected to multiple sets of source data lines and is used to charge multiple sets of source data lines simultaneously during row gate scan line scanning.
[0052] Furthermore, the array circuit also includes a first timing control unit (not shown in the figure); the first timing control unit (not shown in the figure) is electrically connected to multiple first dual-gate scan lines 100 for driving the corresponding two rows of pixels.
[0053] In a specific implementation, the first timing control unit (not shown in the figure) inputs the first driving timing to multiple first dual-gate scan lines 100 to drive two rows of pixels. At the same time, the second timing control unit (not shown in the figure) inputs the second driving timing to drive all source data lines simultaneously, thus enabling simultaneous scanning of two rows. The input of the first driving timing and the second driving timing can adopt technical solutions known to those skilled in the art.
[0054] Second Embodiment
[0055] Secondly, a high-mobility array circuit, such as Figure 4 , Figure 4 This is a schematic diagram of the dual-gate driven array circuit of this application, including a pixel array, multiple row gate scan lines, and multiple source data lines. The pixel array is composed of R pixels, G pixels, and B pixels from multiple pixel units. The gates of the row pixels in the pixel array are electrically connected to the row gate scan lines on both sides, and adjacent row gate scan lines are electrically connected alternately to form a second dual-gate scan line 200. The sources of the pixels in the same column of the pixel array are electrically connected to the source data lines on both sides at odd and even intervals. By electrically connecting adjacent row gate scan lines, a dual-gate scan line that can scan two rows sequentially is formed. By electrically connecting the source data lines to the sources of the column pixels on both sides at odd and even intervals, data can be written and charged for the pixels in two rows in a single scan, greatly improving the charging efficiency. At the same frequency, the number of display rows can be doubled, and at the same resolution, the frequency can be doubled.
[0056] Unlike the first embodiment, this embodiment employs a dual-gate driving scanning method. However, by interleaving the gate scan lines of adjacent row pixels together, the first timing control unit (not shown in the figure) simultaneously drives the scanning of two rows. In this embodiment, column pixels in the pixel array are sequentially separated by column source data lines, such as... Figure 4 Odd-numbered column source data lines (S1, S2, S3, ...) and even-numbered column source data lines (S1', S2', S3', ...) are connected to the source poles of the column pixels on both sides, enabling a single scan of two rows of pixels.
[0057] Furthermore, the array circuit also includes a fourth timing control unit (not shown in the figure); the fourth timing control unit (not shown in the figure) is electrically connected to the odd-numbered column source data lines and the even-numbered column source data lines, and is used to simultaneously drive the odd-numbered column source data lines and the even-numbered column source data lines to charge during row gate scan line scanning.
[0058] Furthermore, the array circuit also includes a third timing control unit (not shown in the figure); the third timing control unit (not shown in the figure) is electrically connected to multiple second dual-gate scan lines 200 for driving the corresponding two rows of pixels.
[0059] In a specific implementation, the third timing control unit (not shown in the figure) inputs the third driving timing to multiple second dual-gate scan lines 200 to drive two rows of pixels. At the same time, the fourth timing control unit (not shown in the figure) inputs the fourth driving timing to drive all source data lines simultaneously, thus enabling simultaneous scanning of two rows. The input of the third and fourth driving timing can adopt technical solutions known to those skilled in the art.
[0060] Thirdly, a liquid crystal display panel includes a high-mobility array circuitry as described in the first or second aspect.
[0061] The high mobility array circuit and liquid crystal display panel of this invention form a dual-gate scan line that can scan two rows sequentially by electrically connecting adjacent row gate scan lines. The source data lines are electrically connected to the sources of the column pixels on both sides at odd and even intervals. Data can be written and charged to the pixels of two rows in a single scan, which greatly improves the charging efficiency. Under the same frequency, the number of display rows can be doubled, and under the same resolution, the frequency can be doubled.
[0062] The above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model shall be included within the protection scope of the present utility model.
Claims
1. A high-mobility array circuit, characterized in that, include: Pixel array; Multiple row gate scan lines; Multiple source data lines; The pixel array is composed of R pixels, G pixels, and B pixels arranged from multiple pixel units; The gates of the row pixels in the pixel array are electrically connected to the corresponding row gate scan lines, and adjacent row gate scan lines are electrically connected to form a first dual gate scan line. Each set of source data lines is electrically connected to the source of the column pixels on both sides at odd and even intervals.
2. The high mobility array circuit according to claim 1, characterized in that, The array circuit also includes: First timing control unit; The first timing control unit is electrically connected to multiple first dual-gate scan lines to drive the corresponding two rows of pixels.
3. The high mobility array circuit according to claim 2, characterized in that, The array circuit also includes: Second timing control unit; The second timing control unit is electrically connected to the multiple sets of source data lines and is used to charge the multiple sets of source data lines simultaneously during the scanning of the row gate scan lines.
4. A high-mobility array circuit, characterized in that, include: Pixel array; Multiple row gate scan lines; Multiple source data lines; The pixel array is composed of R pixels, G pixels, and B pixels arranged from multiple pixel units; The gates of the row pixels in the pixel array are electrically connected to the row gate scan lines on both sides, and the adjacent row gate scan lines are electrically connected in an alternating manner to form a second dual gate scan line. The source poles of pixels in the same column of the pixel array are electrically connected to the source data lines on both sides at odd and even intervals.
5. The high mobility array circuit according to claim 4, characterized in that, The array circuit also includes: Third timing control unit; The third timing control unit is electrically connected to multiple second dual-gate scan lines to drive the corresponding two rows of pixels.
6. The high mobility array circuit according to claim 5, characterized in that, The array circuit also includes: Fourth timing control unit; The fourth timing control unit is electrically connected to the odd-numbered column source data line and the even-numbered column source data line, and is used to simultaneously drive the odd-numbered column source data line and the even-numbered column source data line to charge when the row gate scan line is scanned.
7. A liquid crystal display panel, characterized in that, The array circuit includes the high mobility array circuit described in any one of claims 1-6.