Semiconductor device

Abstract

Various embodiments of the utility model relate to a transistor structure. The transistor structure comprises a field plate structure and a plurality of dielectric structures passing through the field plate structure. In a top view of the transistor structure, the dielectric structures may be arranged in a grid. The dielectric structure enables the position of the field plate structure to be closer to the gate structure of the transistor than in the absence of the dielectric structure, which enables the length of the field plate structure to be increased without increasing (or minimizing) the total length of the transistor.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor device. BACKGROUND

[0002] A high voltage transistor is a metal oxide semiconductor (MOS) transistor that can be configured to operate at a higher drain voltage relative to a low voltage transistor. Low voltage transistors can be used for applications such as logic circuits (e.g., processors), memory (e.g., static random access memory (SRAM)), and / or input / output (I / O) circuits. High voltage transistors can be used for applications such as integrated circuit (IC) drivers, power ICs, image sensors, power management, display driver ICs (DDICs), bipolar complementary metal oxide semiconductor (CMOS) diffused metal oxide semiconductor (DMOS) ICs (BCDICs), and / or image signal processing (ISP) ICs. SUMMARY

[0003] A semiconductor device is provided. The semiconductor device includes a first source / drain region in a substrate. The semiconductor device also includes a second source / drain region in the substrate. The semiconductor device also includes a gate structure over the substrate and between the first source / drain region and the second source / drain region. The semiconductor device also includes a field plate structure over the substrate and between the gate structure and the second source / drain region. The semiconductor device also includes at least one dielectric structure through the field plate structure.

[0004] Another aspect of the present application provides a method of forming a semiconductor device. The method includes forming a gate material layer over a substrate of the semiconductor device. The method also includes forming a patterned photoresist layer over the gate material layer. The method also includes etching the gate material layer using the patterned photoresist layer to form a gate structure of a transistor structure included in the semiconductor device, a field plate structure of the transistor structure adjacent a first side of the gate structure, and at least one opening through the field plate structure. The method also includes forming at least one dielectric structure in the at least one opening through the field plate structure. The method also includes forming a first source / drain region of the transistor structure in the substrate, wherein the first source / drain region is adjacent a second side of the gate structure opposite the first side. The method also includes forming a second source / drain region of the transistor structure in the substrate, wherein the second source / drain region is adjacent the field plate structure.

[0005] Another aspect of the present application provides a semiconductor device. The semiconductor device includes a source / drain region in a substrate. The semiconductor device also includes a gate structure over the substrate and adjacent the source / drain region. The semiconductor device also includes a field plate structure over the substrate and between the gate structure and the source / drain region. The semiconductor device also includes a first dielectric structure through the field plate structure. The semiconductor device also includes a second dielectric structure adjacent the first dielectric structure and through the field plate structure. The semiconductor device also includes a resist protective oxide layer on a portion of an overall length of the field plate structure. The resist protective oxide layer is included over the second dielectric structure and not over the first dielectric structure.

[0006] So that the foregoing features and advantages of the present application can be understood in more detail, a more particular description will be rendered by reference to specific embodiments thereof, which are illustrated in the appended drawings and will be described herein below. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a diagram of an example environment in which systems and / or methods described herein can be implemented.

[0008] Figure 2 is a diagram of a portion of an example semiconductor device described herein.

[0009] Figures 3A-3C is a diagram of an example transistor structure described herein.

[0010] Figure 4 is a diagram of an example implementation of a transistor structure described herein.

[0011] Figures 5A-5Q is a diagram of forming an example implementation of a transistor structure described herein.

[0012] Figures 6A-6CThis is a diagram of an exemplary embodiment of the transistor structure described herein.

[0013] Figure 7 This is a diagram of exemplary components of the apparatus described herein.

[0014] Figure 8 This is a flowchart of an exemplary process related to forming the semiconductor device described herein. Detailed Implementation

[0015] The following utility model description provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components and arrangements are described below to simplify the utility model description. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first component being formed on or on a second component may include embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which additional components may be formed between the first and second components, thereby potentially preventing direct contact between the first and second components. Furthermore, reference numerals and / or letters may be repeated in various instances of the utility model description. Such repetition is for the purpose of brevity and clarity, and not to indicate any relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and similar expressions may be used herein to describe the relationship between one component or feature and another shown in the figures. In addition to the orientations depicted in the figures, these spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0017] In some cases, transistors (e.g., high-voltage transistors) include a field plate layer. The field plate layer is a conductive layer that is included over a portion of the transistor's channel region between the gate structure and the drain region. The field plate layer can improve transistor efficiency by enabling it to operate on the electric field generated by the transistor's gate structure (e.g., reducing the peak value of the electric field). Compared to the absence of a field plate layer, by operating on the electric field generated by the gate structure, the transistor can operate at higher voltages with a lower on-state resistance (Ro). dson To achieve a larger breakdown voltage.

[0018] The length of the field plate layer can be selected based on the operating voltage of the transistor to meet the breakdown voltage parameter of the transistor. For example, the length of the field plate layer can be increased to enable the transistor to achieve a sufficiently high transistor breakdown voltage. While this enables the transistor to operate at a high operating voltage, increasing the length of the field plate layer increases the distance between the gate structure and the drain region. Increasing the distance between the gate structure and the drain region increases the device pitch of the transistor, which decreases the transistor device density that can be achieved on a semiconductor device. In addition, increasing the device pitch of the transistor can decrease the operational efficiency of the transistor, can increase the resistance in the transistor (e.g., can increase R dson

[0019] In some implementations described herein, a transistor structure (e.g., a high voltage transistor) includes a field plate structure and at least one dielectric structure that passes through the field plate structure. In a top view of the transistor structure, the dielectric structure can be arranged in a grid. The dielectric structure enables the field plate structure to be located closer to the gate structure of the transistor compared to if the dielectric structure were not present, which enables the length of the field plate structure to be increased without increasing (or with minimal increase in) the overall length of the transistor.

[0020] The gate structure, the field plate structure, and the openings through the field plate structure for the dielectric structure are all formed by etching a gate material layer. The remaining portions of the gate material layer correspond to the gate structure and the field plate structure. The openings are then filled with a dielectric material to form the dielectric structure in the field plate structure. If the dielectric structure were not present, the pattern in the photoresist used to etch the gate material layer would be considered an isolation space, which means that the pattern would have a very low feature density. As such, a large portion of the transistor would be blocked from exposure during the photolithography operation, resulting in a low exposure efficiency and / or an increased likelihood of underdevelopment of the pattern. The increased likelihood of underdevelopment of the pattern can result in residual photoresist material (referred to as photoresist scum), which can result in defects when etching the gate material layer. In particular, the residual photoresist material can result in underetching between the gate structure and the field plate structure, which can result in bridging (and electrical shorting) between the gate structure and the field plate structure. Spacing the gate structure and the field plate structure farther apart can improve the exposure efficiency because a greater amount of light flux can reach the photoresist between where the gate structure is to be formed and where the field plate structure is to be formed. However, this increases the device pitch of the transistor, which results in increased resistance and / or decreased density as described above.

[0021] ​By including a dielectric structure in the field plate structure described herein, the feature density in the pattern used to form the gate structure, the field plate structure, and the recesses through the field plate structure is increased, resulting in a densely distributed pattern. This densely distributed pattern allows a greater amount of light flux to be exposed to the photoresist beneath which the pattern will be formed. The greater light flux allows the gate structure and the field plate structure to be spaced closer together, while still allowing sufficient light flux to reach the photoresist to ensure complete pattern development.

[0022] Figure 1 This is a diagram of an exemplary environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 As shown, the exemplary environment 100 may include a plurality of semiconductor processing tools 102 to 114 and a wafer / die transport tool 116. The plurality of semiconductor processing tools 102 to 114 may include a deposition tool 102, an exposure tool 104, a developing tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, an ion implantation tool 114, and / or another type of semiconductor processing tool. The tools included in the exemplary environment 100 may be included in semiconductor cleanrooms, semiconductor foundries, semiconductor processing facilities, and / or manufacturing facilities, etc.

[0023] Deposition tool 102 is a semiconductor processing tool including a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, deposition tool 102 includes a spin coater tool capable of depositing a photoresist layer on a substrate (e.g., a wafer). In some embodiments, deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, a low-pressure CVD (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputter tool or another type of PVD tool. In some embodiments, deposition tool 102 includes an epitaxy tool configured to form layers and / or regions of a device by epitaxial growth. In some embodiments, exemplary environment 100 includes multiple types of deposition tools 102.

[0024] Exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a source of radiation, such as an ultraviolet (UV) light source (e.g., a deep UV light source, an extreme UV (EUV) light source, and / or the like), an x-ray source, an electron beam (e-beam) source, and / or the like. Exposure tool 104 can expose a photoresist layer to a source of radiation to transfer a pattern from a mask to the photoresist layer. The pattern can include one or more semiconductor device layer patterns for forming one or more semiconductor devices, can include a pattern for forming one or more structures of a semiconductor device, can include a pattern for etching various portions of a semiconductor device, and / or the like. In some embodiments, exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0025] The developing tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred to the photoresist layer from the exposure tool 104. In some implementations, the developing tool 106 develops the pattern by removing unexposed portions of the photoresist layer. In some implementations, the developing tool 106 develops the pattern by removing exposed portions of the photoresist layer. In some implementations, the developing tool 106 develops the pattern by dissolving exposed or unexposed portions of the photoresist layer using a chemical developer.

[0026] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool 108 can include a wet etching tool, a dry etching tool, and / or the like. In some implementations, the etching tool 108 includes a chamber filled with an etchant, and a substrate is placed in the chamber for a particular period of time to remove a particular amount of one or more portions of the substrate. In some implementations, the etching tool 108 can etch one or more portions of a substrate using plasma etching or plasma-assisted etching, which can involve using ionized gas to isotropically or directionally etch the one or more portions.

[0027] The planarization tool 110 is a semiconductor processing tool capable of grinding or planarizing various layers of a wafer or semiconductor device. For example, the planarization tool 110 can include a chemical mechanical planarization (CMP) tool that grinds or planarizes a layer or surface of deposited or plated material, and / or another type of planarization tool. The planarization tool 110 can utilize a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing) to grind or planarize a surface of a semiconductor device. The planarization tool 110 can use abrasive and corrosive chemical slurries in conjunction with a polishing pad and retaining ring (e.g., typically having a larger diameter than the semiconductor device). The polishing pad and semiconductor device can be pressed together by a dynamic polishing head and held in place by the retaining ring. The dynamic polishing head can be rotated using different axes of rotation to remove material and level any irregularities of the semiconductor device, thereby flattening or planarizing the semiconductor device.

[0028] The plating tool 112 is a semiconductor processing tool capable of plating a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion thereof with one or more metals. For example, the plating tool 112 can include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a compound material or alloy (e.g., tin-silver, tin-lead, and / or the like) electroplating device, and / or an electroplating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0029] The ion implantation tool 114 is a semiconductor processing tool for implanting ions into a substrate, such as a semiconductor wafer. The ion implantation tool 114 generates ions from a source material, such as a gas or a solid, in an arc chamber. The source material is provided into the arc chamber, and an arc voltage discharges between a cathode and an electrode to generate a plasma containing ions of the source material. One or more extraction electrodes are used to extract ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam can be directed toward a substrate so that the ions are implanted beneath a surface of the substrate to dope the substrate.

[0030] The wafer / die transport tool 116 includes a mobile robot, a robotic arm, a trolley or track cart, an overhead hoist transport (OHT) system, an automated material handling system (AMHS), and / or another type of device configured to transport substrates and / or semiconductor devices between the semiconductor processing tools 102-114, between processing chambers of the same semiconductor processing tool, and / or to and from other locations (e.g., wafer racks, storage chambers, and / or the like). In some implementations, the wafer / die transport tool 116 can be a programmed device configured to travel a particular path and / or can be semi-automatically or automatically operated. In some implementations, the example environment 100 includes multiple wafer / die transport tools 116.

[0031] For example, wafer / die transport tool 116 can be included in a cluster tool or another type of tool including multiple processing chambers, and can be configured to transport substrates and / or semiconductor devices between the multiple processing chambers, between a processing chamber and a buffer region, between a processing chamber and an interface tool (e.g., an equipment front end module (EFEM)), and / or between a processing chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), etc. In some implementations, wafer / die transport tool 116 can be included in a multi-chamber (or cluster) deposition tool 102, which can include a pre-clean processing chamber (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or byproducts from a substrate and / or semiconductor device) and multiple types of deposition processing chambers (e.g., processing chambers for depositing different types of materials, processing chambers for performing different types of deposition operations). In such implementations, wafer / die transport tool 116 is configured to transport substrates and / or semiconductor devices between processing chambers of deposition tool 102 without breaking or removing a vacuum (or at least a partial vacuum) between the processing chambers and / or between processing operations, as described herein.

[0032] In some implementations, one or more of semiconductor processing tools 102-114 and / or wafer / die transport tool 116 can be used to perform one or more semiconductor processing operations described herein. For example, one or more of semiconductor processing tools 102-114 and / or wafer / die transport tool 116 can be used to form a gate material layer over a substrate of a semiconductor device; can be used to form a patterned photoresist layer over the gate material layer; can be used to etch the gate material layer with the patterned photoresist layer to form a gate structure of a transistor structure included in the semiconductor device, a field plate structure adjacent to a first side of the gate structure of the transistor structure, and at least one opening through the field plate structure; can be used to form at least one dielectric structure in the at least one opening through the field plate structure; can be used to form a first source / drain region of the transistor structure in the substrate, where the first source / drain region is adjacent to a second side of the gate structure opposite the first side; and / or can be used to form a second source / drain region of the transistor structure in the substrate, where the second source / drain region is adjacent to the field plate structure, etc.

[0033] In some implementations, one or more of the semiconductor processing tools 102-114 and / or wafer / die transport tools 116 can be used to perform one or more of the semiconductor processing operations set forth in connection with Figures 5A-5Q and / or Figure 8 and / or

[0034] Figure 1 The number and arrangement of devices shown in FIG. 1 are provided as one or more examples. In practice, there can be additional devices, fewer devices, different devices, or differently arranged devices than those shown in FIG. 1. Furthermore, two or more devices shown in FIG. 1 can be implemented within a single device, or a single device shown in FIG. 1 can be implemented as multiple, distributed devices. Additionally, a set of devices (e.g., one or more devices) of example environment 100 can perform one or more functions described as being performed by another set of devices of example environment 100. Figure 1 Figure 1 Figure 1

[0035] Figure 2 FIG. 1 is a diagram of an example semiconductor device 200 that is part of the example semiconductor devices described herein. Semiconductor device 200 includes an example of a memory device (e.g., static random access memory (SRAM), dynamic random access memory (DRAM)), a logic device, a processor, an input / output (I / O) device, or another type of semiconductor device that includes one or more transistors. In some implementations, semiconductor device 200 includes one or more high voltage transistors. In these implementations, semiconductor device 200 can include an integrated circuit (IC) driver, a power IC, an image sensor, a display driver IC (DDIC), a bipolar complementary metal oxide semiconductor (CMOS) diffused metal oxide semiconductor (DMOS) IC (BCD IC), and / or an image signal processing (ISP) IC, among others.

[0036] ​​​Semiconductor device 200 includes one or more stacked layers, including dielectric layer 206, etch stop layer (ESL) 208, dielectric layer 210, ESL 212, dielectric layer 214, ESL 216, dielectric layer 218, ESL 220, dielectric layer 222, ESL 224, and dielectric layer 226, etc. Dielectric layers 206, 210, 214, 218, 222, and 226 electrically isolate various structures of semiconductor device 200. Dielectric layers 206, 210, 214, 218, 222, and 226 comprise silicon nitride (SiN). x ), oxides (e.g., silicon oxide (SiO2) x (and / or another oxide material), and / or another type of dielectric material. ESL 208, 212, 216, 220, 224 include layers of material configured to allow various portions of the semiconductor device 200 (or layers included therein) to be selectively etched or protected from etching to form one or more structures included in the semiconductor device 200.

[0037] like Figure 2 As further shown, the semiconductor device 200 includes a plurality of source / drain regions 228. The source / drain regions may refer individually or collectively to sources or drains, depending on the context. Source / drain regions 228 may include epitaxial (epi) regions grown and / or otherwise formed on and / or around portions of the fin structure 204. Source / drain regions 228 may be formed by epitaxial growth and / or another processing technique. In some embodiments, source / drain regions 228 are formed in recessed portions of the fin structure 204. Recessed portions may be formed by strained source-drain (SSD) etching of the fin structure 204 and / or another type of etching operation. Source / drain regions 228 serve as source or drain regions of transistors included in the semiconductor device 200.

[0038] The source / drain region 228 may comprise silicon (Si) having one or more dopants, such as p-type materials (e.g., boron (B) or germanium (Ge), etc.), n-type materials (e.g., phosphorus (P) or arsenic (As), etc.), and / or another type of dopant. Therefore, the semiconductor device 200 may comprise a p-type metal-oxide-semiconductor (PMOS) transistor having a p-type source / drain region, an n-type metal-oxide-semiconductor (NMOS) transistor having an n-type source / drain region, and / or other types of transistors.

[0039] The source / drain region 228 is electrically connected to the source / drain contact 230 of the transistor included in the semiconductor device 200. The source / drain contact (metal source / drain (MD)) 230 comprises cobalt (Co), ruthenium (Ru), and / or other conductive or metallic materials. The transistor also includes a gate structure 232 (main gate, MG) formed of polycrystalline silicon, a metal (e.g., tungsten (W) or another metal), and / or another type of conductive material. The source / drain contact 230 and the gate structure 232 are electrically isolated by one or more sidewall separators, including a sidewall separator layer 234 on each side of the source / drain contact 230 and a sidewall separator layer 236 on each side of the gate structure 232. Sidewall separator layers 234 and 236 comprise silicon oxide (SiO2). x ), silicon nitride (Si x N y Silicon oxycarbonate (SiOC), silicon oxycarbonitrile (SiOCN), and / or other suitable materials. In some embodiments, the sidewall separator layer 234 is omitted from the sidewall of the source / drain contact 230.

[0040] like Figure 2 As further shown, source / drain contacts 230 and gate structure 232 are electrically connected to one or more types of interconnects. The interconnects electrically connect transistors of the semiconductor device 200 and / or electrically connect transistors to other regions and / or components of the semiconductor device 200. In some embodiments, the interconnects electrically connect transistors to the back end of line (BEOL) region of the semiconductor device 200.

[0041] Source / drain contacts 230 are electrically connected to interconnect 238. One or more of the gate structures 232 are electrically connected to interconnect 240 (e.g., a gate via or VG). Interconnects 238 and 240 comprise conductive materials such as tungsten, cobalt, ruthenium, copper, and / or other types of conductive materials. In some embodiments, gate structures 232 are electrically connected to interconnect 240 via gate contacts 242 (CB or MP) to reduce contact resistance between gate structures 232 and interconnect 240. Gate contacts 242 comprise examples of conductive materials such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), or gold (Au).

[0042] like Figure 2Further shown, interconnects 238 and 240 are electrically connected to a plurality of BEOL layers, each BEOL layer including one or more metallization layers and / or via layers. As an example, interconnects 238 and 240 can be electrically connected to an M0 metallization layer, the M0 metallization layer including electrically conductive structures 244 and 246. The M0 metallization layer is electrically connected to a V0 via layer, the V0 via layer including vias 248 and 250. The V0 via layer is electrically connected to an M1 metallization layer, the M1 metallization layer including electrically conductive structures 252 and 254. In some embodiments, the BEOL layers of semiconductor device 200 include additional metallization layers and / or via layers that connect semiconductor device 200 to a package.

[0043] As described above, there is provided Figure 2 As an example. Other examples can differ Figure 2 from the described examples.

[0044] Figures 3A-3C is a diagram of an example transistor structure 300 described herein. Transistor structure 300 can be included in semiconductor device 200 described in connection with Figure 2 Transistor structure 300 can include a high voltage transistor, such as a high voltage planar transistor, a high voltage fin field effect transistor (FinFET), a high voltage nanoscale transistor (e.g., a gate all around (GAA) transistor, a nanosheet transistor, a nanotube transistor, a nanoribbon transistor), a high voltage laterally diffused metal oxide semiconductor (LDMOS) transistor, and / or another type of high voltage transistor.

[0045] Figure 3A shows a top view of transistor structure 300. As Figure 3AAs shown, the transistor structure 300 is included in the substrate 202 of the semiconductor device 200. The transistor structure 300 includes a source / drain region 228a in the substrate 202, and a source / drain region 228b included in the substrate 202. In some embodiments, the source / drain region 228a is a source region of the transistor structure 300 and the source / drain region 228b is a drain region of the transistor structure 300, which is configured to operate at a relatively high voltage. By way of example, the source / drain region 228b can operate at a drain voltage included in a range of about 9 volts to about 36 volts, while a low voltage transistor can operate at a drain voltage range of about 0 volts to about 1.8 volts. However, other values for these ranges are also within the scope of the present disclosure. In some embodiments, the source / drain region 228b is a source region of the transistor structure 300 and the source / drain region 228a is a drain region of the transistor structure 300, which is configured to operate at a relatively high voltage.

[0046] The source / drain region 228a can be electrically and / or physically coupled with one or more source / drain contacts 230a above the source / drain region 228a, and the source / drain region 228b can be electrically and / or physically coupled with one or more source / drain contacts 230b above the source / drain region 228b.

[0047] A gate structure 232 can be included on the substrate 202 between the source / drain region 228a and the source / drain region 228b. A voltage can be selectively applied to the gate structure 232 to selectively control the electrical conductivity in the substrate 202 between the source / drain region 228a and the source / drain region 228b. In a top view of the semiconductor device 200, the gate structure 232 can extend in the y-direction. The gate structure 232 can be electrically and / or physically coupled with one or more gate contacts 242 above the gate structure 232. In some embodiments, the gate contacts 242 are located at one end of the gate structure 232. However, other locations for the gate contacts 242 are also within the scope of the present disclosure.

[0048] The transistor structure 300 also includes a field plate structure 302 between the gate structure 232 and the source / drain region 228b. The field plate structure 302 enables the electric field between the gate structure 232 and the source / drain region 228b to be controlled to achieve a particular breakdown voltage for the transistor structure 300. In particular, the field plate structure 302 can be electrically biased during operation of the transistor structure 300 such that the field plate structure 302 suppresses the peak amplitude of the electric field, enabling the transistor structure 300 to operate at a greater operating voltage before breakdown is reached.

[0049] The field plate structure 302 includes polysilicon material, metal (e.g., tungsten (W) or another metal), and / or another type of conductive material. The field plate structure 302 can include an elongated structure that is substantially parallel to the gate structure 232 and extends in the y-direction. The dimension of the field plate structure 302 in the x-direction (substantially perpendicular to the y-direction) in the semiconductor device 200 is referred to as the length of the field plate structure 302. The length of the field plate structure 302 can be selected to meet a breakdown voltage threshold of the transistor structure 300. For example, the length of the field plate structure 302 can be increased to increase the breakdown voltage of the transistor structure 300, or the length of the field plate structure 302 can be decreased to decrease the breakdown voltage of the transistor structure 300.

[0050] The field plate structure 302 can be electrically and / or physically coupled with one or more field plate contacts 304 above the field plate structure 302. The field plate contacts 304 enable an electrical bias (e.g., voltage, current) to be applied to the field plate structure 302 to suppress the electric field between the gate structure 232 and the source / drain region 228b during operation of the transistor structure 300. The electrical bias increases the depletion of carriers in the substrate 202 between the gate structure 232 and the source / drain region 228b, thereby reducing the peak electric field strength in the substrate 202 between the gate structure 232 and the source / drain region 228b. In some implementations, the field plate contacts 304 are located at one end of the field plate structure 302. However, other locations for the field plate contacts 304 are within the scope of the present disclosure.

[0051] The transistor structure 300 can also include a resist protective oxide (RPO) layer 306 between the gate structure 232 and the source / drain region 228b. The RPO layer 306 can be included over and / or on a portion of the field plate structure 302. The RPO layer 306 can be included to prevent silicide formation on the substrate 202, on the field plate structure 302, and / or on another surface of the transistor structure 300. The RPO layer 306 can include one or more dielectric materials, such as oxide (e.g., SiO x , e.g., SiO2), nitride (e.g., Si x N y , e.g., Si3N4), carbide, oxynitride, oxycarbide, and nitride carbide, polymer, etc., and / or other suitable dielectric materials.

[0052] The field plate structure 302 includes at least one dielectric structure 308. The dielectric structure 308 includes a dielectric plug, a dielectric column, and / or another type of dielectric structure that can be arranged in a grid configuration in a top-down view (plan view) of the transistor structure 300. The grid configuration includes a plurality of columns 308a of the dielectric structure 308 in the x-direction, and one or more rows 308b of the dielectric structure 308 in the y-direction.

[0053] The number of columns 308a can be in a range from about 5 columns to about 200 columns. In some implementations, the number of columns 308a is in a range from about 9 columns to about 199 columns, depending on the y-direction width of the field plate structure 302. For example, the greater the y-direction width of the field plate structure 302 (and the greater the output current of the transistor structure 300), the greater the number of columns 308a of the dielectric structure 308 that can be included in the field plate structure 302. Conversely, the smaller the y-direction width of the field plate structure 302 (and the smaller the output current of the transistor structure 300), the smaller the number of columns 308a of the dielectric structure 308 that can be included in the field plate structure 302. However, other ranges for the number of columns 308a are also within the scope of the present disclosure.

[0054] The number of rows 308b can be in a range from about 1 row to about 4 rows, depending on the x-direction length of the field plate structure 302. For example, the greater the x-direction length of the field plate structure 302 (and the greater the operating voltage of the transistor structure 300), the greater the number of rows 308b of the dielectric structure 308 that can be included in the field plate structure 302. Conversely, the smaller the x-direction length of the field plate structure 302 (and the smaller the output current of the transistor structure 300), the smaller the number of rows 308b of the dielectric structure 308 that can be included in the field plate structure 302. However, other ranges for the number of rows 308b are also within the scope of the present disclosure.

[0055] The dielectric structure 308 is included to make the distance between the gate structure 232 and the field plate structure 302 less than the distance without the dielectric structure 308. As Figure 5F and Figure 5GIn more detail, by including the dielectric structure 308 in the field plate structure 302, the feature density in the pattern used to form the gate structure 232, the field plate structure 302, and the recess through the field plate structure 302 for the dielectric structure 308 is increased, thereby making the pattern a densely distributed pattern. The densely distributed pattern enables a greater amount of optical flux to be exposed to the photoresist below that will form the pattern. The greater amount of optical flux enables the gate structure 232 and the field plate structure 302 to be spaced closer together while still allowing a sufficient amount of optical flux to reach the photoresist to ensure that the pattern is fully developed.

[0056] The arrangement of the dielectric structure 308 in the field plate structure 302 provides regions of the field plate structure 302 that extend fully between opposite sides of the field plate structure 302 in the x-direction, and regions of the field plate structure 302 that extend fully between opposite ends of the field plate structure 302 in the y-direction. This enables the field plate structure 302 to provide a reduced surface field (RESURF) effect 310 in both the x-direction and the y-direction, thereby enabling the field plate structure 302 to be used to suppress electric fields between the gate structure 232 and the source / drain regions 228b in both the x-direction and the y-direction.

[0057] Figure 3B A cross-sectional view of the transistor structure 300 along line A-A in Figure 3A is shown. As can be seen, the dielectric structure 308 is disposed in the field plate structure 302 between the gate structure 232 and the source / drain regions 228b. The dielectric structure 308 is disposed in the field plate structure 302 in a region of the field plate structure 302 that is disposed between the gate structure 232 and the source / drain regions 228b in both the x-direction and the y-direction. Figure 3BAs shown, the substrate 202 can include a plurality of regions. An n-type region 312 includes a region of the substrate 202 doped with one or more n-type dopants, such as phosphorus (P) or arsenic (As), among others. The n-type region 312 can be referred to as an n-type buried layer (NBL). A deep p-well (DPW) region 314 can be included above the n-type region 312. The DPW region 314 includes a region of the substrate 202 doped with one or more p-type dopants, such as boron (B) or germanium (Ge), among others. A drift region 316 can be included above the DPW region 314. The drift region 316 can include a region of the substrate 202 doped with one or more n-type dopants. The drift region 316 includes a portion of the substrate 202 between the gate structure 232 and the source / drain region 228b. The drift region 316 is located below the field plate structure 302, which enables the field plate structure 302 to be used to control the electric field in the drift region 316 of the substrate 202. A channel region 318 can be located adjacent to the DPW region 314 and the drift region 316. The channel region 318 can include a portion of the substrate 202 doped with one or more p-type dopants. The channel region 318 includes a portion of the substrate 202 below the gate structure 232. An isolation region 320 can be located in the substrate 202 adjacent to the source / drain region 228a. The isolation region 320 includes a portion of the substrate 202 doped with one or more p-type dopants.

[0058] The source / drain regions 228a and 228b can be included in the substrate 202. The gate structure 232 and the field plate structure 302 can be included above the substrate 202 and between the source / drain regions 228a and 228b. The gate structure 232 and the field plate structure 302 can be covered by the ESL 208 and the dielectric layer 210. The source / drain contact 230a can extend through the dielectric layer 210 and can be coupled with the source / drain region 228a. The source / drain contact 230b can extend through the dielectric layer 210 and can be coupled with the source / drain region 228b. The field plate contact 304 can extend through the dielectric layer 210 and can be coupled with the field plate structure 302.

[0059] The ESL 212 is included above the dielectric layer 210, and the dielectric layer 214 is included above the ESL 212. Interconnects 238a and 238b can be included in the dielectric layer 214 and / or the ESL 212, where the interconnect 238a is electrically and / or physically coupled with the source / drain contact 230a, and the interconnect 238b is electrically and / or physically coupled with the source / drain contact 230b. The field plate contact 304 is shown in dashed lines in Figure 3B to indicate that the field plate contact 304 is not visible in the cross-section along line A-A. Figure 3BThe field plate contact 304 is included to illustrate that the interconnect 238a electrically couples the source / drain region 228a and the field plate structure 302 through the source / drain contact 230a and the field plate contact 304. This enables the field plate structure 302 to implement a source bias. Biasing the field plate structure 302 with a source bias can convert a gate-drain charge (Q gd ) portion of the electric field in the substrate 202 to a drain-source charge (Q ds ), which can reduce the gate-drain charge (Q gd ) of the electric field, enabling the transistor structure 300 to operate at higher frequencies and with lower power switching losses.

[0060] The gate dielectric layer 322a is included on the substrate 202 between the substrate 202 and the gate structure 232. The gate dielectric layer 322a can provide electrical isolation between the gate structure 232 and the substrate 202, enabling a voltage applied to the gate structure 232 to cause an electric field in the substrate 202. The field plate dielectric layer 322b is included on the substrate 202 between the substrate 202 and the field plate structure 302. The field plate dielectric layer 322b can provide electrical isolation between the field plate structure 302 and the substrate 202, enabling a voltage to be applied to the field plate structure 302 to suppress the electric field generated by the gate structure 232 in the drift region 316. The dielectric structure 308 extends continuously between a top surface of the field plate structure 302 and a bottom surface of the field plate structure 302. Thus, the bottom surface of the dielectric structure 308 can be in contact with a top surface of the field plate dielectric layer 322b.

[0061] The gate dielectric layer 322a and the field plate dielectric layer 322b can each include silicon nitride (SiN x ), an oxide (e.g., silicon oxide (SiO x ), and / or another oxide material), and / or another type of dielectric material. In some implementations, the z-direction thickness of the field plate dielectric layer 322b is greater than the z-direction thickness of the gate dielectric layer 322a. In some implementations, the z-direction thickness of the field plate dielectric layer 322b is approximately the same thickness as the z-direction thickness of the gate dielectric layer 322a. In some implementations, a portion of the gate structure 232 is included on a portion of the field plate dielectric layer 322b.

[0062] One or more sidewall spacers are included on and / or above the sidewalls of the gate structure 232 and / or on and / or above the sidewalls of the field plate structure 302. An outer sidewall spacer 324a is included on the outer sidewalls of the gate structure 232 (e.g., the sidewalls of the gate structure 232 facing away from the field plate structure 302 and toward the source / drain region 228a). An outer sidewall spacer 324b is included on the outer sidewalls of the field plate structure 302 (e.g., the sidewalls of the field plate structure 302 facing away from the gate structure 232 and toward the source / drain region 228b). An inner sidewall spacer 326 is included on the inner sidewalls of the gate structure 232 and the field plate structure 302.

[0063] The inner sidewall spacer 326 is a merged sidewall spacer that extends continuously between the inner sidewalls of the gate structure 232 and the field plate structure 302. As a result, the RPO layer 306 can be omitted at the gate structure 232, and the RPO layer 306 can not be fully disposed along the x-direction length on the field plate structure 302. Instead, the inner sidewall spacer 326 provides protection against silicide formation between the gate structure 232 and the field plate structure 302. The inner sidewall spacer 326 also provides electrical isolation between the gate structure 232 and the field plate structure 302, thereby reducing the likelihood of an electrical short between the gate structure 232 and the field plate structure 302.

[0064] The inclusion of the dielectric structure 308 in the field plate structure 302 enables a reduced distance between the gate structure 232 and the field plate structure 302, which in turn enables the inner sidewall spacer 326 to be continuous, thereby enabling the gate structure 232 and the field plate structure 302 to share the inner sidewall spacer 326. If the gate structure 232 and the field plate structure 302 were positioned farther apart, the sidewall spacers formed on the inner sidewalls of the gate structure 232 and the field plate structure 302 would not merge into a single inner sidewall spacer 326. As such, the RPO layer 306 would need to remain between the gate structure 232 and the field plate structure 302 to provide protection against silicide formation and / or electrical isolation between the gate structure 232 and the field plate structure 302. Thus, the dielectric structure 308 enables fewer layers to be included above the gate structure 232, which can enable the transistor structure 300 to achieve a smaller gate resistance.

[0065] The outer sidewall spacers 324a and 324b and the inner sidewall spacer 326 can each include silicon oxycarbide (SiOC), silicon nitride (SiN x ), an oxide (e.g., silicon oxide (SiO x(and / or another oxide material), and / or another suitable dielectric material. In some embodiments, the outer sidewall separators 324a and 324b, the inner sidewall separator 326, and the dielectric structure 308 comprise the same dielectric material or the same combination of dielectric materials. In some embodiments, the outer sidewall separators 324a and 324b, the inner sidewall separator 326, and / or the dielectric structure 308 comprise different dielectric materials or different combinations of dielectric materials.

[0066] RPO layer 306 is included on a portion of the top surface of field plate structure 302 and on outer wall spacer 324b located on the outer wall of field plate structure 302. RPO layer 306 is located between field plate structure 302 and source / drain region 228b. First end of RPO layer 306 may be located between adjacent rows 308b of dielectric structure 308 (e.g., between first row 308b and second row 308b). Therefore, RPO layer 306 may be included only on a subset of dielectric structure 308. Second end of RPO layer 306 may be located adjacent to source / drain region 228b.

[0067] Figure 3C The edge of transistor structure 300 is shown Figure 3A A cross-sectional view of line BB. (See attached image.) Figure 3C As shown, the gate structure 232 includes a gate contact 242, and the gate contact 242 includes an interconnect 240. The field plate structure 302 includes a field plate contact 304, and the field plate contact 304 includes an interconnect 238a.

[0068] As mentioned above, providing Figures 3A-3C As an example. Other examples can be found related to... Figures 3A-3C The descriptions are different.

[0069] Figure 4 This is a diagram of an exemplary embodiment 400 of the transistor structure 300 described herein. Specifically, Figure 4 One or more dimensions of the transistor structure 300 described herein are shown. Figure 4 As shown, an exemplary dimension D1 of the transistor structure 300 includes the device pitch of the transistor structure 300. "Device pitch" refers to the distance between the source / drain regions 228a and 228b. In some embodiments, dimension D1 is approximately 0.8 micrometers to 4 micrometers. This range (and smaller device pitches) of the device pitch of the transistor structure 300 can be achieved by including a dielectric structure 308 in the field plate structure 302, as including the dielectric structure 308 enables a reduced distance between the field plate structure 302 and the gate structure 232. However, other ranges of values ​​are also within the scope of this disclosure.

[0070] like Figure 4Further shown, another exemplary dimension D2 of the transistor structure 300 includes a distance between the gate structure 232 and the field plate structure 302. In some embodiments, the dielectric structure 308 in the field plate structure 302 enables the distance between the field plate structure 302 and the gate structure 232 to be about 0.10 microns or less. This enables a high density of the transistor structure 300 to be incorporated into the semiconductor device 200 and / or enables the transistor structure 300 to achieve low R dson Furthermore, the shorter the distance between the gate structure 232 and the field plate structure 302, the better the control of the electric field generated by the field plate structure 302 on the gate structure 232. Thus, a distance of about 0.10 microns or less between the field plate structure 302 and the gate structure 232 enables better control of the electric field generated by the gate structure 232 compared to a situation without the dielectric structure 308. However, other values for the dimension D2 are within the scope of the present disclosure.

[0071] As shown in FIG. 3, the gate structure 232 includes a gate dielectric layer 232a and a gate electrode layer 232b. The gate dielectric layer 232a is formed on the substrate 202. The gate electrode layer 232b is formed on the gate dielectric layer 232a. The gate dielectric layer 232a can be formed of any suitable material, such as silicon dioxide, silicon nitride, silicon oxynitride, or any other suitable material. The gate electrode layer 232b can be formed of any suitable material, such as polysilicon, amorphous silicon, or any other suitable material. Figure 4 Further shown, another exemplary dimension D2 of the transistor structure 300 includes a distance between the gate structure 232 and the field plate structure 302. In some embodiments, the dielectric structure 308 in the field plate structure 302 enables the distance between the field plate structure 302 and the gate structure 232 to be about 0.10 microns or less. This enables a high density of the transistor structure 300 to be incorporated into the semiconductor device 200 and / or enables the transistor structure 300 to achieve low R

[0072] As shown in FIG. 3, the gate structure 232 includes a gate dielectric layer 232a and a gate electrode layer 232b. The gate dielectric layer 232a is formed on the substrate 202. The gate electrode layer 232b is formed on the gate dielectric layer 232a. The gate dielectric layer 232a can be formed of any suitable material, such as silicon dioxide, silicon nitride, silicon oxynitride, or any other suitable material. The gate electrode layer 232b can be formed of any suitable material, such as polysilicon, amorphous silicon, or any other suitable material. Figure 4As further illustrated, another exemplary dimension D4 of the transistor structure 300 includes the distance between the side of the field plate structure 302 and the side of the dielectric structure 308. In some embodiments, dimension D4 is included in the range of about 0.03 micrometers to about 0.045 micrometers. If dimension D4 is less than about 0.03 micrometers, the field plate structure 302 may not be patternable using photolithography to form an opening through the field plate structure 302 and in which the dielectric structure 308 is formed. If dimension D4 is greater than about 0.045 micrometers, the device pitch of the transistor structure 300 may be too large to allow for a high density of transistor structures 300 in the semiconductor device 200. Dimension D4 can be included in the range of about 0.03 micrometers to about 0.045 micrometers to satisfy the photolithographic patterning parameters of the dielectric structure 308 while enabling a sufficiently low device pitch of the transistor structure 300. However, other values ​​for dimension D4, as well as ranges other than about 0.03 micrometers to about 0.045 micrometers, are also included within the scope of this disclosure.

[0073] like Figure 4 As further illustrated, an exemplary dimension D5 of the transistor structure includes the distance between adjacent dielectric structures 308. In some embodiments, dimension D5 is included in the range of about 0.25 micrometers to about 0.50 micrometers to satisfy the photolithographic patterning parameters of the dielectric structure 308. However, other ranges of values ​​are also within the scope of this disclosure.

[0074] like Figure 4 As further shown, the exemplary dimension D6 of the transistor structure 300 includes the overlap of the field plate structure 302 and the RPO layer 306 in the x-direction. The overlap of the field plate structure 302 and the RPO layer 306 can be less than the overall x-direction length ( Figure 4 This is denoted as size D7. In some embodiments, size D6 is included in the range of about 0.06 micrometers to about 0.14 micrometers. If size D6 is less than about 0.06 micrometers, defects may occur in the RPO layer 306 due to insufficient resolution of the photoresist pattern used to pattern the RPO layer 306. If size D6 is greater than about 0.14 micrometers, the gate resistance of the gate structure 232 of the transistor structure 300 may not meet the gate resistance threshold. If size D6 is included in the range of about 0.06 micrometers to about 0.14 micrometers, the likelihood of defects forming in the RPO layer 306 and the gate resistance of the gate structure 232 can be reduced. However, other values ​​for size D6 and ranges other than about 0.06 micrometers to about 0.14 micrometers are also included within the scope of this disclosure.

[0075] As mentioned above, providing Figure 4 As an example. Other examples may differ from those regarding... Figure 4 What is described.

[0076] Figures 5A-5Q is a diagram of an exemplary embodiment 500 of forming the transistor structure 300 described herein. In some embodiments, the operations described in connection with Figures 5A-5Q one or more of the operations described are performed using one or more of the semiconductor processing tools 102-114. In some embodiments, the operations described in connection with Figures 5A-5Q one or more of the operations described are performed using another semiconductor processing tool.

[0077] Turning to Figure 5A , a substrate 202 can be provided. The substrate 202 can be provided as a semiconductor wafer, a semiconductor die, and / or another type of semiconductor substrate. In some embodiments, the substrate 202 can be a doped substrate, such as a semiconductor substrate doped with one or more p-type dopants, a semiconductor substrate doped with one or more n-type dopants, and / or another type of doped substrate. In some embodiments, the substrate 202 has a bulk resistivity (or volumetric resistivity) included in a range from about 1 Ohm-cm to about 100 Ohm-cm. However, other ranges of values are within the scope of the present disclosure.

[0078] As Figure 5A further shown, one or more regions of the substrate 202 can be doped. For example, an n-type region 312 can be formed in the substrate 202. As another example, a DPW region 314 can be formed over the n-type region 312 in the substrate 202. As another example, a drift region 316 can be formed over the DPW region 314 in the substrate 202. In some embodiments, the substrate 202 can be provided as a p-type substrate or an n-type substrate, and the channel region 318 can be part of the p-type substrate or the n-type substrate. Alternatively, the n-type region 312 can be a p-type region, and the DPW region 314 can be a deep n-well (DNW) region.

[0079] In some embodiments, the n-type region 312 can be formed using the ion implantation tool 114 by performing an ion implantation operation to implant ions (e.g., n-type ions) into the substrate 202 to form the n-type region 312. The ion implantation tool 114 can be used to direct an ion beam to the substrate 202 such that the ions are implanted below the surface of the substrate 202 to dope the substrate 202. Additionally and / or alternatively, the deposition tool 102 can deposit the n-type region 312 in a PVD operation, an ALD operation, a CVD operation, an epitaxy operation, an oxidation operation, in connection with Figure 1 another type of deposition operation described, and / or other suitable deposition operations.

[0080] In some embodiments, an ion implantation tool 114 can be used to form the DPW region 314 by performing an ion implantation operation to implant ions (e.g., p-type ions) into the substrate 202. The ion implantation tool 114 can be used to guide an ion beam to the substrate 202, such that ions are implanted below the surface of the substrate 202 to dope the substrate 202. Additionally and / or as another option, the deposition tool 102 can be used in PVD, ALD, CVD, epitaxial, oxidation, or bonding operations. Figure 1 Depositing DPW zone 314 in another type of deposition operation and / or other suitable deposition operation.

[0081] In some embodiments, an ion implantation tool 114 can be used to form the drift region 316 by performing an ion implantation operation to implant ions (e.g., n-type ions) into the substrate 202. The ion implantation tool 114 can be used to guide an ion beam to the substrate 202, such that ions are implanted below the surface of the substrate 202 to dope the substrate 202. Additionally and / or as another option, the deposition tool 102 can be used in PVD operations, ALD operations, CVD operations, epitaxial operations, oxidation operations, and bonding operations. Figure 1 Deposit drift zone 316 in another type of deposition operation and / or other suitable deposition operation.

[0082] like Figure 5B As shown, the dielectric layer 502 can be formed on and / or on the top surface of the substrate 202. The deposition tool 102 can be used with PVD, ALD, CVD, spin-coating, oxidation (e.g., high-temperature thermal oxidation), and bonding technologies. Figure 1 Another type of deposition technique, and / or another suitable deposition technique, is described to deposit the dielectric layer 502. In some embodiments, after the deposition tool 102 deposits the dielectric layer 502, the planarization tool 110 planarizes the dielectric layer 502.

[0083] like Figure 5CAs shown, a portion of dielectric layer 502 is removed, and the remaining portion of dielectric layer 502 corresponds to the field plate dielectric layer 322b on drift region 316. In some embodiments, a pattern in a photoresist layer is used to etch dielectric layer 502 to form field plate dielectric layer 322b. In these embodiments, deposition tool 102 can be used to form a photoresist layer on dielectric layer 502. Exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. Development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. Etching tool 108 can be used to etch dielectric layer 502 based on the pattern to form field plate dielectric layer 322b from dielectric layer 502. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique to pattern-based etching of the dielectric layer 502.

[0084] like Figure 5D As shown, the gate dielectric layer 322a can be formed on the substrate 202 and adjacent to the field dielectric layer 322b. The gate dielectric layer 322a can be formed in a similar manner to the field dielectric layer 322b described above. The dielectric layer can be deposited (e.g., using deposition tool 102) on the substrate 202 and the field dielectric layer 322b, and the etching tool 108 can be used to remove the portion of the dielectric layer on the field dielectric layer 322b based on a pattern, leaving the remaining portion of the dielectric layer on the substrate as the gate dielectric layer 322a.

[0085] like Figure 5E As shown, the gate material layer 504 is formed above the gate dielectric layer 322a and the field plate dielectric layer 322b. The deposition tool 102 and / or plating tool 112 can be used with CVD, PVD, ALD, electroplating, or a combination thereof. Figure 1 Another deposition technique, and / or another suitable deposition technique, is described to deposit the gate material layer 504. The gate material layer 504 may have multiple segments spanning the substrate 202 with multiple z-direction heights. For example, the segment of the gate material layer 504 on the field dielectric layer 322b may have a higher z-direction height than the segment of the gate material layer 504 on the gate dielectric layer 322a, because the z-direction thickness of the field dielectric layer 322b is greater than the z-direction thickness of the gate dielectric layer 322a.

[0086] like Figures 5F-5H As shown, a portion of the gate material layer 504 can be removed, leaving the remaining portion of the gate material layer 504 corresponding to the gate structure 232 and the field plate structure 302. For example...Figure 5F and Figure 5G As shown, the patterned photoresist layer 506 can be used to etch the gate material layer 504 to remove portions of the gate material layer 504. A hard mask layer 508 can also be formed on the gate material layer 504 to facilitate etching of the gate material layer 504 based on the patterned photoresist layer 506. A deposition tool 102 can be used to deposit the photoresist layer on the hard mask layer 508, an exposure tool 104 can be used to transfer the pattern from the photomask 510 to the photoresist layer, and a development tool 106 can be used to develop the pattern in the photoresist layer to form the patterned photoresist layer 506.

[0087] As described above, by including a dielectric structure 308 in the field plate structure 302, the increased feature density in the patterned photoresist layer 506 for etching the gate material layer 504 (e.g., compared to not including the dielectric structure 308) results in the patterned photoresist layer 506 comprising a densely distributed pattern. This densely distributed pattern allows a greater amount of light flux to be exposed to the photoresist material layer, enabling the gate structure 232 and the field plate structure 302 to be positioned closer together, while increasing the likelihood of fully developing the patterned photoresist layer 506 using the developing tool 106. This increased likelihood of fully developing the patterned photoresist layer 506 reduces the possibility of residual photoresist material remaining on the gate material layer 504, thereby reducing the likelihood of defects occurring during the etching of the gate material layer 504.

[0088] like Figure 5H As shown, the gate structure 232 is formed on the gate dielectric layer 322a, and in some embodiments, also on a portion of the field dielectric layer 322b. The field structure 302 is formed on the field dielectric layer 322b. A patterned photoresist layer 506 is used to form an opening 512 through the field structure 302, wherein the dielectric structure 308 will be formed. The patterned photoresist layer 506 is also used to form a gap 514 between the gate structure 232 and the field structure 302, thereby physically separating the gate structure 232 from the field structure 302.

[0089] like Figure 5I As shown, the offset spacer 516 can be formed on the sidewall of the gate structure 232, the sidewall of the field plate structure 302, the sidewall of the opening 512 through the field plate structure 302, and the sidewall of the gap 514 between the gate structure 232 and the field plate structure 302. The deposition tool 102 can be used with PVD technology, ALD technology, CVD technology, spin coating technology, oxidation technology (e.g., high-temperature thermal oxidation technology), and bonding... Figure 1Another type of deposition technique is described, and / or another suitable deposition technique, to deposit a conformal dielectric material layer. The etch tool 108 can be used to remove portions of the conformal dielectric material layer such that remaining portions of the conformal dielectric material layer remain on the sidewalls of the gate structure 232, on the sidewalls of the field plate structure 302, on the sidewalls of the opening 512 through the field plate structure 302, and on the sidewalls of the gap 514 between the gate structure 232 and the field plate structure 302.

[0090] As shown in FIG. 3, the outer sidewall spacers 324a and 324b and the inner sidewall spacer 326 can be formed on the dielectric structure 308. The outer sidewall spacers 324a and 324b can be formed on the outer sidewalls of the gate structure 232 and the field plate structure 302, and the inner sidewall spacer 326 can be formed on the inner sidewalls of the gate structure 232 and the field plate structure 302. The outer sidewall spacers 324a and 324b and the inner sidewall spacer 326 can be formed on the offset spacers 516. The inner sidewall spacer 326 fills the gap 514 between the gate structure 232 and the field plate structure 302 such that the inner sidewall spacer 326 is a merged sidewall spacer. The dielectric structure 308 also fills the opening 512 through the field plate structure 302. The dielectric structure 308 can be formed on the offset spacers 516 in the opening 512 and can fill the opening 512. Figure 5J The outer sidewall spacers 324a and 324b, the inner sidewall spacer 326, and the dielectric structure 308 can be formed from a dielectric layer deposited over the transistor structure 300. The deposition tool 102 can be used to deposit the dielectric layer using a PVD technique, an ALD technique, a CVD technique, a spin-on technique, an oxidation technique (e.g., a high-temperature thermal oxidation technique), a combination thereof, and / or the like.

[0091] Another type of deposition technique is described, and / or another suitable deposition technique, to deposit a conformal dielectric material layer. The etch tool 108 can be used to remove portions of the conformal dielectric material layer such that remaining portions of the conformal dielectric material layer remain on the sidewalls of the gate structure 232, on the sidewalls of the field plate structure 302, on the sidewalls of the opening 512 through the field plate structure 302, and on the sidewalls of the gap 514 between the gate structure 232 and the field plate structure 302. Figure 1 Another type of deposition technique is described, and / or another suitable deposition technique, to deposit a conformal dielectric material layer. The etch tool 108 can be used to remove portions of the conformal dielectric material layer such that remaining portions of the conformal dielectric material layer remain on the sidewalls of the gate structure 232, on the sidewalls of the field plate structure 302, on the sidewalls of the opening 512 through the field plate structure 302, and on the sidewalls of the gap 514 between the gate structure 232 and the field plate structure 302.

[0092] As shown in FIG. 3, the outer sidewall spacers 324a and 324b and the inner sidewall spacer 326 can be formed on the dielectric structure 308. The outer sidewall spacers 324a and 324b can be formed on the outer sidewalls of the gate structure 232 and the field plate structure 302, and the inner sidewall spacer 326 can be formed on the inner sidewalls of the gate structure 232 and the field plate structure 302. The outer sidewall spacers 324a and 324b and the inner sidewall spacer 326 can be formed on the offset spacers 516. The inner sidewall spacer 326 fills the gap 514 between the gate structure 232 and the field plate structure 302 such that the inner sidewall spacer 326 is a merged sidewall spacer. The dielectric structure 308 also fills the opening 512 through the field plate structure 302. The dielectric structure 308 can be formed on the offset spacers 516 in the opening 512 and can fill the opening 512. Figure 5KAs shown, one or more isolation regions 320 may be formed in the substrate 202. Forming one or more isolation regions 320 may include doping the substrate 202 with a p-type dopant or an n-type dopant using an ion implantation tool 114. Source / drain regions 228a may be formed on a first side adjacent to the gate structure 232 (e.g., the side opposite to the side facing the field plate structure 302), and source / drain regions 228b may be formed on a side adjacent to the field plate structure 302 (e.g., the side opposite to the side facing the gate structure 232). Forming source / drain regions 228a and 228b may include doping the substrate 202 with a p-type dopant or an n-type dopant using an ion implantation tool 114.

[0093] like Figure 5L As shown, the RPO layer 306 is formed on the outer wall spacer 324b located on the outer wall of the field plate structure 302. Additionally, the RPO layer 306 is formed on a portion of the top surface of the field plate structure 302. The deposition tool 102 can be used to deposit the RPO layer 306 using CVD, ALD, PVD, and / or another type of deposition technique. In some embodiments, the deposition tool 102 deposits the RPO layer 306 as a blanket covering the transistor structure 300. The RPO layer 306 initially covers structures and layers such as the gate structure 232 and the field plate structure 302 of the transistor structure 300. Subsequently, a portion of the RPO layer 306 can be removed from the gate structure 232 (e.g., so that the RPO layer 306 is no longer located on the gate structure 232) and from a portion of the field plate structure 302 using an etching tool 108, such that the RPO layer 306 remains on less than the entire field plate structure 302.

[0094] like Figure 5M As shown, ESL 208 can be formed on and / or on transistor structure 300. ESL 208 covers source / drain regions 228a and 228b, gate structure 232, field plate structure 302, and RPO layer 306, etc. Deposition tool 102 can be used to conformally deposit ESL 208 using CVD technology, ALD technology, PVD technology, and / or another type of deposition technology.

[0095] like Figure 5N and Figure 5O As shown, dielectric layer 210 can be deposited over ESL 208. Deposition tool 102 can be used to deposit dielectric layer 210 using CVD, ALD, PVD, and / or another type of deposition technique. In some embodiments, planarization tool 110 is used to planarize dielectric layer 210 after deposition.

[0096] like Figure 5N and Figure 5OFurther shown, source / drain contacts 230a and 230b, gate contact 242, and field plate contact 304 can be formed in dielectric layer 210 and through ESL 208. Source / drain contact 230a can be formed on source / drain region 228a, source / drain contact 230b can be formed on source / drain region 228b, gate contact 242 can be formed on gate structure 232, and field plate contact 304 can be formed on field plate structure 302.

[0097] To form source / drain contacts 230a and 230b, gate contact 242, and field plate contact 304, recesses through ESL 208 can be formed in dielectric layer 210. The recesses can be formed over source / drain regions 228a and 228b, over gate structure 232, and over field plate structure 302 such that source / drain regions 228a and 228b, gate structure 232, and field plate structure 302 are exposed by the recesses. In some implementations, a pattern in a photoresist layer is used to etch dielectric layer 210 and ESL 208 to form the recesses. In these implementations, deposition tool 102 can be used to form a photoresist layer on dielectric layer 210. Exposure tool 104 can be used to expose the photoresist layer to a source of radiation to pattern the photoresist layer. Development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. Etching tool 108 can be used to etch dielectric layer 210 and ESL 208 based on the pattern to form the recesses. In some implementations, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some implementations, a photoresist removal tool can be used to remove remaining portions of the photoresist layer (e.g., using a chemical stripper, a plasma ashing, and / or other techniques). In some implementations, a hard mask layer is used as an alternative technique to etch dielectric layer 210 and ESL 208 based on the pattern.

[0098] Deposition tool 102 and / or plating tool 112 can be used to deposit source / drain contacts 230a and 230b, gate contact 242, and field plate contact 304 in the recesses using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, another deposition technique described above in connection with Figure 1 deposition tool 102 and / or plating tool 112 can be used to deposit source / drain contacts 230a and 230b, gate contact 242, and field plate contact 304 in the recesses using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, another deposition technique described above in connection with

[0099] As Figure 5P and Figure 5QAs shown, ESL 212 can be formed on dielectric layer 210, and dielectric layer 214 can be formed on ESL 212. Deposition tool 102 can be used to deposit ESL 212 and dielectric layer 214 using CVD techniques, ALD techniques, PVD techniques, and / or another type of deposition technique. In some implementations, planarization tool 110 is used to planarize ESL 212 and / or dielectric layer 214 after deposition of ESL 212 and / or dielectric layer 214.

[0100] As shown, ESL 212 can be formed on dielectric layer 210, and dielectric layer 214 can be formed on ESL 212. Deposition tool 102 can be used to deposit ESL 212 and dielectric layer 214 using CVD techniques, ALD techniques, PVD techniques, and / or another type of deposition technique. In some implementations, planarization tool 110 is used to planarize ESL 212 and / or dielectric layer 214 after deposition of ESL 212 and / or dielectric layer 214. Figure 5P Figure 5Q As further shown, interconnects 238a, 238b, and 240 can be formed in dielectric layer 214 and through ESL 212. Interconnect 238a can be formed on source / drain contact 230a and on field plate contact 304 (e.g., such that source / drain region 228a is electrically coupled with field plate structure 302). Interconnect 238b can be formed on source / drain contact 230b. Interconnect 240 can be formed on gate contact 242.

[0101] To form interconnects 238a, 238b, and 240, recesses can be formed in dielectric layer 214 and through ESL 212. The recesses can be formed over source / drain contacts 230a and 230b, over gate contact 242, and over field plate contact 304, such that source / drain contacts 230a and 230b, gate contact 242, and field plate contact 304 are exposed by the recesses. In some implementations, a pattern in a photoresist layer is used to etch dielectric layer 214 and ESL 212 to form the recesses. In these implementations, deposition tool 102 can be used to form a photoresist layer on dielectric layer 214. Exposure tool 104 can be used to expose the photoresist layer to a source of radiation to pattern the photoresist layer. Development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. Etching tool 108 can be used to etch dielectric layer 214 and ESL 212 based on the pattern to form the recesses. In some implementations, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some implementations, a photoresist removal tool can be used to remove remaining portions of the photoresist layer (e.g., using a chemical stripper, a plasma ashing, and / or other techniques). In some implementations, a hard mask layer is used as an alternative technique to etch dielectric layer 214 and ESL 212 based on the pattern.

[0102] Deposition tool 102 and / or plating tool 112 can be used to deposit interconnects 238a, 238b, and 240 using CVD techniques, PVD techniques, ALD techniques, electroplating techniques, and / or another type of deposition technique. In some implementations, planarization tool 110 is used to planarize interconnects 238a, 238b, and 240 after deposition of interconnects 238a, 238b, and 240. Figure 1 ​Another deposition technique described, and / or another suitable deposition technique, deposits interconnects 238a, 238b, and 240 in the recesses. In some implementations, planarization tool 110 is used to planarize interconnects 238a, 238b, and / or 240 after the interconnects 238a, 238b, and / or 240 are deposited.

[0103] As described above, provide Figures 5A-5Q as an example. Other examples can differ from what is described Figures 5A-5Q in the description.

[0104] Figures 6A-6C is a diagram of an exemplary implementation of the transistor structure 300 described herein. Figure 6A is a diagram of an exemplary implementation 600 of the transistor structure 300, in which a dielectric structure 602, rather than the dielectric structure 308, is included in and passes through the field plate structure 302 of the transistor structure 300. The dielectric structure 602 includes an elongated dielectric trench that extends through the field plate structure 302 between a top surface and a bottom surface of the field plate structure 302. The dielectric structure 602 can extend substantially parallel to the field plate structure 302 in the y-direction, and can be aligned in the x-direction.

[0105] Figure 6B Exemplary implementation 606 is shown in which the dielectric structure 602 can extend substantially perpendicular to the field plate structure 302 in the x-direction, and can be aligned in the y-direction.

[0106] The dielectric structure 602 can be formed using a lower complexity mask than the dielectric structure 308, while still providing the RESURF effect 604 in the y-direction (in exemplary implementation 600) or in the x-direction (in exemplary implementation 606). However, the dielectric structure 308 is capable of providing the RESURF effect 310 in both the x-direction and the y-direction.

[0107] Figure 6C is a diagram of an exemplary implementation 608 of the transistor structure 300, in which the field plate structure 302 includes a combination of one or more dielectric structures 308 and one or more dielectric structures 602.

[0108] As described above, provide Figures 6A-6C as an example. Other examples can differ from what is described Figures 6A-6C in the description.

[0109] Figure 7This is a diagram of exemplary components of the apparatus 700 described herein. In some embodiments, one or more of the semiconductor processing tools 102 to 114 and / or the wafer / die transport vehicle 116 may include one or more apparatuses 700 and / or one or more components of apparatus 700. Figure 7 As shown, the device 700 may include a bus 710, a processor 720, a memory 730, an input component 740, an output component 750, and / or a communication component 760.

[0110] Bus 710 may include one or more components that enable wired and / or wireless communication between components of device 700. Bus 710 can... Figure 7 Two or more components are coupled together (e.g., via operative coupling, communicative coupling, electrical coupling, and / or electronic coupling). For example, bus 710 may include electrical connections (e.g., wires, traces, and / or leads) and / or a wireless bus. Processor 720 may include a central processing unit, graphics processing unit, microprocessor, controller, microcontroller, digital signal processor, field-programmable gate array, application-specific integrated circuit, and / or another type of processing component. Processor 720 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 720 may include one or more processors capable of being programmed to perform one or more operations or processes described elsewhere herein.

[0111] Memory 730 may include volatile memory and / or non-volatile memory. For example, memory 730 may include random access memory (RAM), read-only memory (ROM), a hard disk drive, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory). Memory 730 may include internal memory (e.g., RAM, ROM, or a hard disk drive) and / or removable memory (e.g., removable via a Universal Serial Bus connection). Memory 730 may be a non-transitory computer-readable medium. Memory 730 may store information related to the operation of device 700, one or more instructions, and / or software (e.g., one or more software applications). In some embodiments, memory 730 may include one or more memories coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 720) via bus 710. The communication coupling between the processor 720 and the memory 730 enables the processor 720 to read and / or process information stored in the memory 730 and / or store information in the memory 730.

[0112] Input component 740 can enable device 700 to receive input, such as user input and / or sensed input. For example, input component 740 can include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system sensor, a global navigation satellite system sensor, an accelerometer, a gyroscope, and / or an actuator. Output component 750 can enable device 700 to provide output, such as via a display, a speaker, and / or a light emitting diode. Communication component 760 can enable device 700 to communicate with other devices via wired and / or wireless connections. For example, communication component 760 can include a receiver, a transmitter, a transceiver, a modem, a network adapter, and / or an antenna.

[0113] Device 700 can perform one or more operations or processes set forth herein. For example, a non-transitory computer-readable medium (e.g., memory 730) can store a set of instructions (e.g., one or more instructions or code) for execution by processor 720. Processor 720 can execute the set of instructions to perform one or more operations or processes set forth herein. In some embodiments, execution of the set of instructions by one or more processors 720 enables the one or more processors 720 and / or device 700 to perform one or more operations or processes set forth herein. In some embodiments, hardwired circuitry can be used in place of or in combination with the instructions to perform one or more operations or processes set forth herein. Additionally, or alternatively, processor 720 can be configured to perform one or more operations or processes set forth herein. Thus, embodiments set forth herein are not limited to any specific combination of hardware and software.

[0114] Figure 7 The number and arrangement of components shown in FIG. 8 are provided as an example. Device 700 can include additional components, fewer components, different components, or differently arranged components than those shown in FIG. 8. Additionally, or alternatively, a set of components (e.g., one or more components) of device 700 can perform one or more functions described as being performed by another set of components of device 700. Figure 7 Device 700 can include additional components, fewer components, different components, or differently arranged components than those shown in FIG. 8. Additionally, or alternatively, a set of components (e.g., one or more components) of device 700 can perform one or more functions described as being performed by another set of components of device 700.

[0115] Figure 8 is a flow diagram of an example process 800 associated with forming a semiconductor device as described herein. In some embodiments, one or more of the process blocks of process 800 are performed using one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-114). Additionally, or alternatively, Figure 8 one or more process blocks of process 800 are performed using one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-114). Additionally, or alternatively, Figure 8One or more process blocks can be performed using one or more components of the apparatus 700 (e.g., the processor 720, the memory 730, the input component 740, the output component 750, and / or the communication component 760).

[0116] As shown, the process 800 can include forming a gate material layer over a substrate of a semiconductor device (block 810). For example, one or more of the semiconductor processing tools 102-114 can be used to form the gate material layer 504 over the substrate 202 of the semiconductor device 200, as described herein. Figure 8

[0117] As further shown, the process 800 can include forming a patterned photoresist layer over the gate material layer (block 820). For example, one or more of the semiconductor processing tools 102-114 can be used to form the patterned photoresist layer 506 over the gate material layer 504, as described herein. Figure 8

[0118] As further shown, the process 800 can include etching the gate material layer using the patterned photoresist layer to form gate structures of transistor structures included in the semiconductor device, field plate structures adjacent to a first side of the gate structures of the transistor structures, and at least one opening through the field plate structures (block 830). For example, one or more of the semiconductor processing tools 102-114 can be used to etch the gate material layer 504 using the patterned photoresist layer 506 to form the gate structures 232 of the transistor structures 300 included in the semiconductor device 200, the field plate structures 302 adjacent to a first side of the gate structures 232 of the transistor structures 300, and at least one opening 512 through the field plate structures 302, as described herein. Figure 8

[0119] As further shown, the process 800 can include forming at least one dielectric structure in the at least one opening through the field plate structures (block 840). For example, one or more of the semiconductor processing tools 102-114 can be used to form at least one dielectric structure (e.g., the dielectric structure 308, the dielectric structure 602) in the at least one opening 512 through the field plate structures 302, as described herein. Figure 8

[0120] As further shown, the process 800 can include forming at least one dielectric structure in the at least one opening through the field plate structures (block 840). For example, one or more of the semiconductor processing tools 102-114 can be used to form at least one dielectric structure (e.g., the dielectric structure 308, the dielectric structure 602) in the at least one opening 512 through the field plate structures 302, as described herein. Figure 8 ​​​​Further shown, process 800 can include forming a first source / drain region of a transistor structure in the substrate (block 850). For example, one or more of semiconductor processing tools 102-114 can be used to form first source / drain region 228a of transistor structure 300 in substrate 202, as described herein. In some implementations, first source / drain region 228a is adjacent a second side of gate structure 232 opposite the first side.

[0121] As Figure 8 Further shown, process 800 can include forming a second source / drain region of a transistor structure in the substrate (block 860). For example, one or more of semiconductor processing tools 102-114 can be used to form second source / drain region 228b of transistor structure 300 in substrate 202, as described herein. In some implementations, second source / drain region 228b is adjacent field plate structure 302.

[0122] Process 800 can include additional implementations, such as any single implementation or any combination of implementations described below and / or in conjunction with one or more other processes described elsewhere herein.

[0123] In a first implementation, process 800 includes forming a plurality of offset spacers 516 in a plurality of openings 512, wherein forming the at least one dielectric structure includes forming a plurality of dielectric structures after forming the plurality of offset spacers 516.

[0124] In a second implementation, alone or in combination with the first implementation, the plurality of dielectric structures have a concave top surface.

[0125] In a third implementation, alone or in combination with one or more of the first and second implementations, process 800 includes forming a merged sidewall spacer (e.g., inner sidewall spacer 326) between gate structure 232 and field plate structure 302.

[0126] In a fourth implementation, alone or in combination with one or more of the first through third implementations, the merged sidewall spacer has a concave top surface.

[0127] In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, process 800 includes forming RPO layer 306 on gate structure 232 and on field plate structure 302, and removing a portion of RPO layer 306 from gate structure 232 such that a remaining portion of RPO layer 306 remains on field plate structure 302.

[0128] In a sixth implementation, alone or in combination with one or more of the first through fifth implementations, the process 800 includes removing another portion of the RPO layer 306 from the field plate structure 302 such that a remaining portion of the RPO layer 306 remains on less than an entirety of the field plate structure 302.

[0129] Although Figure 8 An example block of the process 800 is shown, but in some implementations, the process 800 includes additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in FIG. 8. Additionally or alternatively, two or more of the blocks in the process 800 can be performed in parallel. Figure 8

[0130] In this way, a transistor structure (e.g., a high voltage transistor) includes a field plate structure and at least one dielectric structure that passes through the field plate structure. In a top view of the transistor structure, the dielectric structure can be arranged in a grid. The dielectric structure enables the field plate structure to be positioned closer to a gate structure of the transistor than if the dielectric structure were not present, which enables the length of the field plate structure to be increased without increasing (or with minimal increase in) the overall length of the transistor.

[0131] As set forth in greater detail above, some implementations set forth herein provide a semiconductor device. The semiconductor device includes a first source / drain region in a substrate. The semiconductor device includes a second source / drain region in the substrate. The semiconductor device includes a gate structure over the substrate and between the first source / drain region and the second source / drain region. The semiconductor device includes a field plate structure over the substrate and between the gate structure and the second source / drain region. The semiconductor device includes at least one dielectric structure that passes through the field plate structure.

[0132] In some embodiments, the at least one dielectric structure includes a plurality of dielectric plugs. In some embodiments, in a top view of the semiconductor device, the plurality of dielectric plugs are arranged in a plurality of columns in a first direction; and in a top view of the semiconductor device, the plurality of dielectric plugs are arranged in a plurality of rows in a second direction different from the first direction. In some embodiments, the at least one dielectric structure includes a plurality of dielectric trenches. In some embodiments, the semiconductor device further includes a first outer sidewall spacer on a first sidewall of the gate structure, a second outer sidewall spacer on a first sidewall of the field plate structure, and an inner sidewall spacer on a second sidewall of the gate structure and on a second sidewall of the field plate structure. In some embodiments, the inner sidewall spacer extends between the second sidewall of the gate structure and the second sidewall of the field plate structure. In some embodiments, the at least one dielectric structure extends continuously between a top surface of the field plate structure and a bottom surface of the field plate structure.

[0133] ​As set forth in greater detail above, some embodiments set forth herein provide a method. The method includes forming a gate material layer over a substrate of a semiconductor device. The method includes forming a patterned photoresist layer over the gate material layer. The method includes etching the gate material layer with the patterned photoresist layer to form a gate structure of a transistor structure included in the semiconductor device, a field plate structure of the transistor structure adjacent to a first side of the gate structure, and at least one opening through the field plate structure. The method includes forming at least one dielectric structure in the at least one opening through the field plate structure. The method includes forming a first source / drain region of the transistor structure in the substrate, wherein the first source / drain region is adjacent to a second side of the gate structure opposite the first side. The method includes forming a second source / drain region of the transistor structure in the substrate, wherein the second source / drain region is adjacent to the field plate structure.

[0134] In some embodiments, the method further includes forming at least one offset spacer in the at least one opening, wherein forming the at least one dielectric structure includes forming the at least one dielectric structure after forming the at least one offset spacer. In some embodiments, the at least one dielectric structure has a concave top surface. In some embodiments, the method further includes forming a merged sidewall spacer between the gate structure and the field plate structure. In some embodiments, the merged sidewall spacer has a concave top surface. In some embodiments, the method further includes forming a resist protective oxide (RPO) layer on the gate structure and on the field plate structure, and removing a portion of the RPO layer from the gate structure such that a remaining portion of the RPO layer remains on the field plate structure. In some embodiments, the method further includes removing another portion of the RPO layer from the field plate structure such that a remaining portion of the RPO layer remains on a portion of the field plate structure.

[0135] As set forth in greater detail above, some embodiments set forth herein provide a semiconductor device. The semiconductor device includes a first source / drain region in a substrate. The semiconductor device includes a second source / drain region in the substrate. The semiconductor device includes a gate structure over the substrate and between the first source / drain region and the second source / drain region. The semiconductor device includes a field plate structure over the substrate and between the gate structure and the second source / drain region. The semiconductor device includes a plurality of dielectric structures through the field plate structure. The semiconductor device includes an RPO layer on a portion of an overall length of the field plate structure.

[0136] As set forth in greater detail above, some embodiments set forth herein provide a semiconductor device. The semiconductor device includes a source / drain region in a substrate. The semiconductor device includes a gate structure over the substrate and adjacent to the source / drain region. The semiconductor device includes a field plate structure over the substrate and between the gate structure and the source / drain region. The semiconductor device includes a first dielectric structure through the field plate structure. The semiconductor device includes a second dielectric structure adjacent to the first dielectric structure and through the field plate structure. The semiconductor device includes an RPO layer on a portion of an overall length of the field plate structure. The RPO layer is included over the second dielectric structure and not over the first dielectric structure.

[0137] In some embodiments, the semiconductor device further includes a third dielectric structure through the field plate structure, where the third dielectric structure is adjacent to the first dielectric structure, and where the second dielectric structure extends alongside the first and third dielectric structures. In some embodiments, a first end of the RPO layer is located proximate to the source / drain region; and a second end of the RPO layer, opposite the first end, is located on the field plate structure. In some embodiments, the second end of the RPO layer is located between the first and second dielectric structures. In some embodiments, the first dielectric structure includes a dielectric plug. In some embodiments, the second dielectric structure includes a dielectric trench.

[0138] As used herein, "satisfies a threshold" can refer to being greater than the threshold, being greater than or equal to the threshold, being less than the threshold, being less than or equal to the threshold, being equal to the threshold, not being equal to the threshold, or similar values, depending on the context.

[0139] Finally, it should be noted that the above-mentioned embodiments are merely used to illustrate the technical solutions of the present application, rather than limiting them; even though the above-mentioned embodiments of the present application have been described in detail, those skilled in the art should understand that the technical solutions recorded in the above-mentioned embodiments can be modified, or some or all of the technical features can be replaced equivalently; and these modifications or replacements do not cause the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that, include: The first source / drain region is located in the substrate; The second source / drain region is located in the substrate; A gate structure is located on the substrate and between the first source / drain region and the second source / drain region; A field plate structure is located on the substrate and between the gate structure and the second source / drain region; as well as At least one dielectric structure passes through the field plate structure.

2. The semiconductor device according to claim 1, characterized in that, The at least one dielectric structure includes a plurality of dielectric plugs.

3. The semiconductor device according to claim 2, characterized in that, In a top view of the semiconductor device, the plurality of dielectric plugs are arranged in multiple columns in a first direction; and In a top view of the semiconductor device, the plurality of dielectric plugs are arranged in multiple rows in a second direction different from the first direction.

4. The semiconductor device according to claim 1, characterized in that, The at least one dielectric structure includes a plurality of dielectric trenches.

5. The semiconductor device according to claim 1, characterized in that, Also includes: The first outer sidewall separator is located on the first sidewall of the gate structure; The second outer sidewall separator is located on the first sidewall of the field plate structure; as well as The inner sidewall separator is located on the second sidewall of the gate structure and the second sidewall of the field plate structure.

6. The semiconductor device according to claim 5, characterized in that, The inner sidewall separator extends between the second sidewall of the gate structure and the second sidewall of the field plate structure.

7. The semiconductor device according to claim 1, characterized in that, The at least one dielectric structure extends continuously between the top surface and the bottom surface of the field plate structure.

8. A semiconductor device, characterized in that, include: The source / drain regions are located in the substrate; A gate structure is located on the substrate and adjacent to the source / drain regions; A field plate structure is located on the substrate and between the gate structure and the source / drain regions; A first dielectric structure passes through the field plate structure; The second dielectric structure is adjacent to the first dielectric structure and passes through the field plate structure; as well as The resistive protective oxide layer is located on a portion of the overall length of the field plate structure. The resistive protective oxide layer is included on the second dielectric structure but not on the first dielectric structure.

9. The semiconductor device according to claim 8, characterized in that, The first end of the resistive protective oxide layer is located adjacent to the source / drain region; and The second end of the resistive protective oxide layer, opposite to the first end, is located on the field plate structure.

10. The semiconductor device according to claim 9, characterized in that, The second end of the resistive protective oxide layer is located between the first dielectric structure and the second dielectric structure.

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