Chip packaging structure and electronic equipment

Abstract

The utility model discloses a chip packaging structure and an electronic device. The chip packaging structure comprises a chip, a substrate layer, an ACF glue layer and a sealing structure. The ACF adhesive layer is arranged between the chip and the base material layer, and the chip and the base material layer are electrically connected through the ACF adhesive layer; the sealing structure is connected with the base material layer in a sealed mode, and the sealing structure is further located on the periphery of the ACF adhesive layer and used for sealing the ACF adhesive layer. According to the chip packaging structure, the chip and the base material layer are connected through the ACF adhesive layer, the ACF adhesive layer can achieve directional conduction, and the chip and the base material layer are electrically connected. Compared with a traditional complex routing scheme, the scheme has the advantages that the yield is higher, the reliability is better, meanwhile, the circuit connection distance is greatly shortened, the resistance is smaller, and the electrical performance is better.

Description

Technical Field

[0001] This utility model relates to the field of chip packaging technology, and in particular to a chip packaging structure and electronic device. Background Technology

[0002] Existing chip packaging solutions mainly involve bonding the chip to the surface of a substrate layer, processing pads on the chip surface, and connecting the chip and the substrate layer with metal wires. This process is complex, and the metal wires are prone to problems such as short circuits, open circuits, or craters, resulting in poor yield and reliability of the chip packaging structure. Utility Model Content

[0003] This utility model provides a chip packaging structure and electronic device to solve the problems of complex processing, poor yield and reliability of existing chip packaging structures.

[0004] A chip packaging structure includes a chip, a substrate layer, an ACF adhesive layer, and a sealing structure;

[0005] The ACF adhesive layer is disposed between the chip and the substrate layer, and the chip and the substrate layer are electrically connected through the ACF adhesive layer;

[0006] The sealing structure is sealed to the substrate layer, and the sealing structure is also located on the periphery of the ACF adhesive layer for sealing the ACF adhesive layer.

[0007] Preferably, at least one of the chip and the substrate layer is provided with pad protrusions;

[0008] The chip and the substrate layer are electrically connected through the pad protrusions and the conductive particles within the ACF adhesive layer.

[0009] Preferably, the pad protrusion includes a first pad disposed on the surface of the chip opposite to the substrate layer, the ACF adhesive layer is disposed between the first pad and the substrate layer, and the projection of the first pad onto the substrate layer along a first direction at least partially overlaps with the projection of the ACF adhesive layer onto the substrate layer along the first direction; or,

[0010] The pad protrusion includes a second pad disposed on the surface of the substrate layer opposite to the chip. The ACF adhesive layer is disposed between the second pad and the chip. The projection of the second pad onto the chip along the first direction at least partially overlaps with the projection of the ACF adhesive layer onto the chip along the first direction; or...

[0011] The pad protrusion includes a first pad and a second pad. The first pad is disposed on the surface of the chip opposite to the substrate layer, and the second pad is disposed on the surface of the substrate layer opposite to the chip. The ACF adhesive layer is disposed between the first pad and the second pad. The projections of the first pad and the second pad on the substrate layer along the first direction at least partially overlap, and the area of ​​the second pad is larger than the area of ​​the first pad.

[0012] Wherein, the first direction is the direction perpendicular to the substrate layer.

[0013] Preferably, the surface of the substrate layer opposite to the first pad is a flat surface, a raised surface, or a recessed surface;

[0014] And / or, the surface of the chip opposite to the second pad is a flat surface, a raised surface, or a recessed surface.

[0015] Preferably, the area of ​​the second pad is larger than the area of ​​the first pad.

[0016] Preferably, a plurality of the first pads are arranged on the surface of the chip opposite to the substrate layer;

[0017] Multiple second pads are arranged on the surface of the substrate layer opposite to the chip.

[0018] Preferably, the substrate layer includes a wafer substrate layer and a non-wafer substrate layer;

[0019] The amorphous substrate layer includes any one of a glass substrate layer, a flexible film substrate layer, an epoxy-based material layer, a benzocyclobutane material layer, a polyimide substrate layer, and a fiber substrate layer.

[0020] Preferably, the amorphous substrate layer includes an ink region and a window region disposed within the ink region;

[0021] The second pad is disposed within the window opening area; the ACF adhesive layer is attached to the window opening area;

[0022] The area of ​​the windowed region is larger than the area of ​​the chip;

[0023] The depth of the windowed area is 5um-100um.

[0024] Preferably, the thickness of the pad protrusion is 1µm to 100µm, and the area of ​​the pad protrusion is 100µm² to 30000µm².

[0025] Preferably, the thickness of the chip is 50um to 800um; the thickness of the ACF adhesive layer is 3um to 30um; the diameter of the conductive particles is 1um to 50um; the ACF adhesive layer passes the electrical test within the temperature range of -65℃ to 150℃; and the high-temperature operating temperature of the ACF adhesive layer is not lower than 180℃.

[0026] Preferably, the sealing structure includes a molding compound that encapsulates the chip, the molding compound is sealed to the side of the ACF adhesive layer, and the molding compound is sealed to the side of the substrate layer closest to the chip.

[0027] Alternatively, the sealing structure includes a dispensing structure that is sealed to the side of the chip, sealed to the side of the ACF adhesive layer, and sealed to the side of the substrate layer closest to the chip.

[0028] Alternatively, the sealing structure includes a sealing cap that is sealed to the substrate layer, the sealing cap and the substrate layer cooperating to form a sealed space, and the chip and the ACF adhesive layer are disposed within the sealed space.

[0029] Preferably, the sealing structure is an epoxy sealing structure, a polyimide sealing structure, or a fiber sealing structure.

[0030] Preferably, the chip packaging structure further includes solder balls disposed on the surface of the substrate layer away from the ACF adhesive layer.

[0031] A method for manufacturing a chip package structure, comprising:

[0032] An ACF adhesive layer is attached to the surface of at least one of a chip and a substrate layer, such that the ACF adhesive layer is disposed between the chip and the substrate layer, and the chip and the substrate layer are hot-pressed to make the chip and the substrate layer electrically connected through the ACF adhesive layer;

[0033] A sealing structure for sealing the ACF adhesive layer is processed on the surface of the substrate layer.

[0034] Preferably, attaching the ACF adhesive layer to the surface of at least one of the chip and the substrate layer, such that the ACF adhesive layer is disposed between the chip and the substrate layer, includes:

[0035] Pad protrusions are processed on the surface of at least one of the chip and the substrate layer; the ACF adhesive layer is attached to the surface of the chip opposite to the substrate layer, or the ACF adhesive layer is attached to the surface of the substrate layer opposite to the chip, such that the ACF adhesive layer is disposed between the chip and the substrate layer.

[0036] Preferably, the pad protrusion includes at least one of a first pad and a second pad;

[0037] The method of processing pad protrusions on the surface of at least one of the chip and the substrate layer; attaching the ACF adhesive layer to the surface of the chip opposite to the substrate layer, or attaching the ACF adhesive layer to the surface of the substrate layer opposite to the chip, such that the ACF adhesive layer is disposed between the chip and the substrate layer, includes:

[0038] The first pad is processed on the surface of the chip opposite to the substrate layer; the ACF adhesive layer is attached to the surface of the first pad, or the ACF adhesive layer is attached to the surface of the substrate layer opposite to the chip, such that the ACF adhesive layer is disposed between the first pad and the substrate layer, and the projection of the first pad on the substrate layer along a first direction at least partially overlaps with the projection of the ACF adhesive layer on the substrate layer along the first direction; or...

[0039] The second pad is processed on the surface of the substrate layer opposite to the chip; the ACF adhesive layer is attached to the surface of the second pad, or the ACF adhesive layer is attached to the surface of the chip opposite to the substrate layer, such that the ACF adhesive layer is disposed between the second pad and the chip, and the projection of the second pad onto the chip along the first direction at least partially overlaps with the projection of the ACF adhesive layer onto the chip along the first direction; or...

[0040] The first pad is processed on the surface of the chip opposite to the substrate layer, and the second pad is processed on the surface of the substrate layer opposite to the chip; the ACF adhesive layer is attached to the surface of the first pad or the surface of the second pad, such that the ACF adhesive layer is disposed between the first pad and the second pad, and the projections of the first pad and the second pad on the substrate layer along the first direction at least partially overlap, and the area of ​​the second pad is larger than the area of ​​the first pad;

[0041] Wherein, the first direction is the direction perpendicular to the substrate layer.

[0042] Preferably, processing the first pad on the surface of the chip opposite to the substrate layer includes:

[0043] The first pad is processed on one surface of the wafer, the wafer is thinned to the target thickness, and the wafer is cut to obtain the chip with the first pad.

[0044] Preferably, the substrate layer includes a fab substrate layer, and the fab substrate layer includes an ink region;

[0045] Processing the second pad on the surface of the substrate layer opposite to the chip includes:

[0046] An exposure and windowing operation is performed on the ink area of ​​the amorphous substrate layer to obtain a windowed area of ​​the amorphous substrate layer, and the second pad is processed in the windowed area.

[0047] Preferably, the surface processing of pad protrusions on at least one of the chip and the substrate layer includes:

[0048] The pad protrusions are processed on the surface of at least one of the chip and the substrate layer using Fab process, screen printing process, bonding process or metal ball implantation process.

[0049] Preferably, the sealing structure for sealing the ACF adhesive layer is processed on the surface of the substrate layer, comprising:

[0050] The chip is encapsulated using a molding process, and the side of the ACF adhesive layer and the side of the substrate layer near the chip are sealed together to form a molding structure.

[0051] Alternatively, a dispensing process can be used to seal and connect the side of the chip, the side of the ACF adhesive layer, and the side of the substrate layer near the chip, forming a dispensing structure.

[0052] Alternatively, the sealing cap can be sealed to the substrate layer, with the sealing cap and the substrate layer forming a sealed space, and the chip and the ACF adhesive layer disposed within the sealed space.

[0053] Preferably, the manufacturing method further includes: processing solder balls on the surface of the substrate layer away from the ACF adhesive layer using a metal ball implantation process, electroplating process, printing process, screen printing process or chemical plating process.

[0054] An electronic device comprising the aforementioned chip packaging structure.

[0055] The aforementioned chip packaging structure and electronic device connect the chip and substrate layer via an ACF adhesive layer. The ACF adhesive layer enables directional conductivity, achieving an electrical connection between the chip and the substrate layer. Compared to traditional complex wire bonding solutions, this solution offers higher yield, better reliability, significantly shorter circuit connection distances, lower resistance, and better electrical performance. Attached Figure Description

[0056] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 This is a first schematic diagram of the chip packaging structure in one embodiment of the present invention;

[0058] Figure 2 This is a second schematic diagram of the chip packaging structure in one embodiment of the present invention;

[0059] Figure 3 This is a third schematic diagram of the chip packaging structure in one embodiment of the present invention;

[0060] Figure 4 This is a fourth schematic diagram of the chip packaging structure in one embodiment of the present invention;

[0061] Figure 5 This is a fifth schematic diagram of the chip packaging structure in one embodiment of the present invention;

[0062] Figure 6 This is a schematic diagram of the manufacturing process of the chip packaging structure in one embodiment of the present invention.

[0063] In the diagram: 1. Chip; 2. Substrate layer; 21. Ink area; 22. Non-ink area; 23. Windowed area; 3. ACF adhesive layer; 4. Sealing structure; 41. Molding structure; 42. Dispensing structure; 43. Sealing cap; 5. Pad protrusion; 51. First pad; 52. Second pad; 6. Solder ball. Detailed Implementation

[0064] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present utility model.

[0065] It should be understood that this utility model can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this utility model to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout. To fully understand this utility model, detailed structures and steps will be presented in the following description to illustrate the technical solutions proposed by this utility model. Preferred embodiments of this utility model are described in detail below; however, in addition to these detailed descriptions, this utility model may have other embodiments.

[0066] This utility model embodiment provides a chip packaging structure, such as Figures 1-3 As shown, the chip packaging structure includes a chip 1, a substrate layer 2, an ACF adhesive layer 3, and a sealing structure 4. The ACF adhesive layer 3 is disposed between the chip 1 and the substrate layer 2, and the chip 1 and the substrate layer 2 are electrically connected through the ACF adhesive layer 3. The sealing structure 4 is sealed to the substrate layer 2 and is also located around the ACF adhesive layer 3 for sealing the ACF adhesive layer 3.

[0067] The substrate layer 2 contains circuitry and serves as the carrier for the package, enabling interconnection with external signals. The chip 1 is an electronic component manufactured using semiconductor materials and can be of any type, including but not limited to fingerprint recognition chips, photosensitive chips, and ultrasonic recognition chips.

[0068] As an example, the chip packaging structure, during the packaging process, specifically includes: first, attaching an ACF adhesive layer 3 to the surface of chip 1 opposite to the substrate layer 2, or attaching the ACF adhesive layer 3 to the surface of substrate layer 2 opposite to chip 1, such that the ACF adhesive layer 3 is located between chip 1 and substrate layer 2; then, performing a thermo-pressing operation on chip 1 and substrate layer 2 to electrically connect chip 1 and substrate layer 2 through the ACF adhesive layer 3, specifically through the electrical connection of conductive particles within the ACF adhesive layer 3. Next, a sealing structure 4 is processed on the surface of substrate layer 2, such that the sealing structure 4 is sealed to substrate layer 2. This sealing structure 4 is located around the ACF adhesive layer 3, allowing it to seal the ACF adhesive layer 3 and prevent moisture from entering and affecting its conductivity.

[0069] In this example, within the sealing structure 4, chip 1 and substrate layer 2 are electrically connected via ACF adhesive layer 3. That is, chip 1 and substrate layer 2 are positioned opposite each other, with ACF adhesive layer 3 between them. This sealing structure 4 can seal a single chip 1 and its corresponding substrate layer 2, or it can encapsulate multiple chips 1 and their corresponding substrate layers 2, as long as the chip 1 and substrate layer 2 within the sealing structure 4 are electrically connected via ACF adhesive layer 3.

[0070] In this example, chip 1 and substrate layer 2 are connected by ACF adhesive layer 3. ACF adhesive layer 3 enables directional conductivity between chip 1 and substrate layer 2. Compared with traditional complex wire bonding schemes, the chip packaging structure provided in this example has a simpler overall structure, higher yield, and better reliability. Moreover, the packaging process does not require traditional complex wire bonding processes, making it easier to process, easier to promote, and lower in packaging cost. The electrical connection between chip 1 and substrate layer 2 through ACF adhesive layer 3 can also significantly shorten the connection distance between chip 1 and substrate layer 2, resulting in lower resistance and better electrical performance between the two.

[0071] In one embodiment, such as Figures 1-3 As shown, at least one of the chip 1 and the substrate layer 2 is provided with a pad protrusion 5; the chip 1 and the substrate layer 2 are electrically connected through the pad protrusion 5 and the conductive particles in the ACF adhesive layer 3.

[0072] As an example, at least one of chip 1 and substrate layer 2 has pad bumps 5, including the following three cases: First, chip 1 has pad bumps, but substrate layer 2 does not; second, chip 1 does not have pad bumps, but substrate layer 2 has pad bumps; third, chip 1 has pad bumps, and substrate layer 2 also has pad bumps, such as... Figures 1-3 As shown, the pad protrusions on the lower surface of chip 1 are designated as the first pad 51, and the pad protrusions on the upper surface of substrate layer 2 are designated as the second pad 52. The pad protrusions can be fabricated before chip 1 or substrate layer 2 leaves the factory, or during the packaging process after leaving the factory. Furthermore, the fabrication process can employ any technology, as long as at least one of chip 1 and substrate layer 2 forms a conductive protrusion structure on its surface.

[0073] When either chip 1 or substrate layer 2 has pad bumps, and the other does not, the ACF adhesive layer 3 can be attached to the surface of the pad bumps. This ensures electrical connection between chip 1 and substrate layer 2. However, if the ACF adhesive layer 3 is only placed on the surface of the pad bumps and not in the area without pad bumps, air gaps will exist between chip 1 and substrate layer 2. This can easily cause chip 1 and substrate layer 2 to separate, resulting in low reliability. In another embodiment, the ACF adhesive layer 3 can be attached to the surface of an object without pad bumps. That is, the ACF adhesive layer 3 is not only placed on the surface of the pad bumps, but also in the area without pad bumps between chip 1 and substrate layer 2. In this way, the space between chip 1 and substrate layer 2 is filled with the ACF adhesive layer 3, resulting in higher reliability. In this embodiment, the ACF adhesive layer 3 is located between the chip 1 and the substrate layer 2. The chip 1 and the substrate layer 2 are subjected to a thermo-pressing operation so that the chip 1 and the substrate layer 2 are electrically connected through the pad protrusions and the conductive particles in the ACF adhesive layer 3.

[0074] When both chip 1 and substrate layer 2 are provided with pad bumps, the ACF adhesive layer 3 can be attached to at least one of the surfaces of the two pad bumps, so that the ACF adhesive layer 3 is located between the two pad bumps. The chip 1 and substrate layer 2 are subjected to a thermo-pressing operation so that the chip 1 and substrate layer 2 are electrically connected through the pad bumps 5 and the conductive particles in the ACF adhesive layer 3.

[0075] The ACF adhesive layer 3 consists of two parts: a matrix material and conductive particles. The matrix material is mainly composed of thermosetting or thermoplastic resin, providing adhesion and insulation. The conductive particles are mainly composed of metal powder or polymer plastic balls coated with metal, providing conductivity. Usually, an insulating film is wrapped around the conductive particles. Before pressing the ACF adhesive layer 3, the conductive particles are uniformly distributed in the matrix material, do not contact each other, and the insulating film is intact. At this time, the ACF adhesive layer 3 is non-conductive. After pressurizing and heating the ACF adhesive layer 3, the pad protrusions of at least one of the chip 1 and the substrate layer 2 will be pressed into the ACF adhesive layer 3 and come into contact with the conductive particles in the ACF adhesive layer 3. The insulating film that overlaps with the pad protrusions along the first direction is crushed, while the insulating film that does not overlap with the pad protrusions along the first direction is not crushed. This allows the chip 1 and the substrate layer 2 to be electrically connected only in the area where the pad protrusions 5 are located, and not electrically connected in other areas, so as to achieve directional conductivity between the chip 1 and the substrate layer 2. In this example, the ACF adhesive layer 3 at least partially overlaps with the chip 1 and the substrate layer 2 along the first direction to ensure that the chip 1 and the substrate layer 2 achieve directional conductivity through the ACF adhesive layer 3 after hot pressing. Understandably, the ACF adhesive layer 3 can overflow the area where the chip 1 and the substrate layer 2 overlap along the first direction; the overflowed portion is not conductive, and the adhesive properties of the substrate material are mainly used to connect the chip 1 and the substrate layer 2 to ensure the reliability of their connection. In this embodiment, the first direction is perpendicular to the substrate layer 2.

[0076] In one embodiment, the pad protrusion 5 includes a first pad 51 disposed on the surface of the chip 1 opposite to the substrate layer 2, and an ACF adhesive layer 3 disposed between the first pad 51 and the substrate layer 2. The projection of the first pad 51 onto the substrate layer 2 along a first direction at least partially overlaps with the projection of the ACF adhesive layer 3 onto the substrate layer 2 along the first direction; or,

[0077] The pad bump 5 includes a second pad 52, which is disposed on the surface of the substrate layer 2 opposite to the chip 1. An ACF adhesive layer 3 is disposed between the second pad 52 and the chip 1. The projection of the second pad 52 onto the chip 1 along a first direction at least partially overlaps with the projection of the ACF adhesive layer 3 onto the chip 1 along the first direction; or...

[0078] The pad protrusion 5 includes a first pad 51 and a second pad 52; the first pad 51 is disposed on the surface of the chip 1 opposite to the substrate layer 2, and the second pad 52 is disposed on the surface of the substrate layer 2 opposite to the chip 1; the ACF adhesive layer 3 is disposed between the first pad 51 and the second pad 52, and the projections of the first pad 51 and the second pad 52 onto the substrate layer 2 along a first direction at least partially overlap, and the area of ​​the second pad 52 is larger than the area of ​​the first pad 51;

[0079] The first direction is the direction perpendicular to the substrate layer.

[0080] The first pad 51 is a pad processed on the surface of the chip 1. The second pad 52 is a pad processed on the surface of the substrate layer 2.

[0081] As an example, chip 1 is disposed opposite to substrate layer 2, and ACF adhesive layer 3 is disposed between chip 1 and substrate layer 2. When chip 1 is disposed above substrate layer 2, the top surface of chip 1 is the surface away from substrate layer 2, and the bottom surface of chip 1 is the surface opposite to substrate layer 2; the top surface of substrate layer 2 is the surface opposite to chip 1, and the bottom surface of substrate layer 2 is the surface away from chip 1.

[0082] As an example, such as Figure 3 As shown, the pad protrusion 5 may include a first pad 51 but not a second pad 52. The first pad 51 is disposed on the surface of the chip 1 opposite to the substrate layer 2, for example, it may be disposed on the bottom surface of the chip 1. In this example, a first pad 51 can be processed on the bottom surface of chip 1 using, but not limited to, electroplating, chemical plating, and screen printing processes, so that the first pad 51 protrudes from the bottom surface of chip 1. Then, an ACF adhesive layer 3 is attached to the surface of the first pad 51, or the ACF adhesive layer 3 is attached to the surface of the substrate layer 2 opposite to chip 1 (e.g., the top surface of the substrate layer 2), so that the projection of the first pad 51 on the substrate layer 2 along the first direction at least partially overlaps with the projection of the ACF adhesive layer 3 on the substrate layer 2 along the first direction, to ensure that in the subsequent hot pressing operation, the first pad 51 can break through the ACF adhesive layer 3 that at least partially overlaps with its projection on the substrate layer 2 along the first direction. Finally, a hot pressing operation is performed on chip 1 and substrate layer 2 to make chip 1 and substrate layer 2 electrically connected through the conductive particles in the first pad 51 and ACF adhesive layer 3, thereby achieving directional conductivity between chip 1 and substrate layer 2. In this example, the first pad 51 is processed only on chip 1, and the second pad 52 is not processed on substrate layer 2, which reduces the processing steps and saves processing costs.

[0083] As another example, such as Figure 2As shown, the pad protrusion 5 may include a second pad 52 but not a first pad 51. The second pad 52 is disposed on the surface of the substrate layer 2 opposite to the chip 1, for example, it may be disposed on the top surface of the substrate layer 2. In this example, a second pad 52 can be processed on the top surface of the substrate layer 2 using, but not limited to, electroplating, chemical plating, and screen printing processes, so that the second pad 52 protrudes from the top surface of the substrate layer 2. Then, an ACF adhesive layer 3 is attached to the surface of the second pad 52, or the ACF adhesive layer 3 is attached to the surface of the chip 1 opposite to the substrate layer 2 (e.g., the bottom surface of the chip 1), so that the projection of the second pad 52 on the chip 1 along the first direction at least partially overlaps with the projection of the ACF adhesive layer 3 on the chip 1 along the first direction, so as to ensure that during the subsequent hot pressing operation, the second pad 52 can break through the ACF adhesive layer 3 that at least partially overlaps with its projection on the chip 1 along the first direction. Finally, a hot pressing operation is performed on the chip 1 and the substrate layer 2 so that the chip 1 and the substrate layer 2 are electrically connected through the conductive particles in the ACF adhesive layer 3 and the second pad 52, thereby achieving directional conductivity between the chip 1 and the substrate layer 2. In this example, the second pad 52 is processed only on the substrate layer 2, instead of the first pad 51 on the chip 1, which reduces the processing steps and saves processing costs.

[0084] As yet another example, such as Figure 1 As shown, the pad protrusion 5 may include a first pad 51 and a second pad 52. The first pad 51 is disposed on the surface of the chip 1 opposite to the substrate layer 2, and the second pad 52 is disposed on the surface of the substrate layer 2 opposite to the chip 1. For example, the first pad 51 is disposed on the bottom surface of the chip 1, and the second pad 52 is disposed on the top surface of the substrate layer 2. Both can be processed using, but are not limited to, electroplating, chemical plating, and screen printing. Then, an ACF adhesive layer 3 is attached to the surface of the first pad 51 or the surface of the second pad 52. The projections of the first pad 51 and the second pad 52 on the substrate layer 2 along a first direction at least partially overlap, so that during subsequent hot pressing operations, the first pad 51 and the second pad 52 can break through the ACF adhesive layer 3 that at least partially overlaps with their projections on the substrate layer 2 along a first direction. Finally, a hot pressing operation is performed on the chip 1 and the substrate layer 2 to make the chip 1 and the substrate layer 2 electrically connected through the first pad 51, the conductive particles in the ACF adhesive layer 3, and the second pad 52, thereby achieving directional conductivity between the chip 1 and the substrate layer 2. In this example, chip 1 is provided with a first pad 51, and substrate layer 2 is provided with a second pad 52. The first pad 51 and the second pad 52 are arranged opposite to each other, and their projections along the first direction at least partially overlap, which helps to ensure the conductivity of ACF adhesive layer 3 after hot pressing.

[0085] In this example, the area of ​​the substrate layer 2 is generally larger than the area of ​​the chip 1, and the area of ​​the second pad 52 on the substrate layer 2 is larger than the area of ​​the first pad 51 on the chip 1. This facilitates the vertical alignment of the first pad 51 and the second pad 52, thereby improving the accuracy of the bonding between the two through the ACF adhesive layer 3.

[0086] In one embodiment, the surface of the substrate layer opposite to the first pad is a flat surface, a raised surface, or a recessed surface; and / or, the surface of the chip opposite to the second pad is a flat surface, a raised surface, or a recessed surface.

[0087] As an example, when a first pad 51 is provided on the surface of chip 1 opposite to the substrate layer 2, the surface of the substrate layer 2 opposite to the first pad 51 can be a flat surface, a raised surface, or a recessed surface. When the surface of the substrate layer 2 opposite to the first pad 51 is a raised surface, the raised surface and the first pad 51 form a two-sided raised structure, which makes it easier to form directional conductivity when the ACF adhesive layer 3 is hot-pressed, thus helping to ensure its performance. When the surface of the substrate layer 2 opposite to the first pad 51 is a flat surface, the processing technology is simpler and the cost is lower. When the surface of the substrate layer 2 opposite to the first pad 51 is a recessed surface, specific spatial design requirements can be met.

[0088] As an example, when a second pad 52 is provided on the surface of the substrate layer 2 opposite to the chip 1, the surface of the chip 1 opposite to the second pad 52 can be a flat surface or a raised surface. When the surface of the chip 1 opposite to the second pad 52 is a raised surface, the raised surface and the second pad 52 form a two-sided raised structure, which makes it easier to form directional conductivity when the ACF adhesive layer 3 is hot-pressed, thus helping to ensure its performance. When the surface of the chip 1 opposite to the second pad 52 is a flat surface, the processing technology is simpler and more convenient, and the cost is lower. When the surface of the chip 1 opposite to the second pad 52 is a recessed surface, it can meet specific spatial design requirements.

[0089] In one embodiment, a plurality of first pads 51 are arranged on the surface of the chip 1 opposite to the substrate layer 2; a plurality of second pads 52 are arranged on the surface of the substrate layer 2 opposite to the chip 1.

[0090] As an example, multiple first pads 51 are arranged on the surface of chip 1 opposite to the substrate layer 2. The area of ​​the first pads is 100um² to 30000um², which facilitates the alignment of the first pads 51 with the substrate layer 2 and helps to improve the placement accuracy of the ACF adhesive layer 3 disposed between the first pads 51 and the substrate layer 2.

[0091] As another example, multiple second pads 52 are arranged on the surface of the substrate layer 2 opposite to the chip 1. The area of ​​the second pads is 100um² to 30000um², which facilitates the alignment of the second pads 52 with the chip 1 and helps to improve the placement accuracy of the ACF adhesive layer 3 set between the second pads 52 and the chip 1.

[0092] As another example, multiple first pads 51 are arranged on the surface of chip 1 opposite to the substrate layer 2, and multiple second pads 52 are arranged on the surface of substrate layer 2 opposite to chip 1. The total area of ​​the second pads 52 is larger than the total area of ​​the first pads 51 to facilitate the alignment of the first pads 51 and the second pads 52, which helps improve the placement accuracy of the ACF adhesive layer 3 located between the first pads 51 and the second pads 52. Figure 4 As shown, chip 1 has 4*4 first pads 51, and substrate layer 2 has 4*4 second pads 52. The projections of the 4*4 first pads 51 and the 4*4 second pads overlap in the first direction. In this embodiment, the area of ​​the first pads 51 can be smaller than the area of ​​the second pads 52, which improves the placement accuracy of the ACF adhesive layer 3 disposed between the first pads 51 and the second pads 52. Even if the first pads 51 and the second pads 52 are slightly offset in the first direction, the projections of the first pads 51 and the second pads 52 still overlap in the first direction.

[0093] In one embodiment, the substrate layer 2 includes a wafer substrate layer and an amorphous substrate layer; the amorphous substrate layer includes any one of a glass substrate layer 2, a flexible film substrate layer 2, an epoxy material layer 2, a benzocyclobutane material layer 2, a polyimide substrate layer 2, and a fiber substrate layer 2.

[0094] The wafer substrate layer refers to the substrate layer 2 that uses a wafer as the carrier of chip 1, and the main material of the wafer substrate layer is silicon. As an example, the chip packaging structure includes chip 1 and wafer substrate layer. At least one of chip 1 and wafer substrate layer can be provided with pad bumps 5, so that chip 1 and wafer substrate layer are electrically connected through the pad bumps 5 and conductive particles in ACF adhesive layer 3. The packaging process can be implemented using CoW (Chip on Wafer) packaging technology.

[0095] The amorphous substrate layer refers to the substrate layer 2 that uses materials other than wafers as the carrier of chip 1. As an example, the amorphous substrate layer includes any one of a glass substrate layer 2, a flexible film substrate layer 2, an epoxy resin layer 2, an aromatic benzocyclobutene film (ABF), a polyimide substrate layer 2, and a fiber substrate layer 2. As an example, the chip packaging structure includes chip 1 and the amorphous substrate layer. Pad bumps 5 can be provided on at least one of the chip 1 and the amorphous substrate layer, allowing the chip 1 and the amorphous substrate layer to be electrically connected through the pad bumps 5 and conductive particles in the ACF adhesive layer 3. The packaging process can be implemented using a CoW packaging process. For example, when the amorphous substrate layer is a glass substrate layer 2, a CoG packaging process can be used to package chip 1 and the glass substrate layer 2. As another example, when the amorphous substrate layer is a flexible film substrate layer 2, a COF packaging process can be used to package chip 1 and the flexible film substrate layer 2 (Film).

[0096] In one embodiment, such as Figure 5 As shown, the amorphous substrate layer includes an ink region 21 and a window region 23 disposed within the ink region 21; a second pad 52 is disposed within the window region 23; an ACF adhesive layer 3 is attached within the window region 23; the area of ​​the window region 23 is larger than the area of ​​the chip 1; the depth of the window region 23 is 5um-100um.

[0097] As an example, the amorphous substrate layer is typically coated with ink during processing. Therefore, the amorphous substrate layer usually includes an ink region 21, and may also include a non-ink region 22 located outside the ink region 21. During the packaging process of the chip packaging structure, an exposure windowing operation can be performed on the ink region 21. For example, an exposure windowing operation can be performed on the region of the amorphous substrate layer opposite to the chip 1 using an exposure process, but not limited to, to form an opening region 23 opposite to the chip 1; or, an exposure windowing operation can be performed on the region of the amorphous substrate layer opposite to the first pad 51 using an exposure process, but not limited to, to form an opening region 23 opposite to the first pad 51.

[0098] In one example, during the encapsulation of chip 1 and the amorphous substrate layer, a second pad 52 can be fabricated in the window area 23 of the amorphous substrate layer. This second pad 52 is positioned within the window area 23, allowing it to be electrically connected to chip 1 or the first pad 51 of chip 1 via conductive particles within the ACF adhesive layer 3. Alternatively, if the window area 23 of the amorphous substrate layer does not have a second pad 52, the ACF adhesive layer 3 can be attached to the window area 23, allowing the amorphous substrate layer to be electrically connected to the first pad 51 of chip 1 via conductive particles within the ACF adhesive layer 3, thus completing the encapsulation of chip 1 and the amorphous substrate layer. In this example, the window area 23 is set in the ink area 21 of the amorphous substrate layer, and the second pad 52 or the ACF adhesive layer 3 is attached within the window area 23. This allows for fewer layer stacking processes during the encapsulation of chip 1 and the amorphous substrate layer, helping to save on encapsulation costs.

[0099] As an example, a windowing operation is performed in the ink area 21 of the amorphous substrate layer, so that the area of ​​the formed window area 23 is larger than the area of ​​the chip 1. This helps to facilitate the alignment of the chip 1 with the window area 23 and helps to improve the mounting accuracy of the ACF adhesive layer 3 set between the chip 1 and the substrate layer 2.

[0100] As an example, when the depth of the windowed area 23 is 5um-100um, during the windowing operation, its metal layer is exposed and developed, and the second pad 52 can be processed within this metal layer without the need for additional protrusion processing, which helps to save processes. Moreover, the windowed area 23 itself has an alignment frame, which can ensure the alignment accuracy of the second pad 52 and the ACF adhesive layer 3. If the depth of the windowed area 23 is less than 5um, its metal layer may not be exposed, and the goal required by the windowing operation cannot be achieved. If the depth of the windowed area 23 is greater than 100um, there will be a deeper trench, and when the ACF adhesive layer 3 and the chip 1 are hot-pressed, the ACF adhesive layer 3 is prone to overflow, affecting its reliability.

[0101] In one embodiment, the thickness of the pad protrusion 5 is 1µm to 100µm, and the area of ​​the pad protrusion 5 is 100µm² to 30000µm².

[0102] As an example, any processing technology can be used to process conductive material on at least one of the bottom surface of chip 1 and the top surface of substrate layer 2, so as to process pad protrusions with a thickness of 1um to 100um on the surface of at least one of the bottom surface of chip 1 and the top surface of substrate layer 2, so as to meet the requirement of pressing into ACF adhesive layer 3 and contacting the conductive particles in ACF adhesive layer 3; moreover, the area of ​​pad protrusion 5 is 100um² to 30000um², which meets the production design requirements of chip 1 level packaging process, avoiding the area being too small so that the production equipment cannot meet the corresponding standards, and also avoiding the area being too large so as not to meet the fineness requirements.

[0103] In one embodiment, the thickness of chip 1 is 50µm to 800µm; the thickness of ACF adhesive layer 3 is 3µm to 30µm. In this embodiment, ACF adhesive with a thickness of 5µm to 100µm can be used for hot pressing. During the hot pressing process, the ACF adhesive will overflow. When the thickness of ACF adhesive layer 3 after hot pressing is 3µm to 30µm, both reliability and thinness requirements can be simultaneously met. The diameter of the conductive particles is 1µm to 50µm. ACF adhesive layer 3 passes electrical testing within a thermal cycling test temperature range of -65℃ to 150℃. The high-temperature operating temperature range of ACF adhesive layer 3 is 100℃ to 400℃. A high-temperature operating temperature of not less than 100℃ meets basic requirements. When the high-temperature operating temperature of ACF adhesive layer 3 is not less than 180℃, ACF adhesive layer 3 has stable performance in various environments and higher reliability. When the high-temperature operating temperature of ACF adhesive layer 3 is not less than 400℃, the stability of ACF adhesive layer 3 is higher, but the cost is also higher.

[0104] As an example, the thickness of chip 1 is 50µm to 800µm to meet the size requirements of conventional chip 1. The thickness of ACF adhesive layer 3 is 3µm to 30µm, and the diameter of the conductive particles incorporated into ACF adhesive layer 3 is 1µm to 50µm to meet the packaging requirements of chip-level packaging process; moreover, ACF adhesive layer 3 needs to be selected to be resistant to high and low temperatures. Specifically, ACF adhesive layer 3 passes electrical testing within the thermal cycling test temperature range of -65℃ to 150℃, and the high temperature resistance of ACF adhesive layer 3 is not lower than 180℃ to ensure that ACF adhesive layer 3 has stable performance in various environments, higher reliability, and to ensure the yield of chip packaging structure.

[0105] In one embodiment, the sealing structure 4 includes a molding compound 41, which encapsulates the chip 1, is sealed to the side of the ACF adhesive layer 3, and is sealed to the side of the substrate layer 2 near the chip 1.

[0106] Alternatively, the sealing structure 4 includes a dispensing structure 42, which is sealed to the side of the chip 1, sealed to the side of the ACF adhesive layer 3, and sealed to the side of the substrate layer 2 near the chip 1.

[0107] Alternatively, the sealing structure 4 includes a sealing cover 43, which is sealed to the substrate layer 2. The sealing cover 43 and the substrate layer 1 cooperate to form a sealed space, and the chip 1 and the ACF adhesive layer 3 are disposed in the sealed space.

[0108] As an example, such as Figure 1 As shown, after chip 1 and substrate layer 2 are pressed together into an integrated structure using ACF adhesive layer 3, a molding process can be used to encapsulate chip 1, the sides of ACF adhesive layer 3, and the side of substrate layer 2 near chip 1 to form a molding structure 41. Specifically, the molding structure 41 encapsulates chip 1, covering its top and sides. The molding structure 41 is sealed to the sides of ACF adhesive layer 3 and to the side of substrate layer 2 near chip 1, preventing moisture from entering the ACF adhesive layer 3 and thus ensuring the conductivity of the ACF adhesive layer 3. Here, encapsulating chip 1 specifically means encapsulating its top and sides. For example, when using CoW packaging technology to encapsulate chip 1 and substrate layer 2, the molding structure 41 can encapsulate chip 1 and seal it to the sides of ACF adhesive layer 3 and the side of substrate layer 2 near chip 1. In this example, the molding structure 41 completely covers the chip 1 and the ACF adhesive layer 3, which can achieve full sealing protection for the chip 1 and the ACF adhesive layer 3, and its sealing performance is good.

[0109] As another example, such as Figure 2 As shown, after chip 1 and substrate layer 2 are pressed together into an integrated structure using ACF adhesive layer 3, a dispensing process can be used to apply adhesive to the sides of chip 1, the sides of ACF adhesive layer 3, and the side of substrate layer 2 near chip 1 to form a dispensing structure 42. This dispensing structure 42 is sealed to the sides of chip 1, the sides of ACF adhesive layer 3, and the side of substrate layer 2 near chip 1. This allows the dispensing structure 42 to surround the periphery of ACF adhesive layer 3, sealing the periphery and preventing moisture from entering the ACF adhesive layer 3, thus ensuring the conductivity of ACF adhesive layer 3. For example, when using CoG or CoF packaging technology to encapsulate chip 1 and substrate layer 2, the dispensing structure 42 can be used to encapsulate the sides of chip 1, the sides of ACF adhesive layer 3, and the surface of substrate layer 2 near chip 1. In this example, the dispensing structure 42 seals the side of the connected chip 1 and the side of the ACF adhesive layer 3, achieving a certain sealing effect and reducing processing costs.

[0110] As yet another example, such as Figure 3 As shown, after the chip 1 and the substrate layer 2 are pressed together into an integral structure by the ACF adhesive layer 3, the sealing cap 43 can be sealed to the side of the substrate layer 2 closest to the chip 1 to form a sealed space. The chip 1 and the ACF adhesive layer 3 are located within the sealed space, preventing moisture from entering the ACF adhesive layer 3 through the dispensing structure 42, thereby ensuring the conductivity of the ACF adhesive layer 3. In this example, the sealing cap 43 completely surrounds the chip 1 and the ACF adhesive layer 3, ensuring its sealing performance.

[0111] In this embodiment, the side of the substrate layer 2 closest to the chip 1 is the upper surface of the substrate layer, and the side of the substrate layer 2 furthest from the chip 1 is the bottom surface of the substrate layer.

[0112] In one embodiment, the sealing structure 4 is an epoxy sealing structure, a polyimide sealing structure, or a fiber sealing structure.

[0113] As an example, the sealing structure 4 can be an epoxy sealing structure made of epoxy material, a polyimide sealing structure made of polyimide material, or a fiber sealing structure made of fiber material. The specific structure used can be determined according to actual needs.

[0114] In one embodiment, the chip packaging structure further includes solder balls 6, which are disposed on the surface of the substrate layer 2 away from the ACF adhesive layer 3.

[0115] As an example, the chip package structure also includes solder balls 6, which are electrically connected to the circuitry within the substrate layer 2, enabling the chip package structure to connect to external circuitry, devices, or other structures via the solder balls 6. In this example, the solder balls 6 can be processed using, but is not limited to, metal ball implantation, electroplating, printing, screen printing, and chemical plating processes, as long as the electrical connection and reliability requirements are met.

[0116] This invention provides a method for manufacturing a chip packaging structure, comprising:

[0117] S1: Attach the ACF adhesive layer 3 to the surface of at least one of the chip 1 and the substrate layer 2, and hot-press the chip 1 and the substrate layer 2 so that the ACF adhesive layer 3 is disposed between the chip 1 and the substrate layer 2, and the chip 1 and the substrate layer 2 are electrically connected through the ACF adhesive layer 3.

[0118] S2: A sealing structure 4 for sealing the ACF adhesive layer 3 is processed on the surface of the substrate layer 2.

[0119] As an example, in step S1, the ACF adhesive layer 3 is attached to the surface of the chip 1 opposite to the substrate layer 2, or the ACF adhesive layer 3 is attached to the surface of the substrate layer 2 opposite to the chip 1. The ACF adhesive layer 3 is located between the chip 1 and the substrate layer 2. The chip 1 and the substrate layer 2 are subjected to a thermo-pressing operation so that the chip 1 and the substrate layer 2 are electrically connected through the ACF adhesive layer 3, specifically through the conductive particles in the ACF adhesive layer 3.

[0120] As an example, in step S2, a sealing structure 4 is processed on the surface of the substrate layer 2 so that the sealing structure 4 is sealed to the substrate layer 2. The sealing structure 4 is located on the periphery of the ACF adhesive layer 3 so that the sealing structure 4 can seal the ACF adhesive layer 3 to prevent moisture from entering the ACF adhesive layer 3 and affecting the conductivity of the ACF adhesive layer 3.

[0121] In this example, the ACF adhesive layer 3 is attached to the surface of at least one of the chip 1 and the substrate layer 2, placing the ACF adhesive layer 3 between the chip 1 and the substrate layer 2. The chip 1 and the substrate layer 2 are then thermo-pressed to electrically connect them through the ACF adhesive layer 3. This process eliminates the need for traditional complex wire bonding, reducing processing difficulty, making it easy to implement, and lowering packaging costs. Furthermore, the resulting chip package structure has a simple overall structure, higher yield, and better reliability. It also significantly shortens the connection distance between the chip 1 and the substrate layer 2, resulting in lower resistance and better electrical performance. A sealing structure 4 is sealed to the substrate layer 2 and located around the ACF adhesive layer 3, preventing moisture from entering and affecting its conductivity.

[0122] In one embodiment, step S1, which involves attaching the ACF adhesive layer 3 to the surface of at least one of the chip 1 and the substrate layer 2, such that the ACF adhesive layer 3 is disposed between the chip 1 and the substrate layer 2, includes:

[0123] A pad protrusion 5 is processed on the surface of at least one of the chip 1 and the substrate layer 2; an ACF adhesive layer 3 is attached to the surface of the chip 1 opposite to the substrate layer 2, or the ACF adhesive layer 3 is attached to the surface of the substrate layer 2 opposite to the chip, such that the ACF adhesive layer 3 is disposed between the chip 1 and the substrate layer 2.

[0124] As an example, pad bumps 51 are processed on the surface of chip 1, or pad bumps 52 are processed on the surface of substrate layer 2, or pad bumps 5 are processed on both the surface of chip 1 and substrate layer 2. The pad bumps can be processed before chip 1 or substrate layer 2 leaves the factory, or they can be processed during the packaging process after leaving the factory. Furthermore, the process of processing the pad bumps can use any process, as long as it forms a conductive bump structure on the surface of chip 1 and / or substrate layer 2.

[0125] As an example, the ACF adhesive layer 3 is attached to the surface of the chip 1 opposite to the substrate layer 2, or the ACF adhesive layer 3 is attached to the surface of the substrate layer 2 opposite to the chip, such that the ACF adhesive layer is disposed between the chip 1 and the substrate layer 2. Specifically, when either the chip 1 or the substrate layer 2 has a pad protrusion and the other does not, the ACF adhesive layer 3 can be attached to the surface of the pad protrusion, or the ACF adhesive layer 3 can be attached to the surface of the chip 1 or the substrate layer 2 that at least partially overlaps with the projection of the pad protrusion along the first direction, such that the ACF adhesive layer 3 is located between the chip 1 and the substrate layer 2, so that the chip 1 and the substrate layer 2 can be thermo-pressed to electrically connect the chip 1 and the substrate layer 2 through the pad protrusion 5 and the conductive particles in the ACF adhesive layer 3. When both chip 1 and substrate layer 2 are provided with pad protrusions 5, the ACF adhesive layer 3 can be attached to the surface where either pad protrusion 5 is located, so that the ACF adhesive layer 3 is located between the surfaces where the two pad protrusions are located, so that the chip 1 and substrate layer 2 can be thermo-pressed to make the chip 1 and substrate layer 2 electrically connected through the pad protrusions 5 and the conductive particles in the ACF adhesive layer 3.

[0126] In one embodiment, the pad protrusion 5 includes at least one of a first pad 51 and a second pad 52;

[0127] Processing pad bumps 5 on the surface of at least one of chip 1 and substrate layer 2; attaching ACF adhesive layer 3 to the surface of chip 1 opposite to substrate layer 2, or attaching ACF adhesive layer 3 to the surface of substrate layer 2 opposite to chip, such that ACF adhesive layer 3 is disposed between chip 1 and substrate layer 2, including:

[0128] A first pad 51 is processed on the surface of chip 1 opposite to the substrate layer 2; an ACF adhesive layer 3 is attached to the surface of the first pad 51, or the ACF adhesive layer 3 is attached to the surface of the substrate layer 2 opposite to chip 1, such that the ACF adhesive layer 3 is disposed between the first pad 51 and the substrate layer 2, and the projection of the first pad 51 onto the substrate layer 2 along a first direction at least partially overlaps with the projection of the ACF adhesive layer 3 onto the substrate layer 2 along the first direction; or,

[0129] A second pad 52 is processed on the surface of the substrate layer 2 opposite to the chip 1; an ACF adhesive layer 3 is attached to the surface of the second pad 52, or the ACF adhesive layer 3 is attached to the surface of the chip 1 opposite to the substrate layer 2, such that the ACF adhesive layer 3 is disposed between the second pad 52 and the chip 1, and the projection of the second pad 52 onto the chip 1 along the first direction at least partially overlaps with the projection of the ACF adhesive layer 3 onto the chip 1 along the first direction; or,

[0130] A first pad 51 is processed on the surface of chip 1 opposite to the substrate layer 2, and a second pad 52 is processed on the surface of substrate layer 2 opposite to chip 1; an ACF adhesive layer 3 is attached to the surface of the first pad 51 or to the surface of the second pad 52, such that the ACF adhesive layer 3 is disposed between the first pad 51 and the second pad 52, and the projections of the first pad 51 and the second pad 52 onto the substrate layer 2 along the first direction at least partially overlap.

[0131] As an example, a first pad 51 can be processed on the surface opposite to the substrate layer 2 (e.g., the bottom surface of the chip 1) using processes such as electroplating, chemical plating, and screen printing, so that the first pad 51 protrudes from the bottom surface of the chip 1. Then, an ACF adhesive layer 3 is attached to the surface where the first pad 51 is located, or the ACF adhesive layer 3 is attached to the surface of the substrate layer 2 opposite to the chip 1 (e.g., the top surface of the substrate layer 2), so that the ACF adhesive layer 3 is disposed between the first pad 51 and the substrate layer 2, and the projection of the first pad 51 on the substrate layer 2 along the first direction at least partially overlaps with the projection of the ACF adhesive layer 3 on the substrate layer 2 along the first direction, so as to ensure that in the subsequent hot pressing operation, the first pad 51 can break through the ACF adhesive layer 3 that at least partially overlaps with its projection on the substrate layer 2 along the first direction. Finally, a hot pressing operation is performed on the chip 1 and the substrate layer 2 to make the chip 1 and the substrate layer 2 electrically connected through the ACF adhesive layer 3, thereby achieving directional conductivity between the chip 1 and the substrate layer 2. In this example, the first pad 51 is processed only on chip 1, and the second pad 52 is not processed on substrate layer 2, which reduces the processing steps and saves processing costs.

[0132] As an example, a second pad 52 can be processed on the surface of the substrate layer 2 opposite to the chip 1 (e.g., the top surface of the substrate layer 2) using processes such as electroplating, chemical plating, and screen printing, so that the second pad 52 protrudes from the top surface of the substrate layer 2. Then, an ACF adhesive layer 3 is attached to the surface of the second pad 52, or the ACF adhesive layer 3 is attached to the surface of the chip 1 opposite to the substrate layer 2 (e.g., the bottom surface of the chip 1), so that the ACF adhesive layer 3 is disposed between the second pad 52 and the chip 1, and the projection of the second pad 52 onto the chip 1 along the first direction at least partially overlaps with the projection of the ACF adhesive layer 3 onto the chip 1 along the first direction, so as to ensure that during the subsequent hot pressing operation, the second pad 52 can break through the ACF adhesive layer 3 that at least partially overlaps with its projection onto the chip 1 along the first direction. Finally, a hot pressing operation is performed on the chip 1 and the substrate layer 2 so that the chip 1 and the substrate layer 2 are electrically connected through the conductive particles in the ACF adhesive layer 3 and the second pad 52, thereby achieving directional conductivity between the chip 1 and the substrate layer 2. In this example, the second pad 52 is processed only on the substrate layer 2, instead of the first pad 51 on the chip 1, which reduces the processing steps and saves processing costs.

[0133] As an example, a first pad 51 can be processed on the surface opposite to the substrate layer 2 (e.g., the bottom surface of the chip 1) using processes such as electroplating, chemical plating, and screen printing, and a second pad 52 can be processed on the surface opposite to the chip 1 on the substrate layer 2 using processes such as electroplating, chemical plating, and screen printing, respectively. Then, an ACF adhesive layer 3 is attached to the surface of the first pad 51 or the surface of the second pad 52, such that the ACF adhesive layer 3 is disposed between the first pad 51 and the second pad 52, and the projections of the first pad 51 and the second pad 52 onto the substrate layer 2 along a first direction at least partially overlap, so that during subsequent hot pressing operations, the first pad 51 and the second pad 52 can break through the ACF adhesive layer 3 that at least partially overlaps with their projections onto the substrate layer 2 along a first direction. Then, a hot pressing operation is performed on the chip 1 and the substrate layer 2 to make the chip 1 and the substrate layer 2 electrically connected through the ACF adhesive layer 3, thereby achieving directional conductivity between the chip 1 and the substrate layer 2. In this example, chip 1 is provided with a first pad 51, and substrate layer 2 is provided with a second pad 52. The first pad 51 and the second pad 52 are arranged opposite to each other, and their projections on substrate layer 2 along the first direction at least partially overlap, which helps to ensure the conductivity of ACF adhesive layer 3 after hot pressing.

[0134] In one embodiment, processing a first pad 51 on the surface of chip 1 opposite to the substrate layer 2 includes:

[0135] A first pad 51 is processed on one surface of the wafer and the substrate layer 2, the wafer is thinned to the target thickness, and the wafer is cut to obtain a chip 1 with the first pad 51.

[0136] As an example, processing a first pad 51 on the surface of chip 1 opposite to the substrate layer 2 specifically includes:

[0137] Step 1: Process a first pad 51 on one surface of the wafer. Specifically, the process may be, but is not limited to, Fab process, silkscreen process, mounting process, or metal ball implantation process. Process the first pad 51 on the bottom surface of the wafer. The first pad 51 may be made of copper, gold, silver, aluminum, or other conductive materials. The thickness of the first pad 51 is 1um to 100um, and the area of ​​the first pad 51 is 100um² to 30000um². This is to meet the requirements of pressing the ACF adhesive layer 3 and contacting the conductive particles in the ACF adhesive layer 3, and to meet the production design requirements of the chip level 1 packaging process.

[0138] Step 2: Thin the wafer to the target thickness of 50um to 800um.

[0139] Step 3: Divide the wafer to obtain a single chip 1 with a thickness of 50um to 800um and a first pad 51. The dicing process can be, but is not limited to, UV hard film dicing, laser dicing, knife dicing and etching dicing.

[0140] In this example, the order of steps one and two above can be changed depending on the actual situation.

[0141] In one embodiment, the substrate layer 2 includes a fab substrate layer, which includes an ink region 21;

[0142] Processing a second pad 52 on the surface of the substrate layer 2 opposite to the chip 1 includes:

[0143] An exposure windowing operation is performed in the ink region 21 of the amorphous substrate layer to obtain the windowed region 23 of the amorphous substrate layer, and the second pad 52 is processed in the windowed region 23.

[0144] As an example, a second pad 52 is processed on the surface of the substrate layer 2 opposite to the chip 1, specifically including:

[0145] Step 1: Perform an exposure windowing operation on the ink area 21 of the amorphous substrate layer. For example, an exposure windowing operation can be performed on the area of ​​the amorphous substrate layer opposite to the chip 1 using an exposure process, but not limited to, to form an opening area 23 opposite to the chip 1; or, an exposure windowing operation can be performed on the area of ​​the amorphous substrate layer opposite to the first pad 51 using an exposure process, but not limited to, to form an opening area 23 opposite to the first pad 51.

[0146] Step 2: Process the second pad 52 within the window area 23. This allows for fewer layer stacking processes in the chip 1 packaging process, helping to save packaging costs. In this example, the second pad 52 is processed in the window area 23 using, but not limited to, fab process, screen printing process, mounting process, or metal ball implantation process. The second pad 52 can be made of copper, gold, silver, aluminum, or other conductive materials. The thickness of the second pad 52 is 1µm to 100µm, and the area of ​​the second pad 52 is 100µm² to 30000µm². This satisfies the requirement of pressing into the ACF adhesive layer 3 and contacting the conductive particles in the ACF adhesive layer 3, and meets the production design requirements of the chip level 1 packaging process.

[0147] In one embodiment, pad bumps 5 are processed on the surface of at least one of the chip 1 and the substrate layer 2, including:

[0148] Using Fab process, screen printing process, bonding process or metal ball implantation process, pad protrusions 5 are processed on the surface of at least one of chip 1 and substrate layer 2.

[0149] As an example, pad protrusions 5 can be processed on the surface of at least one of chip 1 and substrate layer 2 using, but not limited to, fab processes, screen printing processes, mounting processes, or metal ball implantation processes. Specifically, a first pad 51 can be processed on the bottom surface of chip 1 using, but not limited to, fab processes, screen printing processes, mounting processes, or metal ball implantation processes, so that the first pad 51 is electrically connected to chip 1; and / or, a second pad 52 can be processed on the top surface of substrate layer 2 using, but not limited to, fab processes, screen printing processes, mounting processes, or metal ball implantation processes, so that the second pad 52 is electrically connected to the circuitry within substrate layer 2. The first pad 51 and the second pad 52 here can be any conductor material, for example, copper, gold, silver, aluminum, or other materials.

[0150] In one embodiment, a sealing structure 4 for sealing the ACF adhesive layer 3 is processed on the surface of the substrate layer 2, including:

[0151] The chip 1 is encapsulated using a molding process, and the side of the ACF adhesive layer 3 and the surface of the substrate layer 2 opposite to the chip 1 are sealed to form a molding structure 41.

[0152] Alternatively, a dispensing process can be used to seal and connect the side of chip 1, the side of ACF adhesive layer 3, and the surface of substrate layer 2 opposite to chip 1, forming a dispensing structure 42.

[0153] Alternatively, the sealing cap 43 can be sealed to the substrate layer 2, and the sealing cap 43 and the substrate layer 2 can cooperate to form a sealed space, with the chip 1 and the ACF adhesive layer 3 disposed within the sealed space.

[0154] As an example, after chip 1 and substrate layer 2 are pressed together into a single structure using ACF adhesive layer 3, a molding process can be used to encapsulate chip 1, the sides of ACF adhesive layer 3, and the side of substrate layer 2 closest to chip 1 to form a molding structure 41. This prevents moisture from entering the ACF adhesive layer 3 through the molding structure 41, thus ensuring the conductivity of the ACF adhesive layer 3. Specifically, encapsulating chip 1 here means encapsulating the top surface and sides of chip 1. For example, when using CoW packaging technology to encapsulate chip 1 and substrate layer 2, a molding structure 41 can be used to encapsulate chip 1 (including the top and sides), ACF adhesive layer 3, and the top surface of substrate layer 2. In this example, the molding structure 41 completely encapsulates chip 1 and ACF adhesive layer 3, achieving full sealing protection for both chip 1 and ACF adhesive layer 3, with good sealing performance.

[0155] As another example, after chip 1 and substrate layer 2 are pressed together into a single structure using ACF adhesive layer 3, a dispensing process can be used to apply adhesive to the sides of chip 1, the sides of ACF adhesive layer 3, and the top surface of substrate layer 2. This creates a dispensing structure 42 that seals the sides of chip 1, ACF adhesive layer 3, and the top surface of substrate layer 2. The dispensing structure 42 surrounds the ACF adhesive layer 3, sealing its periphery and preventing moisture from entering the ACF adhesive layer 3, thus ensuring the conductivity of the ACF adhesive layer 3. For example, when using CoG or CoF packaging processes to encapsulate chip 1 and substrate layer 2, the dispensing structure 42 can be used to encapsulate the sides of chip 1 and the top surface of substrate layer 2. In this example, the dispensing structure 42 seals the sides of chip 1 and ACF adhesive layer 3, providing a certain sealing effect at a lower processing cost.

[0156] As another example, after chip 1 and substrate layer 2 are pressed together into a single structure using ACF adhesive layer 3, sealing cap 43 can be sealed to the top surface of substrate layer 2 to form a sealed space. Chip 1 and ACF adhesive layer 3 are located within this sealed space, preventing moisture from entering the ACF adhesive layer 3 through dispensing structure 42, thus ensuring the conductivity of ACF adhesive layer 3. In this example, sealing cap 43 completely surrounds chip 1 and ACF adhesive layer 3, ensuring their sealing performance.

[0157] In one embodiment, the method for manufacturing the chip packaging structure further includes: processing solder balls 6 on the surface of the substrate layer 2 away from the ACF adhesive layer 3 using a metal ball implantation process, electroplating process, printing process, screen printing process or chemical plating process.

[0158] Furthermore, after step S2, that is, after processing the sealing structure 4 for sealing the ACF adhesive layer 3 on the substrate layer 2, the manufacturing method of the chip package structure further includes: processing solder balls 6 on the bottom surface of the substrate layer 2. Specifically, the processing can be carried out by, but is not limited to, metal ball implantation process, electroplating process, printing process, screen printing process and chemical plating process, as long as the electrical connection and reliability requirements are met.

[0159] The following example illustrates the manufacturing method of a chip package structure, which includes the following steps:

[0160] Step 1, as follows Figure 6 As shown in (A), a first pad 51 is processed on the surface of wafer 1. In this example, the first pad 51 can be processed on the surface of wafer 1 such that the thickness of the first pad 51 protruding from the wafer surface is 1um-100um, and the area of ​​each first pad 51 is 100um²-30000um². This process can be performed before the wafer leaves the factory or after the wafer leaves the factory. Specifically, it can be processed by electroplating, chemical plating, screen printing, etc., and the material can be any conductor.

[0161] Step two, as Figure 6 As shown in (B), it will be as follows Figure 6 (A) The wafer 1 shown is thinned to the target thickness and then diced to obtain multiple chips 1 with first pads 51. Typically, the target thickness of chip 1 is between 50um and 800um. The wafer with the first pads 51 can be diced into multiple individual chips 1. For example, but not limited to, UV hard film cutting, laser cutting, blade cutting, and etching cutting can be used. In this example, the order of processing the first pads 51 and the wafer thinning operation can be maintained or interchanged according to the process requirements of the packaging plant.

[0162] Step 3: As Figure 6 As shown in (C), the ACF adhesive layer 3 is pre-pressed onto the surface of the diced chip 1. In this example, the ACF adhesive layer 3 can be pre-pressed before wafer dicing. In other embodiments, the ACF adhesive layer 3 can also be pressed onto the surface of the substrate layer 2, depending on the process sequence requirements. The thickness of the ACF adhesive layer 3 is typically between 3µm and 30µm, and the diameter of the conductive particles within the ACF adhesive layer 3 is between 1µm and 50µm. Here, an ACF adhesive layer 3 that can withstand high and low temperatures is selected, specifically, the thermal cycling test temperature range of the ACF adhesive layer 3 is -65℃ to 150℃, and the high-temperature operating temperature is between 100℃ and 400℃. In this example, the ACF adhesive layer 3 pre-pressed in the pressure head area will adhere to the surface of the first pad 51, while the non-pressure head area will be removed by the release film.

[0163] Step Four: As Figure 6 As shown in (D), an exposure windowing operation is performed in the ink region 21 of the amorphous substrate layer to define a window region 23 within the amorphous substrate layer, and a second pad 52 is defined within the window region 23. Understandably, if there is sufficient design space, the exposure windowing operation may not be performed, and the top surface of the substrate layer 2 may be a recessed surface, a flat surface, or a raised surface, which can be determined according to the specific situation.

[0164] Step 5: As Figure 6 As shown in (E), when cutting the wafer using UV hard film in step two above, it is also necessary to perform a UV removal operation on the chip 1 with the pre-pressed ACF adhesive layer 3 so that the chip 1 with the pre-pressed ACF adhesive layer 3 can be removed from the UV cutting hard film; then, the chip 1 with the ACF adhesive layer 3 is hot-pressed onto the substrate layer 2 at a specified position, specifically hot-pressed onto the area where the first pad 51 and the second pad 52 overlap along the first direction.

[0165] Step Six: As Figure 6As shown in (F), the sealing structure 4 is processed using, but not limited to, molding or dispensing processes. Materials such as epoxy, polyimide, and fiber systems are processed to form the molding structure 41. An external cap can also be used. For COF or COG type encapsulations, no molding material is required. Finally, using processes such as metal ball implantation, electroplating, printing, screen printing, or chemical plating, solder balls 6 are processed on the surface of the substrate layer 2 away from the ACF adhesive layer 3. Figure 6 As shown in (F).

[0166] Step 7: Cut multiple individual chips into individual chips, package and ship them, and the packaging process is complete.

[0167] This invention provides an electronic device, including the aforementioned chip packaging structure. The electronic device is an electronic device with a display screen, and can be a laptop, mobile phone, tablet computer, desktop computer, gaming device, in-vehicle electronic device, wearable smart device, etc.

[0168] The above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model, and should all be included within the protection scope of this utility model.

Claims

1. A chip packaging structure, characterized in that, This includes the chip, substrate layer, ACF adhesive layer, and sealing structure; The ACF adhesive layer is disposed between the chip and the substrate layer, and the chip and the substrate layer are electrically connected through the ACF adhesive layer; The sealing structure is sealed to the substrate layer, and the sealing structure is also located on the periphery of the ACF adhesive layer for sealing the ACF adhesive layer.

2. The chip packaging structure according to claim 1, characterized in that, At least one of the chip and the substrate layer is provided with pad protrusions; The chip and the substrate layer are electrically connected through the pad protrusions and the conductive particles within the ACF adhesive layer.

3. The chip packaging structure according to claim 2, characterized in that, The pad protrusion includes a first pad disposed on the surface of the chip opposite to the substrate layer. The ACF adhesive layer is disposed between the first pad and the substrate layer. The projection of the first pad onto the substrate layer along a first direction at least partially overlaps with the projection of the ACF adhesive layer onto the substrate layer along the first direction; or... The pad protrusion includes a second pad disposed on the surface of the substrate layer opposite to the chip. The ACF adhesive layer is disposed between the second pad and the chip. The projection of the second pad onto the chip along the first direction at least partially overlaps with the projection of the ACF adhesive layer onto the chip along the first direction; or... The pad protrusion includes a first pad and a second pad. The first pad is disposed on the surface of the chip opposite to the substrate layer, and the second pad is disposed on the surface of the substrate layer opposite to the chip. The ACF adhesive layer is disposed between the first pad and the second pad. The projections of the first pad and the second pad on the substrate layer along the first direction at least partially overlap, and the area of ​​the second pad is larger than the area of ​​the first pad. Wherein, the first direction is the direction perpendicular to the substrate layer.

4. The chip packaging structure according to claim 3, characterized in that, The surface of the substrate layer opposite to the first pad is a flat surface, a raised surface, or a recessed surface; And / or, the surface of the chip opposite to the second pad is a flat surface, a raised surface, or a recessed surface.

5. The chip packaging structure according to claim 3, characterized in that, Multiple first pads are arranged on the surface of the chip opposite to the substrate layer; Multiple second pads are arranged on the surface of the substrate layer opposite to the chip.

6. The chip packaging structure according to claim 3, characterized in that, The substrate layer includes a wafer substrate layer and a non-wafer substrate layer; The amorphous substrate layer includes any one of a glass substrate layer, a flexible film substrate layer, an epoxy-based material layer, a benzocyclobutane material layer, a polyimide substrate layer, and a fiber substrate layer.

7. The chip packaging structure according to claim 6, characterized in that, The amorphous substrate layer includes an ink region and a window region disposed within the ink region; The second pad is disposed within the window opening area; the ACF adhesive layer is attached to the window opening area; The area of ​​the windowed region is larger than the area of ​​the chip; The depth of the windowed area is 5um-100um.

8. The chip packaging structure according to claim 2, characterized in that, The thickness of the pad protrusion is 1µm to 100µm, and the area of ​​the pad protrusion is 100µm² to 30000µm².

9. The chip packaging structure according to any one of claims 1 to 8, characterized in that, The thickness of the chip is 50um to 800um; the thickness of the ACF adhesive layer is 3um to 30um; the diameter of the conductive particles is 1um to 50um; the ACF adhesive layer passes the electrical test within the temperature range of -65℃ to 150℃ for thermal cycling; and the high-temperature operating temperature of the ACF adhesive layer is not lower than 180℃.

10. The chip packaging structure according to any one of claims 1 to 8, characterized in that, The sealing structure includes a molding compound that encapsulates the chip, the molding compound is sealed to the side of the ACF adhesive layer, and the molding compound is sealed to the side of the substrate layer closest to the chip. Alternatively, the sealing structure includes a dispensing structure that is sealed to the side of the chip, sealed to the side of the ACF adhesive layer, and sealed to the side of the substrate layer closest to the chip. Alternatively, the sealing structure includes a sealing cap that is sealed to the substrate layer, the sealing cap and the substrate layer cooperating to form a sealed space, and the chip and the ACF adhesive layer are disposed within the sealed space.

11. The chip packaging structure according to any one of claims 1 to 8, characterized in that, The sealing structure is an epoxy sealing structure, a polyimide sealing structure, or a fiber sealing structure.

12. The chip packaging structure according to any one of claims 1 to 8, characterized in that, The chip packaging structure also includes solder balls disposed on the surface of the substrate layer away from the ACF adhesive layer.

13. An electronic device, characterized in that, Includes the chip packaging structure described in any one of claims 1-12.

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