Low-stress packaging structure
By using a flip-chip packaging structure that bridges silicon wafers or large chips as carriers, the performance degradation problem caused by thermal stress during MEMS chip packaging is solved, achieving high-performance and reliable packaging of MEMS sensors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-20
- Publication Date
- 2026-03-24
AI Technical Summary
In existing MEMS chip packaging, the thermal mismatch between the adhesive and the substrate material leads to stress sensitivity, which affects chip performance, especially for sensors such as accelerometers.
A low-stress packaging structure is adopted, using a bridging silicon wafer or a chip with a larger width as a suspension carrier to bond the MEMS chip in a flip-chip manner. The bottom of the MEMS chip does not contact the substrate with adhesive. The bridging silicon wafer or large chip is used as a carrier to isolate thermal stress, thus realizing flip-chip packaging.
It effectively isolates the thermal stress deformation of the substrate, improves the performance and reliability of MEMS sensors, and reduces the impact of stress on chip performance.
Smart Images
Figure CN224030654U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a kind of MEMS chip packaging technology, especially a kind of MEMS chip packaging structure for reducing the stress influence of adhesive. BACKGROUND
[0002] MEMS chip refers to micro-electro-mechanical system (Micro-Electro-Mechanical Systems) chip, also known as micro-electro-mechanical system integrated circuit. It manufactures small mechanical components on the chip surface through micro-nano manufacturing technology, and is connected with circuit elements. These small mechanical structures can realize sensing, measurement, control and execution functions. MEMS has been widely used in various sensor chips in automotive electronics, aerospace and other fields, and its core function is to convert physical signals into electrical signals that can be recognized by electronic devices. Because MEMS chip has the advantages of small size, light weight, low energy consumption, high performance and so on, they have a wide range of applications in mobile devices, automotive field, medical devices, industrial control, consumer electronics, environmental monitoring and other fields.
[0003] At present, most of the dispensing schemes in application packaging are to make the bottom of MEMS chip around overflow. Although increasing the bonding area can effectively improve the bonding strength of the chip, but due to the thermal mismatch between the adhesive, the chip and the substrate material, stress will be generated, which will cause the performance loss of stress-sensitive MEMS chip (especially accelerometer and other sensors). SUMMARY
[0004] The purpose of the utility model is to provide a low-stress packaging structure, aiming at optimizing the problem of stress-sensitive MEMS chip.
[0005] The technical solution of the utility model to achieve the above-mentioned purpose is a low-stress packaging structure, which installs two or more chips on the substrate, at least one of which is a stress-sensitive MEMS chip. Its characteristics are that the MEMS chip and the remaining chips to be packaged are pre-bonded into one, and one of the remaining chips is glued to the substrate. The bottom of the MEMS chip is set as non-glue distribution, and is opposite to the substrate in space.
[0006] Further, two chips and a bridge silicon wafer are involved in packaging. The width of the bridge silicon wafer is greater than the sum of the MEMS chip and the other chip. The top of the MEMS chip is set as glue distribution, and the top and bottom of the other chip are set as glue distribution. The two chips are bonded to the bottom surface of the bridge silicon wafer and are separated from each other, and the other chip is bonded to the substrate.
[0007] Further, three chips are involved in the packaging, and one of the chips has a width greater than the sum of the MEMS chip and another chip, the top of the MEMS chip is provided with glue, the top and bottom of the other chip are provided with glue, the MEMS chip and the other chip are bonded to the bottom of the chip with a greater width and are separated from each other, and the other chip is bonded to the substrate.
[0008] Further, the height of the other chip is less than the height of the MEMS chip and is close to the height of the MEMS chip, and the bottom of the other chip is provided with thickened glue.
[0009] Further, the height of the other chip is less than the height of the MEMS chip and is close to the height of the MEMS chip, and the bottom of the other chip is provided with thickened glue.
[0010] The packaging structure of the utility model has the following technical effects: the MEMS chip is bonded in a flip-chip manner by using a bridge silicon wafer or a chip with a greater width as a suspension carrier, the MEMS chip is not in contact with the substrate and is not provided with glue in the state of completing the chip packaging, and thus the thermal stress deformation of the substrate is effectively isolated, and the performance of the MEMS sensor is improved. BRIEF DESCRIPTION OF DRAWINGS
[0011] Figure 1 is a structural schematic view of a preferred embodiment of the low-stress packaging structure of the utility model.
[0012] Figure 2 is a structural schematic view of a preferred embodiment of the low-stress packaging structure of the utility model.
[0013] Figure 3 is a structural schematic view of another preferred embodiment of the low-stress packaging structure of the utility model. DETAILED DESCRIPTION
[0014] The specific embodiments of the utility model will be further described in detail below in combination with the accompanying drawings, so that the technical scheme of the utility model is easier to understand and grasp, and the protection scope of the utility model is more clearly defined.
[0015] In view of the fact that the thermal expansion coefficients of different components in the traditional packaging structure are greatly different, in order to avoid the influence of the deformation caused by stress on the performance of the MEMS chip, the packaging structure of the chip is improved, and the chip performance is improved while the stress sensitivity of the MEMS chip is optimized and the reliability of the packaged product is maintained.
[0016] The above packaging structure is mainly used for mounting two or more chips on a substrate, and at least one of the chips is a stress-sensitive MEMS chip. The summarized structure optimization feature is that the MEMS chip is pre-bonded with the remaining chips to be packaged into one body, and is glued to the substrate by one of the remaining chips. On this basis, the bottom of the MEMS chip does not need to be provided with glue, and is spaced apart from the substrate.
[0017] As shown in the preferred embodiment, Figure 1 Two chips and a bridge silicon wafer 3 are involved in packaging, the width of the bridge silicon wafer 3 is greater than the sum of the MEMS chip 22 and the other chip 21. When packaging, the top of the MEMS chip 22 is provided with glue, the top and bottom of the other chip 21 are provided with glue, and the two chips are bonded to the bottom surface of the bridge silicon wafer 3 and spaced apart from each other, and are bonded to the substrate 1 by the other chip 21. It can be seen that the bottom of the MEMS chip does not have adhesive 4 and is spaced apart from the substrate 1, so that the stress transmission channel between the two is cut off, and the MEMS chip can maximize its design performance.
[0018] As shown in the preferred embodiment, Figure 2 Three chips are involved in packaging, and one of the chips 23 has a width greater than the sum of the MEMS chip 22 and the other chip 21. When packaging, the top of the MEMS chip 22 is provided with glue, the top and bottom of the other chip 21 are provided with glue, and then the MEMS chip 22 and the other chip 21 are bonded to the bottom surface of the chip 23 with a larger width and spaced apart from each other, and finally the other chip 21 is bonded to the substrate 1, realizing the integrated packaging of the three chips on the substrate, which can also improve the stress sensitivity of the MEMS chip.
[0019] Of course, there are differences in the thickness of different chips involved in packaging, which may cause the above-mentioned optimized structure to fail. Therefore, as shown in Figure 2 When the height (i.e. the thickness itself) of the other chip 21 is less than and close to the height of the MEMS chip 22, the bottom of the other chip 21 can be provided with thickened glue, so that the total height satisfies the suspended state of the MEMS chip. But when the height of the other chip 21 is less than the height of the MEMS chip and the gap cannot be cut off the stress transmission channel by thickening the glue. Then as shown in another preferred embodiment, Figure 3 The bottom of the other chip 21 is supported by a pad 5 (preferably a silicon wafer) and bonded to the substrate.
[0020] From the above, the scheme introduction and the embodiment details of the low stress packaging structure of the utility model can be seen, it has substantial characteristics and progress, and its technical effect is shown as follows: through using a bridge silicon wafer or a chip with a larger width as a suspension carrier, the MEMS chip is bonded in a flip-chip manner, and there is no contact and glue distribution between the MEMS chip and the substrate in the chip packaging state, so that the thermal stress deformation of the substrate is effectively isolated, and the performance of the MEMS sensor is improved.
[0021] In addition to the above embodiments, the utility model can also have other implementation manners, and any technical scheme formed by equivalent replacement or equivalent transformation falls within the scope of the utility model claimed.
Claims
1. A low-stress packaging structure for mounting two or more chips on a substrate, wherein at least one chip is a stress-sensitive MEMS chip, characterized in that: The MEMS chip is pre-bonded integrally with the rest of the chips to be packaged, and is glued to the substrate by one of the rest of the chips, the bottom of the MEMS chip is arranged without glue, and is opposite the substrate in space.
2. The low stress packaging structure of claim 1, wherein: Two chips and a bridge silicon chip are involved in the packaging, the width of the bridge silicon chip is greater than the sum of the MEMS chip and the other chip, the top of the MEMS chip is arranged with glue, the top and bottom of the other chip are arranged with glue, the two chips are bonded to the bottom of the bridge silicon chip and are separated from each other, and the other chip is bonded to the substrate.
3. The low stress packaging structure of claim 1, wherein: Three chips are involved in the packaging, and the width of one of the chips is greater than the sum of the MEMS chip and the other chip, the top of the MEMS chip is arranged with glue, the top and bottom of the other chip are arranged with glue, the MEMS chip and the other chip are bonded to the bottom of the chip with a greater width and are separated from each other, and the other chip is bonded to the substrate.
4. A low stress packaging structure according to claim 2 or 3, wherein: The height of the other chip is less than and close to the height of the MEMS chip, and the bottom of the other chip is arranged with thickened glue.
5. The low stress packaging structure of claim 2 or 3, wherein: The height of the other chip is less than the height of the MEMS chip and the difference exceeds the allowable thickening amount of the glue, the bottom of the other chip is supported by a pad and is bonded to the substrate. The height of the other chip is less than the height of the MEMS chip and the difference exceeds the allowable thickening amount of the glue, the bottom of the other chip is supported by a pad and is bonded to the substrate.