Memory and electronic equipment

Abstract

The utility model relates to a memory and electronic equipment, the memory comprises a memory chip and a logic chip, the memory chip and the logic chip are packaged by adopting a three-dimensional stacking process, the memory has a memory mode and a calculation mode, and the memory is configured as follows: in the memory mode, the logic chip is connected with the memory chip; realizing information interaction of the storage chip through a first information interaction path; and in the calculation mode, realizing information interaction of the storage chip through a second information interaction path. According to the application, two information interaction channels are set, and the first information interaction channel enables information interaction to be more efficient; the second information interaction path provides higher data bandwidth for the logic chip; therefore, the memory provided by the utility model has the two advantages, one interaction path can be flexibly selected according to requirements, and the application scene of the memory is enriched.

Description

Technical Field

[0001] This utility model relates to the field of chip technology, specifically to a memory and electronic device. Background Technology

[0002] like Figure 1 As shown, when a traditional two-dimensional memory communicates with an external system, it typically performs corresponding functions based on commands or data sent to the memory by an external controller. The interface circuit of a traditional two-dimensional memory receives these commands or data and transmits them to the memory control logic circuit. The control logic further parses these commands into operation instructions for the memory control circuit and, through a control path, controls the relevant circuits to execute the instruction operations, thus realizing the system communication function. Data is then stored in or read from the memory according to these instructions. Therefore, in traditional solutions, within the memory chip, there is only one control path and one data path for communication between the memory circuit and the external memory. This control path and data path typically pass through the memory's internal interface circuit, data buffer circuit, and control logic circuit before finally reaching the memory circuit.

[0003] As the "memory wall" bottleneck in memory becomes increasingly severe, 3D memory implemented through advanced packaging technology is gradually becoming the mainstream solution for improving memory performance metrics such as data bandwidth in the "post-Moore's Law era." This architecture can package multiple memory chips and logic chips together and achieve electrical connections between these chips through advanced packaging. However, the interface circuitry of this type of memory is typically designed on the logic chip, resulting in the memory circuitry within the memory chip needing to navigate long control and data paths to complete communication tasks with the outside world. This control and data path architecture has become a serious bottleneck for further improving the performance of this type of memory.

[0004] like Figure 2 As shown, HBM is a three-dimensional stacked memory based on TSV technology, typically composed of multiple DRAM memory chips and logic chips stacked together. Its memory interface circuitry is located on the bottommost logic chip. Between different chips, control and data paths form the vertical I / O constructed using TSV technology. Within the logic chip, control paths are designed between interface circuits, control logic, memory chip controllers, and data buffers, while data paths primarily exist between interface circuits, data buffers, and other circuits. Within the memory chip, control paths mainly exist between control circuits and memory circuits, while data paths primarily consist of data input or output channels.

[0005] Although 3D memory such as HBM has overcome the performance bottleneck of traditional 2D memory chips to some extent through advanced packaging technology, the control and data paths of such memory chips are not fundamentally different from those of traditional 2D memory chips. In particular, the path from the interface circuit to the memory circuit in the memory chip is even more complex than that of traditional 2D memory chips. Data needs to be transmitted for a long time to reach the interface circuit. It can be said that such a path architecture seriously affects memory access efficiency.

[0006] Therefore, it is necessary to improve the existing memory. Utility Model Content

[0007] To address the above problems, this utility model provides a memory, including a memory chip and a logic chip. The memory chip and the logic chip are packaged using a three-dimensional stacking process. The memory has a storage mode and a computing mode, and is configured to: in the storage mode, realize information interaction of the memory chip through a first information interaction path; and in the computing mode, realize information interaction of the memory chip through a second information interaction path.

[0008] The memory provided in this application, based on different operating modes of the memory and combined with the data transmission requirements and characteristics of each operating mode, adaptively matches the information interaction path that meets the requirements and characteristics. It can flexibly select one of the more efficient information interaction paths to perform the operation according to the operation that the memory needs to perform. Compared with a memory that can only be implemented through one path for all operations, it improves the overall performance of the memory and enriches its application scenarios.

[0009] Optionally, the memory further includes an interface circuit configured for information interaction between the memory and an external source. The first information interaction path is located between the interface circuit and the memory chip, and the second information interaction path is located between the functional circuit of the logic chip and the memory chip.

[0010] Optionally, the functional circuit includes circuits for implementing any or a combination of functions such as error correction, multiplication, division, addition and subtraction, buffering, control, protection, drive, load, connection and interface functions.

[0011] The functional circuit may also include any and a combination of basic logic circuits (e.g., AND gate, OR gate, NOT gate, XOR gate, etc.), storage circuits (e.g., flip-flops, registers), timing control circuits (e.g., clocks, counters, timers), and data processing circuits (encoders, decoders, multiplexers, etc.).

[0012] The memory provided in this application has two information interaction paths. The first information interaction path can directly realize the control and data transmission of the memory chip based on external instructions through the interface circuit, making the information interaction more efficient. The second information interaction path, by utilizing the I / O interface between three-dimensional stacked chips implemented by advanced packaging, significantly improves the resource utilization of the memory chip and provides higher data bandwidth for the logic chip. Therefore, the memory provided in this application can take into account both of the above advantages.

[0013] Optionally, the memory is further provided with a control circuit, which is connected to the first information interaction path and the second information interaction path. The control circuit can arbitrate based on the instruction type for accessing the memory, and based on the arbitration result, selectively allow the memory to realize information interaction between the external device and the memory chip through the first information interaction path or the second information interaction path.

[0014] The memory provided in this application, through the setting of the control circuit, can, on the one hand, coordinate the transmission of information through the instruction interaction path according to preset rules, thereby avoiding errors and conflicts; on the other hand, the preset rules can be combined with the application scenario, so that the memory can always interact with information through the interaction path adapted to the current application scenario, thus taking into account both efficiency and bandwidth.

[0015] Optionally, the "control circuit is capable of arbitrating based on the instruction type for accessing the memory" includes:

[0016] If the instruction type for accessing the memory is a memory access-related instruction, it is determined that information interaction between the external system and the memory chip will be achieved through the first information interaction path; and

[0017] If the instruction type for accessing the memory is a computation-related instruction, it is determined that information interaction between the external system and the memory chip will be achieved through the second information interaction path.

[0018] Optionally, the first information interaction path includes a first data path and a first control path, and the second information interaction path includes a second data path and a second control path. The first data path and the second data path are used for data information transmission, and the first control path and the second control path are used for control information transmission. The control circuit is disposed in the memory chip, and the memory chip further includes:

[0019] Storage circuitry, used to implement storage functions, includes multiple memory groups;

[0020] Multiple data selection circuits are configured corresponding to the multiple memory groups, including a control terminal, a data interaction terminal, a first data path terminal, and a second data path terminal. The control terminal is connected to the control circuit, the data interaction terminal is connected to the multiple memory groups, and the first data path terminal and the second data path terminal are respectively connected to the first data path and the second data path. The data selection circuit can selectively connect the data interaction terminal to the first data path terminal or the second data path terminal based on the signal from the control terminal.

[0021] Optionally, the interface circuit is disposed in the logic chip.

[0022] Optionally, the interface circuit is disposed on the memory chip.

[0023] Optionally, the memory chip is provided with a first interface for information interaction with the logic chip for each memory group. Correspondingly, the logic chip is provided with a second interface in the stacking direction with the memory chip, corresponding to the position of the first interface. The first interface and the second interface are connected to form part of the second data path.

[0024] This configuration can further increase the bandwidth of the second data path.

[0025] Optionally, the first interface and the second interface are electrically connected using TSV, hybrid bonding, or hybrid bonding technology.

[0026] To achieve the aforementioned objectives, this application provides a method for controlling a memory, applied to control the memory described above, comprising the following steps:

[0027] Determine the operating mode of the memory; and

[0028] Based on the operating mode, an information interaction path matching the operating mode is selected to realize information interaction of the memory chip.

[0029] Optionally, the control method for the memory further includes:

[0030] Data consistency detection step: In response to changes / switches in the information interaction path, detect the correctness of the data stored in the memory chip.

[0031] Based on the memory control method provided in this application, the correctness of the data stored in the memory chip is ensured by data consistency detection when receiving data transmitted in different paths, thus avoiding errors.

[0032] Optionally, the control method for the memory further includes:

[0033] At any given time, only one information exchange channel is accessible.

[0034] The above method not only enables the matching of data / instructions and paths, but also ensures that only one information exchange path can enter the working state at any given time, while the other information exchange path enters the inaccessible state, thereby avoiding conflicts.

[0035] In order to achieve the above-mentioned utility model objectives, this application provides an electronic device that uses the memory described above. Attached Figure Description

[0036] Figure 1 It is the architecture of memory in existing technology.

[0037] Figure 2 It is a memory architecture packaged using a three-dimensional stacking process in existing technologies.

[0038] Figure 3 This is a schematic diagram of the memory architecture provided in an embodiment of this utility model.

[0039] Figure 4 This is a schematic diagram of the memory architecture provided in an embodiment of this utility model.

[0040] Figure 5 This is a schematic diagram of the memory architecture provided in an embodiment of this utility model.

[0041] Figure 6 This is a schematic diagram of the steps of the memory control method provided in the embodiments of this utility model. Detailed Implementation

[0042] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0043] like Figure 3 As shown, this embodiment provides a memory, including a memory chip 100 and a logic chip 200. The memory chip 100 and the logic chip 200 are packaged using a three-dimensional stacked packaging process. The memory has a storage mode and a computing mode, and is configured to: in the storage mode, realize information interaction of the memory chip 100 through a first information interaction path; and in the computing mode, realize information interaction of the memory chip 100 through a second information interaction path.

[0044] Optionally, the memory also includes an interface circuit 300, which is configured to allow the memory to interact with external systems. A first information interaction path is provided between the interface circuit 300 and the memory chip 100, and a second information interaction path is provided between the functional circuit 250 of the logic chip 200 and the memory chip 100.

[0045] In other words, the memory is configured with a first information interaction path that directly interacts with the memory chip 100 via the interface circuit 300, and a second information interaction path that interacts with the memory chip 100 via the functional circuit 250 of the logic chip 200.

[0046] The functional circuit 250 includes any and a combination of basic logic circuits (such as AND gate, OR gate, NOT gate, XOR gate, etc.), storage circuits (such as flip-flops, registers), timing control circuits (such as clocks, counters, timers), and data processing circuits (encoders, decoders, multiplexers, etc.); the functional circuit 250 also includes, but is not limited to, circuits for implementing error correction functions, multiplication, division, addition and subtraction calculation functions, buffering functions, control functions, protection functions, driving functions, load functions, connection functions, and interface functions.

[0047] In this embodiment, two information interaction paths are provided. The first information interaction path can directly control the memory chip 100 based on external instructions through the interface circuit 300, making information interaction more efficient. The second information interaction path utilizes the I / O interface between three-dimensional stacked chips implemented with advanced packaging, which significantly improves the resource utilization of the memory chip 100 and provides higher data bandwidth for the logic chip 200. Therefore, the memory provided in this embodiment can take into account both advantages. It can flexibly select one of the more efficient information interaction paths to perform the operation according to the operation that the memory needs to perform. Compared with a memory that can only perform all operations through one path, this improves the overall performance of the memory and enriches its application scenarios.

[0048] Optionally, the memory also includes a control circuit 400, which is connected to a first information interaction path and a second information interaction path. The memory chip 100 is configured to selectively interact with the outside of the memory through the first information interaction path, or with the logic chip 200 through the second information interaction path, based on the arbitration result of the control circuit 400. In this embodiment, by setting up the control circuit 400, on the one hand, information can be coordinated to be transmitted through a designated interaction path according to preset rules, avoiding errors and conflicts. On the other hand, the preset rules can be combined with the application scenario, enabling the memory to always interact with information through an interaction path adapted to the current application scenario. This allows different types of operation instructions to be selectively implemented through a more efficient information interaction path, balancing efficiency and bandwidth.

[0049] In other words, the control circuit 400 can arbitrate based on the type of instruction that accesses the memory, and based on the arbitration result, selectively allow the memory to realize information interaction between the external device and the memory chip 100 through the first information interaction path or the second information interaction path.

[0050] The memory provided in this embodiment, through the setting of the control circuit 400, can, on the one hand, coordinate the transmission of information through the instruction interaction path according to preset rules, thereby avoiding errors and conflicts. On the other hand, the preset rules can be combined with the application scenario, so that the memory can always interact with information through the interaction path adapted to the current application scenario, thus taking into account both efficiency and bandwidth.

[0051] Optionally, "the control circuit 400 is capable of arbitrating based on the instruction type for accessing memory" includes:

[0052] If the instruction type for accessing memory is a memory access-related instruction, it is determined that information exchange between the external device and the memory chip 100 will be achieved through the first information exchange path; and

[0053] If the instruction type for accessing the memory is a computation-related instruction, it is determined that information interaction between the external device and the memory chip 100 will be achieved through the second information interaction path.

[0054] More specifically, when performing traditional memory chip 100 access operations, information interaction can be achieved through the first information interaction path. Compared with the second information interaction path, the information transmission path is shortened. However, when performing operations such as data rearrangement and calculation, the second information interaction path has the advantage of bandwidth. Users can selectively transmit information based on the path that matches the information being interacted with, thereby improving the performance of the memory.

[0055] Since the types of information exchanged between the memory chip 100 and the logic chip 200, as well as between the two and the external system, mainly include control information and data information, in this embodiment, the first information exchange path includes a first data path (data path 1) for data exchange and a first control path (control path 1) for control instruction exchange, and the second information exchange path includes a second data path (data path 2) for data exchange and a second control path (control path 2) for control instruction exchange.

[0056] The control circuit 400 can be connected to the interface circuit 300 and the logic chip 200 through the first control path and the second control path respectively. Based on the control command, it can selectively enable the first data path or the second data path to interact with the memory chip 100.

[0057] The following is an exemplary description of the specific implementation scheme of the memory provided in this embodiment:

[0058] The control circuit 400 is disposed in the memory chip 100. In addition to the arbitration function mentioned above, it can also control the memory circuit 110 of the memory chip 100. The memory circuit 110 includes multiple memory groups 111. The memory chip 100 also includes multiple data selection circuits 120 corresponding to the memory groups 111. The data selection circuit 120 has a control terminal, a data interaction terminal, a first data path terminal and a second data path terminal. The control terminal is connected to the control circuit 400. More specifically, the control terminal is connected to the arbitrator 410 disposed inside the control circuit 400. The data interaction terminal is connected to each memory group 111. The first data path terminal and the second data path terminal are respectively connected to the first data path and the second data path.

[0059] Continue to refer to Figure 3Optionally, the interface circuit 300 is disposed in the logic chip 200. In addition to the functional circuit 250, the logic chip 200 also includes a control logic circuit 210, an interface data buffer circuit 220, a memory chip control circuit 230, and an internal data buffer circuit 240. This is used to buffer data transmitted via the first data path. The control logic circuit 210 is connected to the interface circuit 300 and can convert external instructions into operation instructions such as address, timing, and control mode for read / write operations. The memory chip control circuit 230 is connected to the control logic circuit 210, the internal data buffer circuit 240, the functional circuit 250, and the control circuit 400. It can control the memory chip 100 by driving the control circuit 400. The functional circuit 250 can perform functions including logic calculation and control. It is connected to the memory chip control circuit 230 and the internal data buffer circuit 240, and can schedule the data buffered in the internal data buffer circuit 240. Based on the calculation results and control tasks, it can control the operation of the memory chip 100 through the memory chip control circuit 230.

[0060] Figure 3 The specific working principle of the memory shown is as follows:

[0061] The memory includes a storage mode and a computing mode. In response to receiving a memory access-related instruction, the interface circuit 300 sends an instruction to the memory chip 100, causing the memory chip 100 to enter the storage mode. In the storage mode, the memory chip 100 receives the instruction from the interface circuit 300 through the first control path and writes data (which may contain instructions from the functional circuit 250) through the first data path. In response to receiving a computing-related instruction, the interface circuit 300 sends an instruction to the memory chip 100, causing the memory chip 100 to enter the computing mode. In the computing mode, the functional circuit 250 obtains instructions and data through the second data path and processes the data based on the instructions.

[0062] It should be noted that, based on the different types of control commands, the control arbitrator 410 sends an arbitration signal corresponding to the control command to the data selection circuit 120. Based on the arbitration signal, the data selection circuit 120 selects the path that matches the arbitration signal in the first data path and the second data path, and allows the path to interact with the memory group 111 via the data interaction terminal. This achieves accurate control of the data path selection. At any given time, only one path can enter the working state, while the other path enters the inaccessible state, thereby avoiding errors and conflicts.

[0063] Optionally, the first data path is formed by interface circuit 300 → interface data buffer circuit 220 → memory chip 100 (data selection circuit 120), and the first control path is formed by interface circuit 300 → control logic circuit 210 → memory chip control circuit 230 → memory chip 100 (control circuit 400); the second data path is formed by functional circuit 250 → internal data buffer circuit 240 → memory chip 100 (data selection circuit 120), and the second control path is formed by memory chip control circuit 230 → control circuit 400 / internal data buffer circuit 240 / functional circuit 250.

[0064] It should be noted that the "→" in the implementation method is only used to describe the information transmission path and does not constitute a limitation on the direction of information transmission. In other words, various information can be bidirectionally interacted / transmitted between corresponding modules based on needs or instructions.

[0065] Because the internal data buffer circuit 240 and the data selection circuit 120 use advanced IO technology with three-dimensional stacked packaging, higher bandwidth data transmission is achieved compared to the first data path. Specifically, the internal data buffer circuit 240 and the data selection circuit 120 can be electrically connected using TSV, hybrid bonding or hybrid bonding technology. In addition, since the information transmission path of the first data path is shorter, the information transmission efficiency can be improved.

[0066] Alternatively, in another embodiment of this application, such as Figure 4 As shown, it is similar to Figure 3 The difference between the memory shown is that the interface circuit 300 is located on the memory chip 100. In this case, the interface circuit 300 is directly connected to the control circuit 400 and the data selection circuit 120. The information interaction path is shorter, which can give full play to the advantages of efficient interaction. At the same time, there is no need to set up an interface data buffer circuit and interface circuit on the logic chip 200.

[0067] In this embodiment, the first data path is formed by interface circuit 300 → memory chip 100 (data selection circuit 120); the first control path is formed by interface circuit 300 → memory chip 100 (control circuit 400); the second data path is formed by interface circuit 300 → logic chip 200 (functional circuit 250 → data buffer circuit 240) → memory chip 100 (data selection circuit 120); the second control path is formed by interface circuit 300 → logic chip 200 (control logic circuit 210 → memory chip control circuit 230; functional circuit 250 → memory chip control circuit 230; data buffer circuit 240 → memory chip control circuit 230) → memory chip 100 (control circuit 400).

[0068] pass Figure 3 and Figure 4 The paths of each data path and control path corresponding to the illustrated memory architecture can be seen. The first information interaction path (first data path and first control path) has less path complexity, so the information interaction is more efficient. The second information interaction path has higher data bandwidth because its data transmission path is based on advanced packaging.

[0069] Furthermore, the advantages of placing the interface circuit 300 on the memory chip 100 include: the interface circuit is generally a SerDes (Serialization / Deserialization) circuit, a high-speed serial-to-parallel / parallel-to-serial data conversion interface circuit. Its implementation requires a complex design and testing process, including circuit design, circuit netlist simulation, layout design, parasitic parameter extraction and post-simulation, and chip return testing, to ensure functional correctness. This means that if the interface circuit is migrated from one process technology to another, the above process needs to be repeated, resulting in a huge and complex workload, and reliability cannot be guaranteed. The memory architecture provided in this embodiment places the interface circuit on the memory chip, eliminating the need for process migration from memory chip technology to logic chip technology. Therefore, it greatly reduces the design complexity and difficulty of three-dimensional stacked memory, and significantly improves the architecture iteration speed of such memory.

[0070] Optionally, such as Figure 5 As shown, in order to further increase the bandwidth advantage of the second information interaction path, the second information interaction path is designed as follows: the memory chip 100 is provided with a first interface 130 for data interaction with the logic chip 200 for each memory group 111. Correspondingly, the logic chip 200 is provided with a second interface 260 in the stacking direction with the memory chip 100, taking the two chips as a horizontal stack as an example, that is, in the vertical direction, corresponding to the position of the first interface 130. The second interface 260 is connected to the data buffer circuit 240 to form a partial second data path. In this way, the logic chip 200 can control multiple memory groups 110 in the memory chip 100 to perform operations simultaneously, significantly improving the resource utilization of the memory chip 100 and providing higher data bandwidth for the second information interaction path.

[0071] Furthermore, in this embodiment, different memory groups perform completely different, partially the same, or completely the same operations in response to corresponding control instructions.

[0072] With this configuration, the memory control method provided in this embodiment is more flexible than that in the prior art. It can make different memory groups execute different control instructions according to the needs, thereby improving the utilization rate of memory, data interaction efficiency and the diversity of working modes.

[0073] Optionally, this embodiment also provides a memory control method, applied to control the memory provided in this embodiment, such as... Figure 6 As shown, the steps include:

[0074] Determine the operating mode of the memory; and

[0075] Based on the operating mode, an information interaction path matching the operating mode is selected to realize information interaction of the memory chip 100.

[0076] Optionally, the memory control method further includes:

[0077] Data consistency detection steps: In response to changes / switches in the information exchange path, detect the correctness of the data stored in the memory chip 100.

[0078] Specifically, it also includes: when responding to external memory access-related instructions (such as read and write operations), determining to achieve information interaction through the first information interaction path; and when responding to computation-related instructions such as data rearrangement or computation execution, determining to achieve information interaction through the second information interaction path.

[0079] The purpose of data consistency detection is to ensure that the memory chip 100 has not experienced data corruption or address errors. Based on the memory control method provided in this embodiment, the correctness of the data stored in the memory chip is guaranteed by data consistency detection when receiving data transmitted in different paths, thus avoiding errors.

[0080] Optionally, the memory control method also includes: at any given time, only one information exchange path is accessible.

[0081] This setup not only enables matching of data / instructions and paths, but also ensures that only one information exchange path can be active at any given time, while the other path becomes inaccessible, thus preventing conflicts.

[0082] Optionally, in this embodiment, the memory chip 100 is a Flash memory chip, a DRAM memory chip, an SRAM memory chip, an MRAM chip, or an RRAM memory chip.

[0083] Optionally, the interface 120 of the memory bank 110 is configured to receive any combination of the following signals: address input signal, data input / output signal, word or byte select input signal, hardware reset / sector protection unlock signal, output enable signal, command lane signal, address lane signal, Ready / Busy indicator signal, differential clock signal, clock enable signal, chip select signal, row address strobe signal, column address strobe signal, write enable signal, data read / write clock signal, BANK address signal, data mask signal, termination resistor signal, calibration signal, command address signal, and data bus signal.

[0084] Optionally, when the memory has multiple stacked memory chips, the upper-layer memory chips and the lower-layer memory chips are connected via I / O through an advanced package interface and are jointly controlled by a memory group controller on the logic chip. For example, when a memory group controller on the logic chip is working, it can simultaneously access the memory groups on these memory chips corresponding to that memory group controller.

[0085] Optionally, this embodiment also provides an electronic device that uses the memory provided in this embodiment; the electronic device may be a computer.

[0086] The technical solution of this utility model has now been described in conjunction with the accompanying drawings. However, it will be readily understood by those skilled in the art that the protection scope of this utility model is obviously not limited to the specific embodiments described above. Without departing from the principles of this utility model, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions resulting from these changes or substitutions will all fall within the protection scope of this utility model.

Claims

1. A memory, characterized in that, The device includes a memory chip and a logic chip, which are packaged using a three-dimensional stacking process. The memory has a storage mode and a computing mode, and is configured as follows: In the aforementioned storage mode, information interaction between the storage chips is achieved through a first information interaction path; and In the aforementioned computing mode, information interaction between the memory chips is achieved through a second information interaction channel.

2. The memory according to claim 1, characterized in that, It also includes an interface circuit, which is configured for the memory to interact with external systems. The first information interaction path is located between the interface circuit and the memory chip, and the second information interaction path is located between the functional circuit of the logic chip and the memory chip.

3. The memory according to claim 2, characterized in that, The functional circuit includes circuits for implementing any or a combination of the following functions: error correction, multiplication, division, addition and subtraction calculation, buffering, control, protection, driving, load, connection and interface functions.

4. The memory according to claim 2 or 3, characterized in that, A control circuit is also provided, which is connected to the first information interaction path and the second information interaction path. The control circuit can arbitrate based on the instruction type for accessing the memory chip, and based on the arbitration result, selectively allow the memory chip to realize information interaction between the external and the memory chip through the first information interaction path or the second information interaction path.

5. The memory according to claim 4, characterized in that, The phrase "the control circuit is capable of arbitrating based on the instruction type for accessing the memory chip" includes: If the instruction type for accessing the memory chip is a memory access related instruction, it is determined that information interaction between the external system and the memory chip will be achieved through the first information interaction path; and If the instruction type for accessing the memory chip is a computation-related instruction, it is determined that information interaction between the external system and the memory chip will be achieved through the second information interaction path.

6. The memory according to claim 4, characterized in that, The first information interaction path includes a first data path and a first control path, and the second information interaction path includes a second data path and a second control path. The first data path and the second data path are used for data information transmission, and the first control path and the second control path are used for control information transmission. The control circuit is disposed in the memory chip, and the memory chip further includes: Storage circuitry, used to implement storage functions, includes multiple memory groups; Multiple data selection circuits are configured corresponding to the multiple memory groups, including a control terminal, a data interaction terminal, a first data path terminal, and a second data path terminal. The control terminal is connected to the control circuit, the data interaction terminal is connected to the multiple memory groups, and the first data path terminal and the second data path terminal are respectively connected to the first data path and the second data path. The data selection circuit can selectively connect the data interaction terminal to the first data path terminal or the second data path terminal based on the signal from the control terminal.

7. The memory according to claim 2 or 3, characterized in that, The interface circuit is located on the logic chip.

8. The memory according to claim 2 or 3, characterized in that, The interface circuit is located on the memory chip.

9. The memory according to claim 6, characterized in that, The memory chip is provided with a first interface for information interaction with the logic chip for each memory group. The logic chip is provided with a second interface in the stacking direction with the memory chip, corresponding to the position of the first interface. The first interface and the second interface are connected to form part of the second data path.

10. The memory according to claim 9, characterized in that, The first interface and the second interface are electrically connected using TSV, hybrid bonding or hybrid bonding technology.

11. An electronic device, characterized in that, The memory described in any one of claims 1-10 is used.

Images