Semiconductor device

Abstract

A semiconductor device includes a substrate, a multilayer metallization layer, a contact pad opening, a contact pad, an oxide layer, and a scribe line pad opening. The substrate has a front side surface, a rear side surface, and a contact pad region. The multi-layer metallization layer is located below the front side surface of the substrate and comprises an interconnection structure and an interlayer dielectric layer. A contact pad opening in the contact pad region extends through the substrate from above the back side surface to an interior region of the interlayer dielectric layer below the front side surface. The contact pad extends from the contact pad opening to the interconnect structure. An oxide layer is over the contact pad. A scribe line pad opening passes through the oxide layer to the contact pad.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of materials on a semiconductor substrate, and patterning the various material layers using lithography to form the circuit components and elements thereon.

[0003] The semiconductor industry continues to seek improved methods of manufacturing semiconductor devices. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the size of the smallest feature included in the semiconductor devices. However, as the smallest feature size decreases, additional problems arise that should be addressed. SUMMARY

[0004] The technical problem to be solved by the present application is to avoid the crystal defects caused by Si dislocations in the STI region.

[0005] In some implementations, a semiconductor device includes a substrate, a multilayer metallization layer, a contact pad opening, a contact pad, an oxide layer, and a scribe line pad opening. The substrate has a front side surface, a back side surface, and a contact pad region. The multilayer metallization layer is under the front side surface of the substrate and includes interconnect structures and interlayer dielectric layers. The contact pad opening extends through the substrate from above the back side surface to an interior region of the interlayer dielectric layer under the front side surface in the contact pad region. The contact pad extends from the contact pad opening to the interconnect structures. The oxide layer is over the contact pad. The scribe line pad opening extends through the oxide layer to the contact pad.

[0006] In some implementations, a semiconductor device includes a substrate having a front side surface, a back side surface, and a contact pad region; interconnect structures embedded in interlayer dielectric (ILD) layers under the front side surface of the substrate; an application specific integrated circuit (ASIC) bonded to a multilayer metallization layer formed under the front side surface; a first contact pad opening in the contact pad region extending through the substrate from above the back side surface to an interior region of the ILD layers under the front side surface; a contact pad extending from the first contact pad opening to the interconnect structures; an oxide layer formed over the contact pad; and a scribe line pad opening formed through the oxide layer to the contact pad.

[0007] In some implementations, a semiconductor device includes a semiconductor structure, a first contact liner opening, a contact liner, an oxide layer, and a scribe line liner opening. The semiconductor structure has a plurality of regions including a contact liner region, the semiconductor structure including a substrate having a shallow trench isolation region in the contact liner region and a multilayer metallization layer having an interlayer dielectric layer and an interconnect structure. The first contact liner opening is in the contact liner region and extends through the shallow trench isolation region to an interior region of the interlayer dielectric layer, where the first contact liner opening does not terminate at the shallow trench isolation region. The contact liner extends from the first contact liner opening to the interconnect structure. The oxide layer is over the contact liner. The scribe line liner opening is through the oxide layer to the contact liner.

[0008] The present application can produce the beneficial effects of avoiding crystal defects caused by Si dislocations in the STI region, thereby achieving high device reliability and effectively improving manufacturing yield. BRIEF DESCRIPTION OF DRAWINGS

[0009] Aspects of the disclosure are best understood from the following detailed description. Figure One It should be noted that the various features are not necessarily drawn to scale in order to illustrate the relevant art. Indeed, the dimensions of the various features can be arbitrarily increased or decreased for clarity sake.

[0010] Figure 1 depicts cross-sectional views of example portions of a semiconductor device according to some embodiments;

[0011] Figure 2 is a flowchart of an example method of manufacturing a CMOS image sensor (CIS) device according to some embodiments;

[0012] Figures 3A to 31 depicts cross-sectional views of a CIS device according to some embodiments at various stages of its manufacturing process;

[0013] Figure 4 is a cross-sectional schematic diagram illustrating an example anisotropic etch wall that can implement a scribe line liner opening according to some embodiments;

[0014] Figure 5 depicts a schematic cross-sectional view of an example portion of an example CIS device according to some embodiments;

[0015] Figure 6 depicts a schematic cross-sectional view of an example portion of an example CIS device according to some embodiments;

[0016] Figure 7 depicts a schematic cross-sectional view of an example portion of an example CIS device according to some embodiments;

[0017] Figure 8 schematic cross-sectional view depicting example portions of an example CIS device, in accordance with some embodiments;

[0018] Figure 9 schematic cross-sectional view depicting example portions of an example CIS device, in accordance with some embodiments.

[0019]

Symbolic Notations

[0020] 100: CIS device

[0021] 102: CIS SOC

[0022] 104: ASIC

[0023] 106: Pixel array region

[0024] 108: Periphery region

[0025] 110: PAD region

[0026] 112: Substrate

[0027] 112A: Front side surface

[0028] 112B: Back side surface

[0029] 114: First layer stack

[0030] 116: Second layer stack

[0031] 118: Multi-layer metallization layer

[0032] 120: Contact pad structure

[0033] 121: Interconnect structure

[0034] 121B: Interconnect structure

[0035] 122: ILD layer

[0036] 124: CESL layer

[0037] 126: First dielectric layer

[0038] 128: ARC layer

[0039] 130: First oxide layer

[0040] 132: Second oxide layer

[0041] 134: Metal layer

[0042] 135: Third oxide layer

[0043] 136: Grid line

[0044] 137: ground metal shield

[0045] 139: first ARC layer

[0046] 141: second ARC layer

[0047] 142: TiN layer

[0048] 143: fourth oxide layer

[0049] 200: method

[0050] 210-238: blocks

[0051] 302: patterned mask

[0052] 304: first cavity portion

[0053] 306: oxide layer

[0054] 308: second cavity portion

[0055] 310: oxide

[0056] 312: ground opening

[0057] 313: pixel opening

[0058] 314: scribe line pad opening

[0059] 410: straight wall

[0060] 500: CIS device

[0061] 502: CIS SOC

[0062] 504: ASIC

[0063] 506: pixel array region

[0064] 508: peripheral region

[0065] 510: PAD region

[0066] 512: substrate

[0067] 514: scribe line pad opening

[0068] 518: multi-layer metallization layer

[0069] 520: contact pad structure

[0070] 521: interconnect structure

[0071] 522: ILD layer

[0072] 523: oxide layer

[0073] 524: STI region

[0074] 552: first cavity portion

[0075] 600: CIS device

[0076] 602: CIS SOC

[0077] 604: ASIC

[0078] 606: pixel array region

[0079] 608: peripheral region

[0080] 610: PAD region

[0081] 612: substrate

[0082] 618: multi-layer metallization layer

[0083] 620A: first contact pad structure

[0084] 620B: second contact pad structure

[0085] 621: interconnect structure

[0086] 622: ILD layer

[0087] 623: oxide layer

[0088] 652A-652B: first cavity portion

[0089] 700: CIS device

[0090] 702: CIS SOC

[0091] 704: ASIC

[0092] 706: pixel array region

[0093] 708: peripheral region

[0094] 710: PAD region

[0095] 712: substrate

[0096] 718: multi-layer metallization layer

[0097] 720: contact pad structure

[0098] 721: interconnect structure

[0099] 722: ILD layer

[0100] 723: oxide layer

[0101] 752: first cavity portion

[0102] 800: CIS device

[0103] 802: CIS SOC

[0104] 804: ASIC

[0105] 806: pixel array region

[0106] 808: peripheral region

[0107] 810: PAD region

[0108] 812: substrate

[0109] 818: multi-layer metallization layer

[0110] 820A: first contact pad structure

[0111] 820B: second contact pad structure

[0112] 821: interconnect structure

[0113] 822: ILD layer

[0114] 823: oxide layer

[0115] 852A-852B: first cavity portion

[0116] 900: CIS device

[0117] 902: CIS SOC

[0118] 904: ASIC

[0119] 906: pixel array region

[0120] 908: peripheral region

[0121] 910: PAD region

[0122] 912: substrate

[0123] 918A-918B: multi-layer metallization layer

[0124] 920A: first contact pad structure

[0125] 920B: second contact pad structure

[0126] 921A-921B: interconnect structure

[0127] 922A-922B: ILD layer

[0128] 923: oxide layer

[0129] 952A-952B: first cavity portion DETAILED DESCRIPTION

[0130] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. These are, of course, merely examples and are in no way intended to be limiting.

[0131] For the sake of brevity, the principles disclosed herein can not be described in detail for all possible embodiments. In addition, various tasks and processes can be employed in the practices of the embodiments described herein without resorting to detailed logic flow diagrams. Furthermore, the various tasks and processes can be performed in the manner described herein or in a different manner. In addition, the embodiments described herein can be implemented in software and / or hardware. As would be apparent to one skilled in the art, such software can be tailored with specific logic to control how and over what frequency the embodiment actually performs. Also, a person skilled in the art would recognize that some of the boundaries between logic blocks are merely illustrative and the functionality of one part can be combined with that of another part. Conversely, the functionality of two or more parts can be combined into a single part.

[0132] Also for the sake of brevity, the processes and tasks of the various embodiments can be described herein as being performed by a single processor or other logic. However, as would be recognized by one of ordinary skill in the art, the processes and tasks can be performed by a single processor or other logic or can be divided amongst different processors or other logic, such as digital signal processors (DSPs), microprocessors, FPGAs, ASICs, microcontrollers, gate level logic, and / or any other logic. Also, a person of ordinary skill in the art would recognize that one or more of the processes and tasks can be performed at different times, possibly by different logic, and / or possibly in a different order. Accordingly, to the extent there is some variation between the descriptions of the processes and tasks of the various embodiments and their performance by different logic, such as a microprocessor versus a DSP, the processes and tasks described herein should not be construed so as to require that a single logic perform all processes and tasks or that one or more processes and tasks be performed only by a single logic.

[0133] Also, the present disclosure can repeat reference numerals and / or letters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0134] It should be noted that references to "an embodiment", "one embodiment", "an example embodiment", "an exemplary aspect", "an example", etc., indicate that the embodiment can include a particular feature, structure, or characteristic, but every embodiment can not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of those skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0135] It should be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in light of the teachings and

[0136] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. These are, of course, merely examples and are in no way limiting of the scope of the present disclosure. For example, in the following description, the formation of a first feature over or on a second feature can include embodiments in which the first feature is formed directly on the second feature, as well as embodiments in which additional features can be formed between the first and second features such that the first and second features are not directly in contact. Throughout this description, like reference numerals and characters can be used to denote like elements, unless otherwise described.

[0137] Semiconductor image sensors are used to sense incident visible or non-visible radiation, such as visible light, infrared light, etc. Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) and charge-coupled device (CCD) sensors are used in a variety of applications, such as digital still cameras, mobile phones, tablet computers, eyewear, etc. These image sensors utilize an array of pixels to absorb (e.g., sense) incident radiation and convert it into an electrical signal. One example of an image sensor is a backside illuminated (BSI) image sensor, which detects radiation from the "backside" of the substrate of the BSI image sensor.

[0138] A backside illuminated (BSI) image sensor is a type of CIS device. The BSI image sensor includes a pixel region formed on a substrate (e.g., a semiconductor substrate) and having an array of pixels or a radiation sensing region. The terms “radiation sensing region” and “pixel” are used interchangeably throughout this disclosure. A pixel is used to convert photons from incident radiation into an electrical signal. The electrical signal is then distributed to processing components attached to the BSI image sensor. For this reason, interconnect structures in a multi-layer metallization layer overlying the pixel region are used to distribute the electrical signal generated within the pixel to the appropriate processing components. The multi-layer metallization layer is formed on a first surface of the substrate, referred to as the “front side” surface of the substrate. The pixel region is formed on a second surface of the substrate opposite the front side surface of the substrate. This second surface of the substrate is referred to herein as the “back side” surface of the substrate. The pixel region includes a grid structure that provides optical isolation between adjacent pixels. In addition, the pixel region includes a color filter layer. The material of the color filter layer can be selected such that light having a desired wavelength passes through the color filter layer, while light having other wavelengths is absorbed by the color filter layer.

[0139] Components of the BSI image sensor (e.g., pixels, transistors, capacitors, memory structures, or other dies attached to the BSI image sensor) can be electrically coupled to external devices (e.g., external circuitry) via wire connectors attached to a pad structure formed on the back side surface of the substrate. To accomplish this, the pad structure of the BSI image sensor extends from the back side surface of the substrate to the front side surface of the substrate and is electrically connected to interconnect structures in the multi-layer metallization layer of the BSI image sensor. Thus, the interconnect structures in the multi-layer metallization layer that provide electrical signal connections to the BSI image sensor can be electrically connected to external devices or circuitry via the pad structure. The pad structure can be disposed at a periphery of the BSI image sensor surrounding the pixel region.

[0140] A challenge faced by BSI image sensors is achieving high device reliability. Device reliability of a BSI image sensor can be negatively impacted by stress accumulation during manufacturing operations. In a BSI image sensor, a pad structure can be constructed by forming a first cavity portion of a contact pad opening that terminates at a shallow trench isolation (STI) region in the substrate, followed by forming a second cavity portion of the contact pad opening that passes through the substrate and an interlayer dielectric (ILD) layer to an interconnect structure. Silicon (Si) dislocations in the STI region of the substrate can cause crystal defects due to stress accumulation from chemical mechanical polishing (CMP) operations during pixel construction, which negatively impacts manufacturing yield.

[0141] According to some embodiments of the present disclosure, the first cavity portion contacting the pad opening extends to the ILD layer without terminating at the STI region of the substrate. As a result, the STI region is not needed and crystal defects due to Si dislocations in the STI region can be avoided. Various intermediate stages of manufacturing the image sensor device are illustrated. Variations of the embodiments are also discussed. Throughout the various drawings and illustrative embodiments, the same reference numerals are used to denote like elements.

[0142] Figure 1 A schematic cross-sectional view depicting an example portion of an example CIS device 100. The example CIS device 100 includes a CIS system-on-a-chip (SOC) 102 and a carrier substrate, such as an application specific integrated circuit (ASIC) 104. The example CIS device 100, including the CIS SOC 102 and the ASIC 104, has a plurality of regions, including a pixel array region 106, a peripheral region 108 (such as a black level correction (BLC) region) laterally surrounding the pixel array region 106, and a contact pad (PAD) region 110. The example CIS device 100 can further include other regions, such as, for example, an alignment region, such as a scribe-line primary mark (SPM) region, not explicitly illustrated, as including it is not necessary for understanding the various embodiments described herein.

[0143] Example CIS SOC 102 includes a substrate 112 having a front side surface 112A and a back side surface 112B, a first layer stack 114 disposed on the back side surface 112B, a second layer stack 116 disposed on the front side surface 112A, a multi-layer metallization layer 118 disposed within the second layer stack 116, and a contact pad structure 120 disposed within the PAD region 110. The contact pad structure 120 is an input / output (I / O) port of the CIS device 100 and includes a conductive layer electrically coupled to an interconnect structure 121 of the multi-layer metallization layer 118, which is embedded in an ILD layer 122 of the multi-layer metallization layer 118. The example CIS SOC 102 can include additional components, such as microlenses on the first layer stack 114, solder bumps on the contact pad structure 120, metal wiring, active and / or passive devices, insulating layers, etch stop layers, and doped regions, which are not shown for simplicity. The example first layer stack 114 includes a first dielectric layer 126 (e.g., an oxide layer such as AlO, an oxynitride layer, or another suitable material having color filter properties), an ARC (anti-reflection coating) layer 128, a first oxide layer 130, a second oxide layer 132 (e.g., an oxide film such as undoped silicon glass (USG) or another suitable dielectric material), a metal layer 134, and a third oxide layer 135. The example second layer stack 116 includes a fourth oxide layer 143, a contact etch stop layer (CESL) 124, and the multi-layer metallization layer 118.

[0144] The substrate 112 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, a semiconductor wafer, or the like, which can be doped (e.g., with p-type or n-type dopants) or undoped. Other substrates, such as a multi-layer or graded substrate, can also be used. In some embodiments, the semiconductor material of the substrate can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0145] The interconnect structure 121 provides routing and electrical connections between device elements formed in and / or over the substrate 112. The interconnect structure 121 can include one or more electrically conductive features, which in this example include metal wires and / or vias formed therein in the multi-layer metallization layer 118. The electrically conductive features can be electrically connected to active and / or passive devices of the substrate 112 by contacts (not shown). In some embodiments, the interconnect structure 121 can be formed using a single damascene process and / or a dual damascene process, a via-first process, or a metal-first process.

[0146] The electrically conductive material for the metal wires and / or vias can be formed from a conductive material such as copper (Cu), aluminum (Al), tungsten (W), nickel, cobalt, silver, combinations thereof, or other suitable materials, and can be formed using an electrochemical plating process, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or combinations thereof. After the electrically conductive material is formed, a planarization process such as chemical mechanical polishing (CMP) can be used to remove excess electrically conductive material. Figure 1 The interconnect structure 121 shown in FIG. 1 is for illustrative purposes only. The interconnect structure 121 can include other configurations, and can include one or more metal wires and intermetal dielectric (IMD) layers.

[0147] The example pixel array region 106 includes a metal layer 134 having a metal grid structure, where grid lines 136 isolate pixels from one another. The example pixel array region 106 is to receive an incident radiation beam, which is converted into electrical signals in the pixel array region 106 via the first layer stack 114. The electrical signals are distributed to the ASIC 104 or external circuitry through the contact pad structure 120 and the interconnect structure 121. The ASIC 104 can be bonded to the multi-layer metallization layer 118 by molecular forces, a technique known as direct bonding or optical fusion bonding, or by other bonding techniques known in the art, such as metal diffusion or anodic bonding. In some embodiments, the ASIC 104 can include a material similar to the substrate 112, or can include a glass substrate. The ASIC 104 can include active devices (e.g., transistor structures) to form logic and memory circuits in the ASIC. Electrical connections between the active devices in the ASIC 104 and the first layer stack 114 are provided by an interconnect structure 121B in the ASIC 104.

[0148] The perimeter region 108 can include a ground metal shield 137 in the metal layer 134 that provides optical shielding for active devices (not shown) in the perimeter region 108 to keep the active devices optically dark. The active devices in the perimeter region 108 can be reference pixels used to establish a light intensity baseline for the CIS SOC 102. The PAD region 110 can include one or more conductive bond pads or solder bumps (not shown) on the contact pad structure 120 via which electrical connections between the CIS device 100 and external circuitry can be established.

[0149] The first layer stack 114 can include a first dielectric layer 126 on the backside surface 112B, an ARC layer 128 disposed on the first dielectric layer 126 to reduce reflection of incident light, a first oxide layer 130 disposed on the ARC layer 128, a metal layer 134 disposed on the first oxide layer 130, a second oxide layer 132 disposed on the metal layer 134, and a third oxide layer 135 disposed on the second oxide layer 132. In some embodiments, the ARC layer 128 can include a first ARC layer 139 and a second ARC layer 141. In various embodiments, the first ARC layer 139 includes a high-k dielectric material such as hafnium oxide (Hf02). In various embodiments, the second ARC layer 141 includes a high-k dielectric material such as tantalum oxide (Ta205). In other embodiments, the ARC layer 128 can include a high-k dielectric material such as titanium oxide (Ti02), hafnium zirconium oxide (HfZrO), hafnium silicate (HfSi04), zirconium oxide (Zr02), and zirconium silicate (ZrSi02), or other suitable high-k dielectric materials. In various embodiments, the third oxide layer 135 can include a plasma-enhanced oxide (PEOX) layer formed using a plasma-enhanced CVD process with a tetraethoxysilane (PETEOS) precursor. In some embodiments, the metal layer 134 includes a titanium nitride (TiN) layer 142. In some embodiments, the metal layer 134 includes tungsten (W) or other suitable metal material formed over the TiN layer 142.

[0150] In an embodiment, the substrate 112 is formed of Si, has a thickness of about 3 microns; the first dielectric layer 126 is formed of aluminum oxide (AlO), has a thickness of about 40 Angstroms (A); the first ARC layer 139 is formed of HfO2, has a thickness of about 60 A; the second ARC layer 141 is formed of Ta2O5, has a thickness of about 470 A; the first oxide layer 130 is a plasma-enhanced oxide (PEOX), has a thickness of about 700 A; the metal layer 134 has a TiN layer 142 of about 300 A and a tungsten (W) layer of about 1600 A; the second oxide layer 132 is formed of un-doped silicon glass (USG), has a thickness of about 4000 A; the third oxide layer 135 is a low deposited rate resistor protection oxide (LRPO), has a thickness of about 250 A; the CESL has a thickness of about 375 A; and the fourth oxide layer 143 has a thickness of about 385 A.

[0151] The contact pad structure 120 is formed in the first cavity portion of the contact pad opening, which extends to the ILD layer 122 without terminating at the STI region of the substrate 112. As a result, the STI region is not needed in the PAD region 110, and crystal defects due to Si dislocations in the STI region can be avoided.

[0152] Figure 2 A flowchart of an example method 200 for fabricating a CIS device according to some embodiments. For ease of illustration, the operations shown in Figures 3A to 31 will be described with reference to Figure 2 , which show cross-sectional views of a CIS device according to some embodiments at various stages of its fabrication process. The operations can be performed in different orders, or not at all, depending on the specific application program. Note that the method 200 can not result in a complete CIS device. Thus, it should be understood that additional processes can be provided before, during, and after the method, and that some other processes described herein can be modified or eliminated. Figures 3A to 31 The elements in have the same annotations as the elements in Figure 1 , as described above. In some figures, some reference numbers of components or features shown therein can be omitted to avoid obscuring other components or features; this is done for ease of drawing the figures.

[0153] Method 200 is merely an example and is not intended to limit the disclosure to anything that is specifically enumerated. Additional steps can be provided before, during, and after the example method 200, and some of the steps described can be moved, replaced, or eliminated, in additional embodiments of the example method 200. Additional features can be added to the semiconductor devices depicted in the figures, and some of the features described below can be replaced, modified, or eliminated in other embodiments of semiconductor devices.

[0154] It should be understood that components of the semiconductor devices can be fabricated by typical semiconductor technology process flows, and thus only some of the processes are described herein. Moreover, the example semiconductor devices can include various other devices and features, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, and / or other logic devices, etc., but are simplified for better understanding of the concepts of the disclosure. In some embodiments, the example devices include multiple semiconductor devices (e.g., transistors) that can be interconnected, including PFETs (P-channel field-effect transistors), NFETs (N-channel field-effect transistors), etc. Moreover, it should be noted that the operations of method 200, including any description given with reference to the figures, are merely examples and are not intended to be limiting of what is specifically enumerated in the following claims.

[0155] At block 210, the method 200 includes providing a substrate having a front side surface, a back side surface, a pixel array region, a perimeter region, and a contact pad region. Referring to the example of FIG. 1, in embodiments of block 210, the substrate 112 includes the front side surface 112A, the back side surface 112B, the pixel array region 106, the perimeter region 108, and the contact pad region 110. Figure 3A At block 210, the method 200 includes providing a substrate having a front side surface, a back side surface, a pixel array region, a perimeter region, and a contact pad region. Referring to the example of FIG. 1, in embodiments of block 210, the substrate 112 includes the front side surface 112A, the back side surface 112B, the pixel array region 106, the perimeter region 108, and the contact pad region 110.

[0156] At block 212, the method 200 includes forming a multilayer metallization layer adjacent to below the front side surface of the substrate, the multilayer metallization layer having interconnect structures embedded in interlayer dielectric (ILD) layers. After the multilayer metallization layer is formed on the front side surface, a carrier substrate such as an ASIC can then be bonded to the multilayer metallization layer. Referring to the example of FIG. 1, in embodiments of block 212, the multilayer metallization layer 118 is formed below the front side surface 112A of the substrate 112, the multilayer metallization layer 118 having interconnect structures 121 embedded in ILD layers 122. In the illustrated example, the interconnect structures 121B of the ASIC 104 are bonded to the interconnect structures 121 of the multilayer metallization layer 118. Figure 3A At block 212, the method 200 includes forming a multilayer metallization layer adjacent to below the front side surface of the substrate, the multilayer metallization layer having interconnect structures embedded in interlayer dielectric (ILD) layers. After the multilayer metallization layer is formed on the front side surface, a carrier substrate such as an ASIC can then be bonded to the multilayer metallization layer. Referring to the example of FIG. 1, in embodiments of block 212, the multilayer metallization layer 118 is formed below the front side surface 112A of the substrate 112, the multilayer metallization layer 118 having interconnect structures 121 embedded in ILD layers 122. In the illustrated example, the interconnect structures 121B of the ASIC 104 are bonded to the interconnect structures 121 of the multilayer metallization layer 118.

[0157] At block 214, the method 200 includes forming an anti-reflective coating (ARC) layer over the backside surface of the substrate. Referring to Figure 3A In an example of block 214, the ARC layer 128 is formed over the backside surface 112B of the substrate 112.

[0158] At block 216, the method 200 includes forming a first oxide layer over the ARC layer. Referring to Figure 3A In an example of block 216, the first oxide layer 130 is formed over the ARC layer 128.

[0159] At block 218, the method 200 includes forming a first cavity portion of the contact pad opening in the contact pad region, the first cavity portion extending from a top surface of the first oxide layer to an inner region of the ILD layer. In various embodiments, the first contact pad opening is formed by depositing a mask, patterning the mask with an opening, and etching the first cavity portion of the contact pad opening based on the patterned mask. In an embodiment, the mask is formed of silicon nitride (SiN) having a thickness of 880 A. Referring to Figure 3B In an example of block 218, a patterned mask 302 is formed over the first oxide layer 130, and a first cavity portion 304 of the contact pad opening is formed in the contact pad region 110, extending from the patterned mask 302 and a top surface of the first oxide layer 130 to an inner region of the ILD layer 122.

[0160] Thereafter, a contact pad structure 120 is formed in the first cavity portion 304 of the contact pad opening, the first cavity portion 304 extending to the ILD layer 122 without terminating at the STI region of the substrate 112. As a result, the STI region is not needed, and crystal defects due to Si dislocations in the STI region can be avoided.

[0161] At block 220, the method 200 includes forming an oxide (e.g., plasma-enhanced oxide (PEOX)) layer on sidewalls of the substrate and the ARC layer exposed by the first contact pad opening and on a top surface of the ILD layer exposed by the first contact pad opening. Forming the oxide layer on the sidewalls of the substrate and the ARC layer exposed by the first contact pad opening and on the top surface of the ILD layer exposed by the first contact pad opening involves depositing the oxide followed by etching the oxide. Referring to Figure 3CIn an example, in the embodiment of block 220, an oxide (e.g., plasma-enhanced oxide (PEOX)) layer 306 is formed on the sidewalls of the substrate 112 and ARC layer 128 exposed by the first cavity portion 304 of the contact liner opening and on the surface of the ILD layer 122 exposed by the first cavity portion 304 of the contact liner opening.

[0162] At block 222, the method 200 includes forming a contact liner extending from the first cavity portion of the contact liner opening to the interconnect structure. In various embodiments, forming a contact liner extending from the first cavity portion of the contact liner opening to the interconnect structure includes forming a second cavity portion of the contact liner opening and forming a contact liner in the second cavity portion of the contact liner opening, the second cavity portion extending to the interconnect structure from the oxide layer on the surface of the ILD layer exposed by the first cavity portion of the contact liner opening. In an embodiment, the contact liner is formed of aluminum copper (AlCu). In an embodiment, the AlCu contact liner is formed by depositing a layer of AlCu material and patterning and etching the layer of AlCu material to form the liner structure. Reference is made to FIG. 2B. Figure 3C In an example, in the embodiment of block 222, a second cavity portion 308 of the contact liner opening extending to the interconnect structure 121 is formed. Reference is made to FIG. 2B. Figure 3D In an example, in the embodiment of block 222, a contact liner structure 120 is formed in the second cavity portion 308 of the contact liner opening.

[0163] At block 224, the method 200 includes forming an outer layer of oxide in the first and second cavity portions of the contact liner opening above the substrate and above the contact liner. In various embodiments, forming an outer layer of oxide involves depositing an oxide layer using a PECVD process. Reference is made to FIG. 2B. Figure 3E In an example, in the embodiment of block 224, an outer layer of oxide 310 is formed in the first cavity portion 304 of the contact liner opening and the second cavity portion 308 of the contact liner opening above the substrate 112 and above the contact liner structure 120.

[0164] At block 226, the method 200 includes planarizing the oxide formed above the substrate. In various embodiments, planarizing the outer layer of oxide formed above the substrate includes using a CMP operation to remove the oxide over the patterned mask, remove the patterned mask, and remove a portion of the oxide over the ARC layer. In various embodiments, an etch operation is performed to remove the oxide over the patterned mask, the patterned mask, and the portion of the oxide over the ARC layer, followed by a CMP operation to planarize a top surface of the oxide over the ARC layer. Reference is made to FIG. 2B. Figure 3FIn an example, in an embodiment of block 226, the oxide over the patterned mask 302, the patterned mask 302, and a portion of the oxide over the ARC layer 128 have been removed. The oxide 310 over the ARC layer 128 has been planarized using a CMP operation.

[0165] At block 228, the method 200 includes forming a ground opening in the perimeter region. In various embodiments, forming the ground opening in the perimeter region involves an etching operation. Reference is made to Figure 3G In an example, in an embodiment of block 228, the ground opening 312 has been formed in the perimeter region 108.

[0166] At block 230, the method 200 includes forming a metal layer including grid lines in the pixel region and a ground metal shield in the perimeter region. In various embodiments, the metal layer is formed by depositing a layer of TiN over the pixel array region and the perimeter region, including in the ground opening, followed by depositing a layer of tungsten (W) over the layer of TiN. In various embodiments, forming the metal layer including grid lines in the pixel region and a ground metal shield in the perimeter region also includes depositing the layer of TiN and the layer of W over the PAD region when the layer of TiN and the layer of W are deposited over the pixel array region and the perimeter region, where portions of the layer of TiN and the layer of W deposited over the PAD region are removed in a subsequent operation.

[0167] At block 232, the method 200 includes forming a second oxide layer over the metal layer. In various embodiments, the second oxide layer is formed via deposition. In various embodiments, forming the second oxide layer over the metal layer also includes forming the second oxide layer over the metal layer in the PAD region, where portions of the second oxide formed over the PAD region are removed in a subsequent operation.

[0168] At block 234, the method 200 includes forming pixel openings in the pixel array region in the second oxide layer, the metal layer, and a portion of the first oxide layer, defining grid lines. In various embodiments, the pixel openings are formed via patterning and etching the metal layer. In various embodiments, forming the pixel openings in the pixel array region in the second oxide layer, the metal layer, and a portion of the first oxide layer also includes removing the portion of the second oxide layer, the metal layer, and the first oxide layer over the PAD region.

[0169] Reference is made to Figure 3HIn the example of FIG. 2, in the embodiment of blocks 230, 232, and 234, a metal layer 134 including the grid lines 136 in the pixel array region 106 and the ground metal shield 137 in the peripheral region 108 has been formed. A second oxide layer 132 has been formed over the metal layer 134. A pixel opening 313 has been formed in a portion of the second oxide layer 132, the metal layer 134, and the first oxide layer 130 in the pixel array region 106. In addition, the PAD region 110 does not have a metal layer 134 or a second oxide layer 132 formed thereover.

[0170] At block 236, the method 200 includes forming a third oxide layer over the second oxide layer. In various embodiments, forming the third oxide layer includes depositing a plasma-enhanced oxide (PEOX) using a CVD process. In various embodiments, forming the third oxide layer includes depositing the third oxide layer over the second oxide layer over the pixel array region and the peripheral region, and depositing the third oxide layer over the first oxide layer over the PAD region.

[0171] At block 238, the method 200 includes forming a scribe line pad opening over the contact pad. Referring to Figure 31 In the example of FIG. 2, in the embodiment of blocks 236 and 238, a third oxide layer 135 is formed over the second oxide layer 132, and a scribe line pad opening 314 is formed over the contact pad structure 120.

[0172] The aspect ratio of the scribe line pad opening 314 is much higher than the aspect ratio of a scribe line pad opening formed by a process that terminates the first contact pad opening at the STI region of the substrate. Because of the aspect ratio of the scribe line pad opening 314, an anisotropic etching technique can be employed to etch the scribe line pad opening 314.

[0173] Figure 4 FIG. 4 is a cross-sectional schematic diagram illustrating an example anisotropic etched wall that can be implemented for the scribe line pad opening 314. In this example, a technique such as a Bosch plasma etching process, a high aspect ratio plasma etching process, is employed. The Bosch plasma etching process can be used to etch a straight wall 410. The Bosch plasma etching process includes a cyclical process involving an isotropic etch followed by a protective film deposition using fast gas switching in a plasma etching chamber. The isotropic etch can involve Deep Reactive Ion Etching (DRIE), deposition of a protective coating over the etched area, and fast switching between etching and deposition steps during the fabrication process to carve (etch) a small portion of the opening and layer (deposit) material on the wall of the opening to protect the wall during further etching steps.

[0174] Although the foregoing examples are described with respect to forming a BSI image sensor without STI in the substrate in the PAD region, the foregoing devices, apparatuses, and methods can also be used in connection with forming a BSI image sensor with STI in the substrate in the PAD region. For example, Figure 5 A schematic cross-sectional view depicting example portions of an example CIS apparatus 500. The example CIS apparatus 500 includes a CIS system-on-a-chip (SOC) 502 and a carrier substrate, such as an application specific integrated circuit (ASIC) 504. The example CIS apparatus 500 has a plurality of regions, including a pixel array region 506, a peripheral region 508 (such as a black level correction (BLC) region) laterally surrounding the pixel array region 506, and a contact pad (PAD) region 510. The example CIS apparatus 500 can further include other regions.

[0175] The example CIS SOC 502 includes a substrate 512, a multi-layer metallization layer 518, and a pad structure 520 disposed within the PAD region 510. The substrate 512 includes an STI region 524 in the PAD region 510. The pad structure 520 includes a conductive layer electrically coupled to an interconnect structure 521 of the multi-layer metallization layer 518, which is embedded in an ILD layer 522 of the multi-layer metallization layer 518.

[0176] The interconnect structure 521 provides routing and electrical connections between device elements formed in and / or above the substrate 512. The interconnect structure 521 can include one or more conductive features, including in this example metal traces and / or vias formed therein in the multi-layer metallization layer 518. The conductive features can be electrically connected to active and / or passive devices of the substrate 512 through contacts (not shown in the figures). In some embodiments, the interconnect structure 521 can be formed using a single damascene process and / or a dual damascene process, a first via process, or a first metal process.

[0177] The contact pad structure 520 is formed in a first cavity portion 552 of the contact pad opening (e.g., with the oxide layer 523 and a portion of the STI region 524 disposed above the contact pad structure 520 in the first cavity portion 552), which extends to the ILD layer 522 without terminating at the STI region of the substrate 512. As a result, crystal defects due to Si dislocations in the STI region can be avoided.

[0178] A scribe line pad opening 514 is formed over the contact pad structure 520. The aspect ratio of the scribe line pad opening 514 is much higher than that of a scribe line pad formed by a process that terminates the first contact pad opening at the STI region of the substrate. Because of the aspect ratio of the scribe line pad opening 514, an anisotropic etching technique can be employed to etch the scribe line pad opening 514.

[0179] According to another embodiment, the devices, apparatuses, and methods described herein can also be used in connection with forming a BSI image sensor having a first cavity portion (extending to the ILD layer without terminating at the STI region of the substrate) of each of a plurality of contact pad openings. Figure 6 A schematic cross-sectional view of example portions of an example CIS apparatus 600 is depicted. The example CIS apparatus 600 includes a CIS system-on-a-chip (SOC) 602 and a carrier substrate, such as an application specific integrated circuit (ASIC) 604. The example CIS apparatus 600 has a plurality of regions, including a pixel array region 606, a peripheral region 608 (such as a black level correction (BLC) region) laterally surrounding the pixel array region 606, and a contact pad (PAD) region 610. The example CIS apparatus 600 can further include other regions.

[0180] The example CIS SOC 602 includes a substrate 612, a multi-layer metallization layer 618, and a plurality of first contact pad structures 620A and second contact pad structures 620B disposed within the PAD region 610. The first contact pad structures 620A and the second contact pad structures 620B each include a conductive layer electrically coupled to an interconnect structure 621 of the multi-layer metallization layer 618, which is embedded in an ILD layer 622 of the multi-layer metallization layer 618.

[0181] The first contact pad structures 620A are formed in first cavity portions 652A (e.g., with an oxide layer 623 disposed over the first contact pad structures 620A in the first cavity portions 652A) of the first contact pad openings, which extend to the ILD layer 622 without terminating at the STI region of the substrate 612. Similarly, the second contact pad structures 620B are formed in first cavity portions 652B (e.g., with an oxide layer 623 disposed over the second contact pad structures 620B in the first cavity portions 652B) of the second contact pad openings, which extend to the ILD layer 622 without terminating at the STI region of the substrate 612. As a result, the STI region is not needed, and crystal defects due to Si dislocations in the STI region can be avoided.

[0182] According to another embodiment, the devices, apparatuses, and methods described herein can also be used in connection with forming a BSI image sensor having a first cavity portion of a contact pad opening extending to an ILD layer of an ASIC without terminating at an STI region of the substrate. Figure 7 A schematic cross-sectional view depicting example portions of an example CIS apparatus 700. The example CIS apparatus 700 includes a CIS system-on-a-chip (SOC) 702 and a carrier substrate, such as an application specific integrated circuit (ASIC) 704. The example CIS apparatus 700 has a plurality of regions, including a pixel array region 706, a peripheral region 708 (such as a black level correction (BLC) region) laterally surrounding the pixel array region 706, and a contact pad (PAD) region 710. The example CIS apparatus 700 can further include other regions.

[0183] The example CIS SOC 702 includes a substrate 712. The example ASIC 704 includes a plurality of metallization layers 718 and a contact pad structure 720 disposed within the PAD region 710. The contact pad structure 720 includes a conductive layer electrically coupled to an interconnect structure 721 of the plurality of metallization layers 718, which is embedded in an ILD layer 722 of the plurality of metallization layers 718.

[0184] The contact pad structure 720 is formed in a first cavity portion 752 of the contact pad opening (e.g., with an oxide layer 723 disposed on the contact pad structure 720 in the first cavity portion 752) that extends through the CIS SOC 702 to the ILD layer 722 without terminating at an STI region of the substrate 712. As a result, an STI region is not needed, and crystal defects due to Si dislocations in the STI region can be avoided.

[0185] Other configurations are also contemplated in which a contact pad structure is formed in a first cavity portion of a contact pad opening that extends to an ILD layer without terminating at an STI region of a substrate. For example, Figure 8An illustrative cross-sectional view depicting example portions of a CIS device 800. The example CIS device 800 includes a CIS system-on-a-chip (SOC) 802 and a carrier substrate, such as an application specific integrated circuit (ASIC) 804. The example CIS device 800 has multiple regions, including a pixel array region 806, a perimeter region 808 (such as a black level correction (BLC) region) laterally surrounding the pixel array region 806, and a contact pad (PAD) region 810. The example CIS device 800 can further include other regions. The example CIS SOC 802 includes a substrate 812. The example ASIC 804 includes a multi-layer metallization layer 818, and a first contact pad structure 820A and a second contact pad structure 820B disposed within the PAD region 810. The first and second contact pad structures 820A, 820B include electrically conductive layers that are electrically coupled to interconnect structures 821 of the multi-layer metallization layer 818, which are embedded in ILD layers 822 of the multi-layer metallization layer 818. In this example, the first contact pad structure 820A is formed in a first cavity portion 852A of a first contact pad opening (e.g., with an oxide layer 823 disposed over the contact pad structure 820A in the first cavity portion 852A), which extends through the CIS SOC 802 to the ILD layers 822 without terminating at a STI region of the substrate 812. Additionally, the second contact pad structure 820B is formed in a first cavity portion 852B of a second contact pad opening (e.g., with an oxide layer 823 disposed over the contact pad structure 820B in the first cavity portion 852B), which extends through the CIS SOC 802 to the ILD layers 822 without terminating at a STI region of the substrate. As a result, a STI region is not needed, and crystal defects due to Si dislocations in the STI region can be avoided.

[0186] In another example, Figure 9A schematic cross-sectional view depicting example portions of another example CIS device 900. The example CIS device 900 includes a CIS system-on-a-chip (SOC) 902 and a carrier substrate, such as an application specific integrated circuit (ASIC) 904. The example CIS device 900 has multiple regions, including a pixel array region 906, a perimeter region 908 (such as a black level correction (BLC) region) laterally surrounding the pixel array region 906, and a contact pad (PAD) region 910. The example CIS device 900 can further include other regions. The example CIS SOC 902 includes a substrate 912. The example CIS SOC 902 includes a multi-layer metallization layer 918A, and the example ASIC 904 includes a multi-layer metallization layer 918B. A first contact pad structure 920A and a second contact pad structure 920B are disposed within the PAD region 910. The first contact pad structure 920A includes a conductive layer electrically coupled to an interconnect structure 921A of the multi-layer metallization layer 918A embedded in an ILD layer 922A of the multi-layer metallization layer 918A, and the second contact pad structure 920B includes a conductive layer electrically coupled to an interconnect structure 921B of the multi-layer metallization layer 918B embedded in an ILD layer 922B of the multi-layer metallization layer 918B. In this example, the first contact pad structure 920A can be formed in a first cavity portion 952A of a first contact pad opening extending to the ILD layer 922A without terminating at an STI region of the substrate 912 (e.g., with an oxide layer 923 disposed over the contact pad structure 920A in the first cavity portion 952A), and the second contact pad structure 920B can be formed in a first cavity portion 952B of a second contact pad opening extending through the CIS SOC 902 to the ILD layer 922B without terminating at an STI region of the substrate 912 (e.g., with an oxide layer 923 disposed over the contact pad structure 920B in the first cavity portion 952B). As a result, an STI region is not needed, and crystal defects due to Si dislocations in the STI region can be avoided.

[0187] In some aspects, the techniques described herein are directed to a method of manufacturing a semiconductor device, comprising: providing a substrate having a front side surface, a back side surface, and a contact pad region; providing an interconnect structure embedded in an interlayer dielectric (ILD) layer under the front side surface of the substrate; forming a first cavity portion of a contact pad opening in the contact pad region extending through the substrate from above the back side surface to an interior region of the ILD layer under the front side surface; forming an oxide layer over the contact pad; and forming a scribe line pad opening through the oxide layer to the contact pad.

[0188] In some aspects, the techniques described herein are directed to a method of manufacturing, wherein providing an interconnect structure embedded in an ILD layer comprises forming a multi-layer metallization layer under the front side surface of the substrate, the multi-layer metallization layer comprising the interconnect structure and the ILD layer.

[0189] In some aspects, the techniques described herein are directed to a method of manufacturing a semiconductor device, further comprising bonding an application specific integrated circuit (ASIC) to the multi-layer metallization layer formed under the front side surface, and wherein the interconnect structure and the ILD layer are embedded in the ASIC.

[0190] In some aspects, the techniques described herein are directed to a method of manufacturing a semiconductor device, further comprising forming an anti-reflective coating (ARC) layer over the back side surface of the substrate, and forming a first oxide layer over the ARC layer, and wherein: forming the first cavity portion of the contact pad opening comprises forming the first cavity portion of the contact pad opening to extend from a top surface of the first oxide layer to the interior region of the ILD layer.

[0191] In some aspects, the techniques described herein are directed to a method of manufacturing a semiconductor device, further comprising forming an oxide layer on sidewall portions of the substrate exposed by the first cavity portion of the contact pad opening, sidewall portions of the ARC layer exposed by the first cavity portion of the contact pad opening, and a surface of the ILD layer exposed by the first cavity portion of the contact pad opening.

[0192] In some aspects, the techniques described herein are directed to a method of manufacturing a semiconductor device, wherein forming the contact pad comprises: forming the oxide layer on a surface of the ILD layer exposed by the first cavity portion of the free contact pad opening of the contact pad opening to extend to a second cavity portion of the interconnect structure; and forming the contact pad in the second cavity portion of the contact pad opening.

[0193] In some aspects, the techniques described herein are directed to a method of manufacturing a semiconductor device, wherein forming a scribe line pad opening through an oxide layer to a contact pad includes performing an anisotropic etching operation to form the scribe line pad opening.

[0194] In some aspects, the techniques described herein are directed to a method of manufacturing a semiconductor device, wherein performing an anisotropic etching operation includes performing a cyclic process involving an isotropic etching and a subsequent protective film deposition.

[0195] In some aspects, the techniques described herein are directed to a semiconductor device, comprising: a substrate having a front side surface, a back side surface, and a contact pad region; an interconnect structure embedded in an interlayer dielectric (ILD) layer under the front side surface of the substrate; an application specific integrated circuit (ASIC) bonded to a multi-layer metallization layer formed under the front side surface; a first contact pad opening in the contact pad region extending through the substrate from above the back side surface to an interior region of the ILD layer under the front side surface; a contact pad extending from the first contact pad opening to the interconnect structure; an oxide layer formed over the contact pad; and a scribe line pad opening formed through the oxide layer to the contact pad.

[0196] In some aspects, the techniques described herein are directed to a semiconductor device, wherein the multi-layer metallization layer comprises the interconnect structure and the ILD layer.

[0197] In some aspects, the techniques described herein are directed to a semiconductor device, wherein the interconnect structure and the ILD layer are embedded in the ASIC.

[0198] In some aspects, the techniques described herein are directed to a semiconductor device, wherein the contact pad comprises aluminum copper (AlCu).

[0199] In some aspects, the techniques described herein are directed to a semiconductor device, further comprising: a second contact pad opening in the contact pad region extending through the substrate from above the back side surface to the interior region of the ILD layer under the front side surface; a second contact pad extending from the second contact pad opening to the interconnect structure, wherein the oxide layer is formed over the contact pad; and a second scribe line pad opening formed through the oxide layer to the contact pad.

[0200] In some aspects, the techniques described herein are directed to a semiconductor device, further comprising: an anti-reflective coating (ARC) layer over a backside surface of the substrate; and a first oxide layer over the ARC layer, wherein the first contact pad opening extends from a top surface of the first oxide layer to an interior region of the ILD layer.

[0201] In some aspects, the techniques described herein are directed to a method of manufacturing a semiconductor device, comprising: providing a semiconductor structure having a plurality of regions including a contact pad region, the semiconductor structure comprising a substrate having a shallow trench isolation (STI) region in the contact pad region and a multi-layer metallization layer having an interconnect structure embedded in an interlayer dielectric (ILD) layer; forming a first contact pad opening in the contact pad region, the first contact pad opening extending through the STI region to an interior region of the ILD, wherein the first contact pad opening does not terminate at the STI region; forming a contact pad extending from the first contact pad opening to the interconnect structure; forming an oxide layer over the contact pad; and forming a scribe line pad opening through the oxide layer to the contact pad.

[0202] In some aspects, the techniques described herein are directed to a method of manufacturing a semiconductor device, further comprising forming an anti-reflective coating (ARC) layer over a backside surface of the substrate and forming a first oxide layer over the ARC layer, and wherein: forming the first contact pad opening comprises forming the first contact pad opening extending from a top surface of the first oxide layer to an interior region of the ILD layer.

[0203] In some aspects, the techniques described herein are directed to a method of manufacturing a semiconductor device, further comprising forming an oxide layer on sidewall portions of the substrate exposed by the first contact pad opening, sidewall portions of the ARC layer exposed by the first contact pad opening, and a surface of the ILD layer exposed by the first contact pad opening.

[0204] In some aspects, the techniques described herein are directed to a method of manufacturing a semiconductor device, wherein forming the contact pad comprises: forming an oxide layer on a surface of the ILD layer free of the first contact pad opening extending to a second cavity portion of the interconnect structure; and forming the contact pad in the second cavity portion of the first contact pad opening.

[0205] In some aspects, the techniques described herein are directed to a method of manufacturing a semiconductor device, wherein forming the scribe line pad opening through the oxide layer to the contact pad comprises performing an anisotropic etching operation to form the scribe line pad opening.

[0206] In some aspects, the techniques described herein are directed to a method of manufacturing a semiconductor device, wherein performing an anisotropic etching operation comprises performing a cyclic process involving an isotropic etch followed by a protective film deposition.

[0207] In some embodiments, a semiconductor device includes a substrate, a multilayer metallization layer, a contact pad opening, a contact pad, an oxide layer, and a scribe line pad opening. The substrate has a front side surface, a back side surface, and a contact pad region. The multilayer metallization layer is under the front side surface of the substrate and includes an interconnect structure and an interlayer dielectric layer. The contact pad opening extends through the substrate from above the back side surface to an interior region of the interlayer dielectric layer under the front side surface in the contact pad region. The contact pad extends from the contact pad opening to the interconnect structure. The oxide layer is over the contact pad. The scribe line pad opening extends through the oxide layer to the contact pad.

[0208] In some aspects, the interconnect structure is embedded in the interlayer dielectric layer.

[0209] In some aspects, the semiconductor device further includes an antireflective coating layer and a first oxide layer. The first oxide layer is over the antireflective coating layer, wherein the contact pad opening extends from a top surface of the first oxide layer to the interior region of the interlayer dielectric layer.

[0210] In some aspects, the semiconductor device further includes an antireflective coating layer disposed over the back side surface, wherein the oxide layer covers a plurality of sidewall portions of the substrate and a plurality of sidewall portions of the antireflective coating layer.

[0211] In some embodiments, a semiconductor device includes a semiconductor structure, a first contact pad opening, a contact pad, an oxide layer, and a scribe line pad opening. The semiconductor structure has a plurality of regions including a contact pad region, the semiconductor structure including a substrate having a shallow trench isolation region in the contact pad region and a multilayer metallization layer having an interlayer dielectric layer and an interconnect structure. The first contact pad opening is in the contact pad region and extends through the shallow trench isolation region to an interior region of the interlayer dielectric layer, wherein the first contact pad opening does not terminate at the shallow trench isolation region. The contact pad extends from the first contact pad opening to the interconnect structure. The oxide layer is over the contact pad. The scribe line pad opening extends through the oxide layer to the contact pad.

[0212] In some aspects, the semiconductor device further includes an antireflective coating layer and a first oxide layer. The first oxide layer is over the antireflective coating layer, wherein the contact pad opening extends from a top surface of the first oxide layer to the interior region of the interlayer dielectric layer.

[0213] In some aspects, wherein the oxide layer covers a plurality of sidewall portions of the substrate and a plurality of sidewall portions of the antireflective coating layer.

[0214] In some aspects, the interconnect structure is embedded in an interlayer dielectric layer.

[0215] While at least one exemplary embodiment has been presented in the foregoing detailed description of the disclosure, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the disclosure in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the disclosure. It should be understood that various changes can be made in the function and arrangement of elements described in the exemplary embodiment without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. A semiconductor device, characterized by comprising: Comprising: a substrate having a front side surface, a back side surface, and a contact pad region; a multilayer metallization layer underlying the front side surface of the substrate and including an interconnect structure and an interlevel dielectric layer; a contact pad opening in the contact pad region extending through the substrate from above the back side surface to an interior region of the interlevel dielectric layer underlying the front side surface; a contact pad extending from the contact pad opening to the interconnect structure; an oxide layer over the contact pad; and a scribe line pad opening through the oxide layer to the contact pad. wherein the interconnect structure is embedded in the interlevel dielectric layer.

2. The semiconductor device according to claim 1, wherein Further comprising:

3. The semiconductor device according to claim 1 or claim 2, wherein an antireflective coating layer; and a first oxide layer over the antireflective coating layer, wherein the contact pad opening extends from a top surface of the first oxide layer to the interior region of the interlevel dielectric layer. Further comprising:

4. The semiconductor device according to claim 1 or claim 2, wherein an antireflective coating layer disposed over the back side surface, wherein the oxide layer covers sidewall portions of the substrate and sidewall portions of the antireflective coating layer. Comprising:

5. A semiconductor device, characterized by comprising: a substrate having a front side surface, a back side surface, and a contact pad region; an interconnect structure embedded in an interlevel dielectric layer underlying the front side surface of the substrate; a special application integrated circuit bonded to a multilayer metallization layer formed underlying the front side surface; a first contact pad opening in the contact pad region extending through the substrate from above the back side surface to a first interior region of the interlevel dielectric layer underlying the front side surface; a contact pad extending from the first contact pad opening to the interconnect structure; an oxide layer formed over the contact pad; and a scribe line pad opening formed through the oxide layer to the contact pad. Further comprising: a second contact pad opening in the contact pad region extending through the substrate from above the back side surface to a second interior region of the interlevel dielectric layer underlying the front side surface; 6. The semiconductor device according to claim 5, wherein a second contact pad extending from the second contact pad opening to the interconnect structure, wherein the oxide layer is formed over the contact pad; and a second scribe line pad opening formed through the oxide layer to the contact pad. Comprising: a semiconductor structure having regions including a contact pad region, the semiconductor structure including a substrate having a shallow trench isolation region in the contact pad region and a multilayer metallization layer having an interlevel dielectric layer and an interconnect structure; a first contact pad opening in the contact pad region extending through the shallow trench isolation region to an interior region of the interlevel dielectric layer, wherein the first contact pad opening does not terminate at the shallow trench isolation region; 7. A semiconductor device, characterized by comprising: a contact pad extending from the first contact pad opening to the interconnect structure; an oxide layer over the contact pad; and a scribe line pad opening through the oxide layer to the contact pad. Further comprising: an antireflective coating layer; and a first oxide layer over the antireflective coating layer, wherein the first contact pad opening extends from a top surface of the first oxide layer to the interior region of the interlevel dielectric layer. ​ 8. The semiconductor device according to claim 7, wherein ​ ​ ​ 9. The semiconductor device according to claim 8, wherein wherein the oxide layer covers sidewall portions of the substrate and sidewall portions of the antireflective coating layer.

10. The semiconductor device according to any one of Claims 7 to 9, wherein wherein the interconnect structure is embedded in the interlayer dielectric layer.

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