Circuit structure
By adding conductive bumps at the joint of conductive blind vias, the problem of easy cracking of conductive blind vias is solved, and the reliability and stability of the circuit structure are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-09
- Publication Date
- 2026-03-24
AI Technical Summary
In existing technologies, the junction of conductive blind vias is prone to cracking due to stress input, which limits wiring density and signal transmission speed.
Conductive bumps are placed at the joints of conductive blind holes to increase the contact area and avoid stress-induced cracking.
By adding conductive bumps, the contact area of conductive blind vias is increased, preventing cracking at the via overlap and improving the reliability and stability of the circuit structure.
Smart Images
Figure CN224037819U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a semiconductor structure, in particular to a wiring structure. BACKGROUND
[0002] With the rapid development of electronic industry, electronic products tend to be light, thin, short and small in shape, and high performance, high function and high speed in function. Therefore, in order to meet the requirements of high integration and miniaturization of semiconductor devices, packaging substrates with thinning, low warping, high density wiring and other designs are often used in packaging processes.
[0003] Figures 1A-1D A cross-sectional view of a conventional packaging substrate manufacturing method.
[0004] As shown in Figure 1A , a core layer 10 is provided, and a conductive via 100 is formed in the core layer 10.
[0005] As shown in Figure 1B , copper foil dielectric material 11 is pressed on both sides of the core layer 10.
[0006] As shown in Figure 1C , a first blind hole 110 is formed in the copper foil dielectric material 11, and chemical copper 12 is deposited and electroplating copper process is performed to form a first wiring layer 13 on the copper foil dielectric material 11 and a first conductive blind hole 130 in the first blind hole 110.
[0007] As shown in Figure 1D , another copper foil dielectric material 14 is pressed on the first wiring layer 13, a second blind hole 140 is formed in the other copper foil dielectric material 14, and then chemical copper is deposited and electroplating copper process is performed to form a second wiring layer 15 on the first wiring layer 13 and a second conductive blind hole 150 in the second blind hole 140.
[0008] However, in order to increase the wiring density and speed up the signal transmission of modern electronic products, the aperture of the conductive blind hole must be reduced and the design must be stacked. However, the interface of the current stacked hole is a 2D interface of electroplated copper-chemical copper-electroplated copper, and when stress is input, the bottom of the conductive blind hole is prone to crack along the 2D interface.
[0009] Therefore, how to overcome the various problems of the prior art has become a pressing issue to be solved. CONTENT OF THE INVENTION
[0010] In view of the aforementioned deficiencies of the prior art, the present application provides a circuit structure, comprising: a first dielectric material; a first circuit layer formed on the first dielectric material; a plurality of first conductive blind holes formed in the first dielectric material and connected to the first circuit layer; a second dielectric material formed on the first circuit layer; a second circuit layer formed on the second dielectric material; a plurality of second conductive blind holes formed in the second dielectric material and connected to the second circuit layer, and each of the second conductive blind holes is stacked on each of the first conductive blind holes; and a plurality of conductive bumps respectively arranged at the junctions of each of the first conductive blind holes and the corresponding each of the second conductive blind holes.
[0011] The present application also provides a method for manufacturing a circuit structure, comprising: forming a first circuit layer on a first dielectric material, and forming a plurality of first conductive blind holes in the first dielectric material and connected to the first circuit layer; forming a conductive bump on each of the first conductive blind holes; forming a second dielectric material on the first circuit layer; and forming a second circuit layer on the second dielectric material, and forming a plurality of second conductive blind holes in the second dielectric material and connected to the second circuit layer, wherein each of the second conductive blind holes is stacked on each of the first conductive blind holes, and each of the conductive bumps is arranged at the junction of each of the first conductive blind holes and the corresponding each of the second conductive blind holes.
[0012] The aforementioned circuit structure and the method for manufacturing the same further comprise providing a substrate for disposing the first dielectric material.
[0013] The aforementioned circuit structure and the method for manufacturing the same further comprise providing a substrate for disposing the first dielectric material.
[0014] The aforementioned circuit structure and the method for manufacturing the same further comprise providing a substrate for disposing the first dielectric material.
[0015] The aforementioned circuit structure and the method for manufacturing the same further comprise providing a substrate for disposing the first dielectric material.
[0016] The aforementioned circuit structure and the method for manufacturing the same further comprise providing a substrate for disposing the first dielectric material.
[0017] The aforementioned circuit structure and the method for manufacturing the same further comprise providing a substrate for disposing the first dielectric material.
[0018] The aforementioned circuit structure and the method for manufacturing the same further comprise providing a substrate for disposing the first dielectric material.
[0019] From the above, the circuit structure of the present application mainly increases the contact area of the first conductive blind hole and the second conductive blind hole (and the first conductive blind hole and the conductive via hole) by setting the conductive bump at the joint of the first conductive blind hole and the second conductive blind hole (and the first conductive blind hole and the conductive via hole), so as to avoid the problem of crack damage at the stacked hole due to stress. BRIEF DESCRIPTION OF DRAWINGS
[0020] Figures 1A-1D A cross-sectional schematic view of the manufacturing method of the existing packaging substrate.
[0021] Figures 2A-2E A cross-sectional schematic view of the manufacturing method of the circuit structure of the present application.
[0022] Figure 3 A cross-sectional schematic view of another embodiment of the circuit structure of the present application.
[0023] REFERENCE NUMERALS
[0024] 10 core layer
[0025] 100 conductive via hole
[0026] 11 copper foil dielectric material
[0027] 110 first blind hole
[0028] 12 chemical copper
[0029] 13 first circuit layer
[0030] 130 first conductive blind hole
[0031] 14 another copper foil dielectric material
[0032] 140 second blind hole
[0033] 15 second circuit layer
[0034] 150 second conductive blind hole
[0035] 2, 3 circuit structure
[0036] 20 core board
[0037] 200 conductive via hole
[0038] 21 first dielectric material
[0039] 210 first blind hole
[0040] 211 first metal layer
[0041] 22 conductive layer
[0042] 23 first circuit layer
[0043] 230 First conductive blind hole
[0044] 24 Second Dielectric Material
[0045] 240 Second blind hole
[0046] 241 Second metal layer
[0047] 25 Conductive layer
[0048] 26 Second Line Layer
[0049] 260 Second conductive blind hole
[0050] 30 Wiring Layer
[0051] b1 First conductive bump
[0052] b2 Second conductive bump. Detailed Implementation
[0053] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.
[0054] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the scope of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this application, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," and "one" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.
[0055] Figures 2A-2E This is a cross-sectional schematic diagram of the manufacturing method of the circuit structure 2 of this application.
[0056] like Figure 2A As shown, a substrate is provided. In this embodiment, the substrate is a core board 20 (which includes a core layer and copper foils on both sides), and at least one plurality of conductive vias 200 penetrating the core layer are formed in the core board 20 (for ease of viewing, only one conductive via 200 is shown in the figure). In other embodiments, the substrate may also be an insulating layer, a wiring layer, or a carrier board, etc.
[0057] like Figure 2BAs shown, first conductive bumps b1 are electroplated at both ends of the conductive through hole 200, and first dielectric material 21 with a first metal layer 211 is pressed onto both sides of the core plate 20. The planar dimension of the first conductive bump b1 is smaller than the planar dimension of the end of the conductive through hole 200.
[0058] The first dielectric material 21 is, for example, a prepreg (PP), polybenzoxazole (PBO), or polyimide (PI), and the first metal layer 211 is, for example, copper foil.
[0059] like Figure 2C As shown, at least one first blind hole 210 is formed on the first dielectric material 21 having a first metal layer 211, wherein the first blind hole 210 corresponds to the position of the conductive via 200, and the first conductive bump b1 is exposed outside the first blind hole 210.
[0060] The first blind hole 210 can be formed by laser drilling, and its shape can be cone-shaped or funnel-shaped as shown in the figure.
[0061] In one embodiment, the planar dimension (width) of the first conductive bump b1 is 0.3 to 0.5 times the bottom diameter of the first blind hole 210, and the height of the first conductive bump b1 is at least 5 micrometers (um), but is not limited thereto.
[0062] Then, a conductive layer 22 is formed on the first dielectric material 21 with the first metal layer 211 and inside the first blind via 210 (including the outer surface of the first conductive bump b1). The conductive layer 22 is fabricated by depositing chemical copper.
[0063] like Figure 2D As shown, a first circuit layer addition process is performed to form a first circuit layer 23 and a first conductive blind via 230 on both sides of the core board 20. In this embodiment, the first circuit layer 23 is formed on the first dielectric material 21 using an electroplating process, and the first conductive blind via 230 is formed in the first blind via 210. The first conductive blind via 230 is stacked above the conductive via 200, so that the first conductive bump b1 is located at the junction of the first conductive blind via 230 and the conductive via 200. Then, a second conductive bump b2 is formed at the exposed end of the first conductive blind via 230, and the planar dimension of the second conductive bump b2 is smaller than the planar dimension of the end of the first conductive blind via 230.
[0064] The conductive layer 22 serves as a seed layer, and is made of electroplated copper material, which is used as the first circuit layer 23.
[0065] like Figure 2EAs shown, a second circuit layer addition process is performed. Referring to the aforementioned process, a second dielectric material 24 with a second metal layer 241 is formed on the first circuit layer 23, a second blind via 240 is formed, a conductive layer 25 is formed, and a second circuit layer 26 and a second conductive blind via 260 are formed by electroplating. The second conductive blind via 260 is stacked on top of the first conductive blind via 230, and the second conductive bump b2 is sandwiched between the first conductive blind via 230 and the second conductive blind via 260 to form the circuit structure 2 of this application. The circuit structure 2, which is combined with the core board 20, can serve as a packaging substrate for carrying the chip.
[0066] In one embodiment, the planar dimension (width) of the second conductive bump b2 is 0.3 to 0.5 times the bottom diameter of the second blind hole 240. Additionally, the height of the second conductive bump b2 is at least 5 micrometers (µm).
[0067] Please see Figure 3 This is a cross-sectional view of another embodiment of the redistribution circuit structure 3 of this application. This embodiment is largely the same as the previous embodiment, with the main difference being that a substrate such as the wiring layer 30 is provided, and a first circuit layer 23 (with a first conductive blind via 230) and a second circuit layer 26 (with a second conductive blind via 260) are sequentially stacked on the wiring layer 30. A second conductive bump b2 is formed at the junction of the first conductive blind via 230 and the corresponding second conductive blind via 260 to form a multilayer circuit structure.
[0068] Through the aforementioned manufacturing method, this application also discloses a circuit structure 2,3, comprising: a first dielectric material 21; a first circuit layer 23 formed on the first dielectric material 21; a plurality of first conductive blind vias 230 formed in the first dielectric material 21 and connected to the first circuit layer 23; a second dielectric material 24 formed on the first circuit layer 23; a second circuit layer 26 formed on the second dielectric material 24; a plurality of second conductive blind vias 260 formed in the second dielectric material 24 and connected to the second circuit layer 26, wherein each of the second conductive blind vias 260 is correspondingly stacked on each of the first conductive blind vias 230; and a plurality of conductive bumps (second conductive bumps b2) respectively disposed at the junction of each of the first conductive blind vias 230 and the corresponding second conductive blind vias 260.
[0069] The aforementioned circuit structure also includes a substrate for mounting the first dielectric material 21.
[0070] The substrate may be an insulating layer, a wiring layer 30, a carrier board, or a core board 20. The core board 20 has at least one or more conductive vias 200, and each of the first conductive blind vias 230 is stacked on the corresponding conductive via 200, and a conductive bump (first conductive bump b1) is sandwiched between each conductive via 200 and the corresponding first conductive blind via 230.
[0071] In summary, the circuit structure of this application mainly increases the contact area between the first and second conductive blind holes (and the first conductive blind hole and the conductive through hole) by setting conductive bumps at the junction of the first conductive blind hole and the second conductive blind hole (and the first conductive blind hole and the conductive through hole), thereby avoiding the problem of cracking at the overlapping hole due to stress.
[0072] The above embodiments are illustrative of the principles and effects of this application and are not intended to limit this application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be as set forth in the claims.
Claims
1. A circuit structure, characterized in that, include: First dielectric material; The first circuit layer is formed on the first dielectric material; Multiple first conductive blind vias are formed in the first dielectric material and connected to the first circuit layer; The second dielectric material is formed on the first circuit layer; The second circuit layer is formed on the second dielectric material; Multiple second conductive blind vias are formed in the second dielectric material and connected to the second circuit layer, and each of the second conductive blind vias is stacked on top of each of the first conductive blind vias; as well as Multiple conductive bumps are formed at the junction of each of the first conductive blind holes and the corresponding second conductive blind holes.
2. The circuit structure as described in claim 1, characterized in that, The circuit structure also includes a substrate for mounting the first dielectric material.
3. The circuit structure as described in claim 2, characterized in that, The substrate can be an insulating layer, a wiring layer, a carrier board, or a core board.
4. The circuit structure as described in claim 3, characterized in that, The core board has multiple conductive vias, and each of the first conductive blind vias is stacked on the conductive via.
5. The circuit structure as described in claim 4, characterized in that, A conductive bump is sandwiched between each conductive through hole and the corresponding first conductive blind hole.
6. The circuit structure as described in claim 1, characterized in that, The height of the conductive bump is at least 5 micrometers.
7. The circuit structure as described in claim 1, characterized in that, The second dielectric material has a plurality of second blind vias formed therein, such that each of the second conductive blind vias is formed in the second blind via.
8. The circuit structure as described in claim 7, characterized in that, The planar dimension of the conductive bump is 0.3 to 0.5 times the bottom diameter of the second blind hole.