Display substrate and display device

Abstract

A display substrate and a display device relate to the technical field of display. The display substrate comprises a substrate, a first conductive layer, a semiconductor layer, a first insulating layer and a second conductive layer, wherein the first conductive layer, the semiconductor layer, the first insulating layer and the second conductive layer are stacked on one side of the substrate, and the first conductive layer is arranged close to the substrate; the first conducting layer comprises a data line and a plurality of first conducting structures, the semiconductor layer comprises a source electrode connecting region, a first conductor region, a channel region, a second conductor region and a drain electrode connecting region which are sequentially arranged in the first direction, and the second conducting layer comprises a plurality of grid electrodes, and a first switching pattern and a second switching pattern which are arranged on the two sides of the grid electrodes; the first insulating layer is provided with a first via hole and a second via hole, the data line and the source electrode connecting area are in lap joint with the first switching pattern through the first via hole, the first conductive structure and the drain electrode connecting area are in lap joint with the second switching pattern through the second via hole, the first switching pattern and the first conductive area are not overlapped, and the second switching pattern and the second conductive area are not overlapped. The second switching pattern is not overlapped with the second conductor area.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] Electronic paper usually adopts electrophoresis display (EPD) as a display panel. Electronic paper display not only has the advantages of comfortable reading, ultra-thin and light, bendable, and the like, similar to paper, but also can refresh the display content, and has lower power consumption than liquid crystal display. SUMMARY

[0003] The present disclosure provides a display substrate including a plurality of sub-pixels in a display area, the display substrate comprising:

[0004] a substrate, and a first conductive layer, a semiconductor layer, a first insulating layer and a second conductive layer sequentially stacked on one side of the substrate, the first conductive layer being disposed close to the substrate;

[0005] The first conductive layer includes a data line and a plurality of first conductive structures in different sub-pixels, the semiconductor layer includes a plurality of semiconductor patterns in different sub-pixels, the semiconductor pattern includes a source connection region, a first conductorization region, a channel region, a second conductorization region and a drain connection region arranged in sequence along a first direction, the second conductive layer includes a plurality of gate electrodes in different sub-pixels, and a first switching pattern and a second switching pattern are oppositely arranged on both sides of the gate electrode along the first direction; and

[0006] The first insulating layer is provided with a first via hole and a second via hole, the first via hole exposes a part of the data line, the source connection region and the first conductorization region, and the second via hole exposes a part of the first conductive structure, the drain connection region and the second conductorization region, the data line and the source connection region are respectively overlapped with the first switching pattern through the first via hole, and the first conductive structure and the drain connection region are respectively overlapped with the second switching pattern through the second via hole, in the orthographic projection on the substrate, the first switching pattern has no overlap with the first conductorization region, and the second switching pattern has no overlap with the second conductorization region.

[0007] In some embodiments, the semiconductor pattern further includes:

[0008] a third conductorization region connected between the first conductorization region and the channel region, the thickness of the first conductorization region being different from the thickness of the third conductorization region; and

[0009] A fourth conductive region is connected between the second conductive region and the channel region, and the thickness of the second conductive region is different from the thickness of the fourth conductive region.

[0010] In some embodiments, the thickness of the first conductive region is less than the thickness of the third conductive region, the thickness of the first conductive region is less than or equal to the thickness of the source connection region, and the thickness of the third conductive region is less than or equal to the thickness of the channel region; and

[0011] The thickness of the second conductive region is less than the thickness of the fourth conductive region, the thickness of the second conductive region is less than or equal to the thickness of the drain connection region, and the thickness of the fourth conductive region is less than or equal to the thickness of the channel region.

[0012] In some embodiments, the display substrate further comprises:

[0013] A second insulating layer is disposed on a side of the second conductive layer away from the substrate; and

[0014] A transparent conductive layer is disposed on a side of the second insulating layer away from the substrate, the transparent conductive layer comprises a plurality of second conductive structures located in different sub-pixels, the second conductive structures are connected to the second transfer patterns through third vias disposed on the second insulating layer, and the second conductive structures do not overlap with the projections of the gate electrodes on the substrate.

[0015] In some embodiments, the second conductive structures comprise a first sub-electrode, a second sub-electrode and a third sub-electrode, the second sub-electrode and the third sub-electrode are located on the same side of the first sub-electrode and are connected to the first sub-electrode, and in the projections of the second sub-electrode and the third sub-electrode on the substrate on the substrate, the second sub-electrode and the third sub-electrode are arranged on both sides of the gate electrode along the first direction; and

[0016] The gap width between the second sub-electrode and the third sub-electrode is substantially equal to the gap width between two adjacent second conductive structures.

[0017] In some embodiments, the display substrate further comprises:

[0018] A third conductive layer is disposed between the second insulating layer and the transparent conductive layer, the third conductive layer comprises a plurality of third conductive structures located in different sub-pixels, the surface of the third conductive structures away from the substrate directly contacts the surface of the second conductive structures close to the substrate, in the projections of the second conductive structures on the substrate, the second conductive structures cover the third conductive structures, and the third conductive structures cover the third vias and the second transfer patterns.

[0019] In some embodiments, in orthographic projection onto the substrate, the second conductive structure and the third conductive structure have different shapes, the second conductive structure covers the first transfer pattern, and the third conductive structure has no overlap with the first transfer pattern.

[0020] In some embodiments, the third conductive layer further comprises a first shielding pattern, the first shielding pattern is disposed apart from the third conductive structure, and an orthographic projection of the first shielding pattern onto the substrate covers an orthographic projection of the channel region onto the substrate.

[0021] The transparent conductive layer further comprises a protection pattern, the protection pattern is disposed apart from the second conductive structure, and an orthographic projection of the protection pattern onto the substrate covers an orthographic projection of the first shielding pattern onto the substrate.

[0022] In some embodiments, in orthographic projection onto the substrate, a gap width between two adjacent second conductive structures is greater than or equal to 5 microns and less than or equal to 15 microns.

[0023] In some embodiments, the sub-pixel further comprises:

[0024] A fourth conductive structure is located in the second conductive layer and / or the semiconductor layer, the fourth conductive structure has overlap with an orthographic projection of the first conductive structure onto the substrate, and fourth conductive structures of a plurality of sub-pixels arranged along the first direction and / or the second direction are interconnected, the second direction being an extension direction of the data line.

[0025] In some embodiments, the first conductive structure comprises:

[0026] A fourth sub-electrode and a fifth sub-electrode are interconnected, in orthographic projection onto the substrate, the fifth sub-electrode is located on a side of the fourth sub-electrode close to the gate electrode, a width of the fifth sub-electrode along the first direction is less than a width of the fourth sub-electrode along the first direction, the fifth sub-electrode has overlap with the second transfer pattern, and the fourth conductive structure covers a portion of the fifth sub-electrode and the fourth sub-electrode.

[0027] In some embodiments, the fourth conductive structure disposed in the same layer comprises:

[0028] a sixth sub-electrode and a seventh sub-electrode are connected to each other, in an orthogonal projection onto the substrate, the seventh sub-electrode is located on a side of the sixth sub-electrode close to the gate electrode, the seventh sub-electrode is located on a side of the second transfer pattern far from the gate electrode, a width of the seventh sub-electrode along the first direction is less than a width of the sixth sub-electrode along the first direction, the sixth sub-electrode completely covers the fourth sub-electrode, and the seventh sub-electrode covers a part of the fifth sub-electrode.

[0029] In some embodiments, the fourth conductive structure comprises:

[0030] a fifth conductive structure is located in the second conductive layer, the fifth conductive structure has an overlapping area with the first conductive structure in an orthogonal projection onto the substrate, fifth conductive structures of a plurality of sub-pixels arranged along the first direction are connected to each other, and a scan line is arranged between fifth conductive structures of two adjacent sub-pixels arranged along the second direction, the scan line is located in the second conductive layer and connected to the gate electrode.

[0031] In some embodiments, in an orthogonal projection onto the substrate, the fifth conductive structure has an overlapping area with the data line, and a width of the overlapping area along the second direction is less than or equal to a width of a non-overlapping area along the second direction.

[0032] In some embodiments, the fourth conductive structure further comprises:

[0033] a sixth conductive structure is located in the semiconductor layer, the sixth conductive structure has an overlapping area with the first conductive structure in an orthogonal projection onto the substrate, the sixth conductive structure is connected to the fifth conductive structure through a fourth via arranged on the first insulating layer, and in an orthogonal projection onto the substrate, an edge of the sixth conductive structure is located in a periphery of an edge of the fourth via; and

[0034] the data line is arranged between sixth conductive structures of two adjacent sub-pixels arranged along the first direction, and the scan line is arranged between sixth conductive structures of two adjacent sub-pixels arranged along the second direction.

[0035] In some embodiments, in an orthogonal projection onto the substrate, a distance between an edge of the sixth conductive structure and an edge of the fourth via is greater than or equal to half of a width of the data line along the first direction, and less than or equal to twice the width of the data line along the first direction.

[0036] In some embodiments, in an orthographic projection onto the substrate, an aperture of the fourth via along the first direction is larger than an aperture of the first via and the second via along the first direction, and an aperture of the fourth via along the second direction is larger than an aperture of the first via and the second via along the second direction.

[0037] In some embodiments, in an orthographic projection onto the substrate, the second conductive layer completely covers the first insulating layer, and a part of an edge of the first insulating layer is substantially aligned with an edge of the second conductive layer.

[0038] The present disclosure provides a display device, comprising: a counter substrate, an electrophoretic solution, and a display substrate as described in any one of the embodiments, the electrophoretic solution being located between the counter substrate and the display substrate, and the second conductive layer being located on a side of the substrate close to the electrophoretic solution.

[0039] The above description is only a summary of the technical solutions of the present disclosure. In order to enable one skilled in the art to better understand the technical means of the present disclosure, the contents of the specification can be implemented, and in order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific embodiments of the present disclosure are described below. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the related art, the drawings needed to be used in the embodiments or related art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings according to these drawings without creative labor. It should be noted that the proportions in the drawings are only for illustration and do not represent the actual proportions.

[0041] FIG. 1 A planar structure schematic diagram of one sub-pixel completed with the preparation of the first conductive layer in the first display substrate example is shown;

[0042] FIG. 2 An exemplary planar structure schematic diagram of two sub-pixels completed with the preparation of the first conductive layer in the first display substrate example is shown; FIG. 1 A cross-sectional structure schematic diagram of the display substrate along the AA' position is shown;

[0043] FIG. 3 A planar structure schematic diagram of one sub-pixel completed with the preparation of the first conductive layer in the first display substrate example is shown;

[0044] FIG. 4 A planar structure schematic diagram of one sub-pixel completed with the preparation of the first conductive layer in the first display substrate example is shown;

[0045] FIG. 5 An exemplary planar structure schematic diagram of two sub-pixels completed with the preparation of the first conductive layer in the first display substrate example is shown; FIG. 4A cross-sectional structure schematic view of the display substrate along the position of AA' is shown.

[0046] FIG. 6 A planar structure schematic view of two sub-pixels in which the semiconductor layer preparation is completed in the first display substrate example is shown.

[0047] FIG. 7 A planar structure schematic view of one sub-pixel in which the first insulating layer preparation is completed in the first display substrate example is shown.

[0048] FIG. 8 Exemplarily shown is FIG. 7 A cross-sectional structure schematic view of the display substrate along the position of AA' is shown.

[0049] FIG. 9 A planar structure schematic view of two sub-pixels in which the first insulating layer preparation is completed in the first display substrate example is shown.

[0050] FIG. 10 A planar structure schematic view of one sub-pixel in which the second conductive layer preparation is completed in the first display substrate example is shown.

[0051] FIG. 11 Exemplarily shown is FIG. 10 A cross-sectional structure schematic view of the display substrate along the position of AA' is shown.

[0052] FIG. 12 A planar structure schematic view of two sub-pixels in which the second conductive layer preparation is completed in the first display substrate example is shown.

[0053] FIG. 13 A planar structure schematic view of one sub-pixel in which the second insulating layer preparation is completed in the first display substrate example is shown.

[0054] FIG. 14 Exemplarily shown is FIG. 13 A cross-sectional structure schematic view of the display substrate along the position of AA' is shown.

[0055] FIG. 15 A planar structure schematic view of two sub-pixels in which the second insulating layer preparation is completed in the first display substrate example is shown.

[0056] FIG. 16 A planar structure schematic view of one sub-pixel in which the third conductive layer preparation is completed in the first display substrate example is shown.

[0057] FIG. 17 Exemplarily shown is FIG. 16 A cross-sectional structure schematic view of the display substrate along the position of AA' is shown.

[0058] FIG. 18A planar structure schematic diagram of two sub-pixels of the first display substrate example is shown, which is completed with the preparation of the third conductive layer;

[0059] FIG. 19 A planar structure schematic diagram of one sub-pixel of the first display substrate example is shown, which is completed with the preparation of the transparent conductive layer;

[0060] FIG. 20 Exemplarily shown is FIG. 19 A cross-sectional structure schematic diagram of the display substrate shown in 22 along the AA' position is shown;

[0061] FIG. 21 A planar structure schematic diagram of two sub-pixels of the first display substrate example is shown, which is completed with the preparation of the transparent conductive layer;

[0062] FIG. 22 A planar structure schematic diagram of one sub-pixel of the second display substrate example is shown, which is completed with the preparation of the first conductive layer;

[0063] FIG. 23 Exemplarily shown is

[0064] FIG. 24 A planar structure schematic diagram of two sub-pixels of the second display substrate example is shown, which is completed with the preparation of the first conductive layer;

[0065] FIG. 25 A planar structure schematic diagram of one sub-pixel of the second display substrate example is shown, which is completed with the preparation of the semiconductor layer;

[0066] FIG. 26 Exemplarily shown is FIG. 25 A cross-sectional structure schematic diagram of the display substrate shown in 22 along the AA' position is shown;

[0067] FIG. 27 A planar structure schematic diagram of two sub-pixels of the second display substrate example is shown, which is completed with the preparation of the semiconductor layer;

[0068] FIG. 28 A planar structure schematic diagram of one sub-pixel of the second display substrate example is shown, which is completed with the preparation of the first insulating layer;

[0069] FIG. 29 Exemplarily shown is FIG. 28 A cross-sectional structure schematic diagram of the display substrate shown in 22 along the AA' position is shown;

[0070] FIG. 30 A planar structure schematic diagram of two sub-pixels of the second display substrate example is shown, which is completed with the preparation of the first insulating layer;

[0071] FIG. 31A planar structure schematic diagram of one sub-pixel in which the second conductive layer is prepared in the second display substrate example is shown;

[0072] FIG. 32 A planar structure schematic diagram of one sub-pixel in which the second conductive layer is prepared in the second display substrate example is shown; FIG. 31 A cross-sectional structure schematic diagram of the display substrate along AA' position is shown;

[0073] FIG. 33 A planar structure schematic diagram of two sub-pixels in which the second conductive layer is prepared in the second display substrate example is shown;

[0074] FIG. 34 A planar structure schematic diagram of one sub-pixel in which the second insulating layer is prepared in the second display substrate example is shown;

[0075] FIG. 35 A planar structure schematic diagram of one sub-pixel in which the second insulating layer is prepared in the second display substrate example is shown; FIG. 34 A cross-sectional structure schematic diagram of the display substrate along AA' position is shown;

[0076] FIG. 36 A planar structure schematic diagram of two sub-pixels in which the second insulating layer is prepared in the second display substrate example is shown;

[0077] FIG. 37 A planar structure schematic diagram of one sub-pixel in which the transparent conductive layer is prepared in the second display substrate example is shown;

[0078] FIG. 38 A planar structure schematic diagram of one sub-pixel in which the transparent conductive layer is prepared in the second display substrate example is shown; FIG. 37 A cross-sectional structure schematic diagram of the display substrate along AA' position is shown;

[0079] FIG. 39 A planar structure schematic diagram of two sub-pixels in which the transparent conductive layer is prepared in the second display substrate example is shown;

[0080] FIG. 40 A planar structure schematic diagram of one sub-pixel in which the first conductive layer is prepared in the third display substrate example is shown;

[0081] FIG. 41 A cross-sectional structure schematic diagram of the display substrate along AA' position is shown;

[0082] FIG. 42 A planar structure schematic diagram of two sub-pixels in which the first conductive layer is prepared in the third display substrate example is shown;

[0083] FIG. 43 A planar structure schematic diagram of one sub-pixel in which the semiconductor layer is prepared in the third display substrate example is shown;

[0084] FIG. 44 A planar structure schematic diagram of one sub-pixel in which the semiconductor layer is prepared in the third display substrate example is shown;FIG. 43 A cross-sectional structure schematic view of the display substrate along the position of AA' is shown.

[0085] FIG. 45 A planar structure schematic view of two sub-pixels in which the semiconductor layer preparation is completed in the third display substrate example is shown.

[0086] FIG. 46 A planar structure schematic view of one sub-pixel in which the first insulating layer preparation is completed in the third display substrate example is shown.

[0087] FIG. 47 Exemplarily shown is FIG. 46 A cross-sectional structure schematic view of the display substrate along the position of AA' is shown.

[0088] FIG. 48 A planar structure schematic view of two sub-pixels in which the first insulating layer preparation is completed in the third display substrate example is shown.

[0089] FIG. 49 A planar structure schematic view of one sub-pixel in which the second conductive layer preparation is completed in the third display substrate example is shown.

[0090] FIG. 50 Exemplarily shown is FIG. 49 A cross-sectional structure schematic view of the display substrate along the position of AA' is shown.

[0091] FIG. 51 A planar structure schematic view of two sub-pixels in which the second conductive layer preparation is completed in the third display substrate example is shown.

[0092] FIG. 52 A planar structure schematic view of one sub-pixel in which the second insulating layer preparation is completed in the third display substrate example is shown.

[0093] FIG. 53 Exemplarily shown is FIG. 52 A cross-sectional structure schematic view of the display substrate along the position of AA' is shown.

[0094] FIG. 54 A planar structure schematic view of two sub-pixels in which the second insulating layer preparation is completed in the third display substrate example is shown.

[0095] FIG. 55 A planar structure schematic view of one sub-pixel in which the transparent conductive layer preparation is completed in the third display substrate example is shown.

[0096] FIG. 56 Exemplarily shown is FIG. 55 A cross-sectional structure schematic view of the display substrate along the position of AA' is shown.

[0097] FIG. 57A planar structure schematic diagram of two sub-pixels in a third display substrate example is shown, which is completed transparent conductive layer preparation;

[0098] FIG. 58 A column chart showing the channel region electric field intensity as a function of the first conductorization region doping concentration is shown.

[0099] FIG. 59 A cross-sectional structure schematic diagram of a display device is exemplarily shown;

[0100] FIG. 60 A connection structure schematic diagram of a display device is exemplarily shown. DETAILED DESCRIPTION

[0101] To make the objects, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present disclosure.

[0102] In the related art, electronic paper mainly realizes full-color display in the following two ways: the first is color printing electronic paper technology, which is electronic paper matched with color filter, and converts black and white electronic paper into full-color electronic paper by using the principle of color mixing; the second is color electronic paper technology, which is composed of 4 colors (such as yellow, cyan, magenta and white) of ink particles, and the corresponding color ink particles are pushed to the display side by applying an electric field using the principle of positive and negative attraction, and different color particles are mixed to present colorful colors.

[0103] In order to drive electronic paper to perform full-color display, a higher driving voltage needs to be provided, for example, VGH≥28V, VGL≤-28V. However, the highest use voltage of the display substrate in the related art cannot meet the driving requirements of color electronic paper, and therefore, there is an urgent need to develop a high-voltage display substrate.

[0104] The present disclosure provides a display substrate, as shown in FIG. 60 The display substrate includes a display area AA and a non-display area NA surrounding the display area AA, the display area AA includes a plurality of sub-pixels PX, and the sub-pixel PX includes a thin film transistor.

[0105] As shown in FIG. 20 The display substrate includes a substrate 10, and a first conductive layer M1, a semiconductor layer ACT, a first insulating layer GI, and a second conductive layer M2 which are sequentially stacked on one side of the substrate 10, and the first conductive layer M1 is arranged close to the substrate 10.

[0106] As FIGS. 19-21 shown, the first conductive layer M1 includes the data line DL and a plurality of first conductive structures EP1 located at different sub-pixels PX, the semiconductor layer ACT includes a plurality of semiconductor patterns located at different sub-pixels PX, the semiconductor pattern includes, in sequence along the first direction f1, the source connection region S, the first conductorization region DT1, the channel region CH, the second conductorization region DT2 and the drain connection region D, the second conductive layer M2 includes a plurality of gate electrodes G located at different sub-pixels PX, and the first transfer pattern ZJ1 and the second transfer pattern ZJ2 are oppositely arranged on both sides of the gate electrode G along the first direction f1.

[0107] Wherein, the first insulating layer GI is provided with a first via H1 and a second via H2, the first via H1 exposes a part of the data line DL, the source connection region S and the first conductorization region DT1, the second via H2 exposes a part of the first conductive structure EP1, the drain connection region D and the second conductorization region DT2, the data line DL and the source connection region S are respectively connected to the first transfer pattern ZJ1 through the first via H1, the first conductive structure EP1 and the drain connection region D are respectively connected to the second transfer pattern ZJ2 through the second via H2, and in the orthographic projection on the substrate 10, the first transfer pattern ZJ1 has no overlap with the first conductorization region DT1, and the second transfer pattern ZJ2 has no overlap with the second conductorization region DT2.

[0108] As FIGS. 19-21 shown, the first conductorization region DT1 is exposed at the position of the first via H1, and the first transfer pattern ZJ1 does not cover the first conductorization region DT1, that is, the first transfer pattern ZJ1 realizes the communication of the data line DL and the source connection region S by half covering the first via H1. The second conductorization region DT2 is exposed at the position of the second via H2, and the second transfer pattern ZJ2 does not cover the second conductorization region DT2, that is, the second transfer pattern ZJ2 realizes the communication of the first conductive structure EP1 and the drain connection region D by half covering the second via H2.

[0109] The display substrate provided by the present disclosure can adjust the doping concentration of the first conductorization region DT1 exposed at the position of the first via H1 and the second conductorization region DT2 exposed at the position of the second via H2, so as to adjust the resistance of the first via H1 and the second via H2, and further adjust the voltage division of the first via H1 and the second via H2, thereby facilitating the improvement of the voltage resistance of the thin film transistor.

[0110] Referring to FIG. 58 a column chart showing the change of the electric field intensity of the channel region CH with the doping concentration of the first conductorization region DT1. As FIG. 58As shown, as the first conductive region DT1 doping concentration decreases, the electric field intensity of the channel region CH decreases. This is because as the first conductive region DT1 doping concentration decreases, the resistance and voltage division of the first via H1 increase, thus the electric field intensity of the channel region CH decreases, and in turn, the voltage resistance capability of the thin film transistor is improved.

[0111] In the present disclosure, a thin film transistor refers to an element including at least three terminals of a gate G, a drain, and a source. The thin film transistor has a channel region CH between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region CH, and the source. In the present disclosure, the channel region CH refers to a region through which current mainly flows, the source is connected to the source connection region S, and the drain is connected to the drain connection region D.

[0112] In the present disclosure, in the case of using a thin film transistor with opposite polarity or in the case of changing the current direction in the circuit operation, the functions of the "source" and the "drain" are sometimes exchanged with each other. Therefore, in the present disclosure, the "source" and the "drain" can be exchanged with each other.

[0113] Exemplarily, the material of the semiconductor layer ACT includes an oxide semiconductor material such as IGZO, and can also include amorphous silicon or low-temperature polysilicon, and the present disclosure does not limit this.

[0114] In some embodiments, the channel region CH of the thin film transistor includes a semiconductor material M1OaNb, where M1 is a single metal or a combination of multiple metals, a>0, and b≥0, O represents an oxygen element, and N represents a nitrogen element, that is, the semiconductor material is a metal oxide material or a metal nitride oxide material. Suitable metal oxide materials include, but are not limited to, one or more of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), In-free OS, rare earth doped oxide (Ln-OS, such as rare earth element doped IGZO / IZO), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O. The material of the channel CH can be in an amorphous, partially crystalline, single crystalline, or polycrystalline state, and can also be a single layer or a multi-layer structure.

[0115] Suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or a combination thereof. In one example, the material of the channel region CH includes indium gallium zinc oxide (IGZO).

[0116] As shown in FIG. 1, the first transfer pattern ZJ1 overlaps with the data line DL and the source connection region S, and the second transfer pattern ZJ2 overlaps with the first conductive structure EP1 and the drain connection region D. FIGS. 19-21 As shown in FIG. 1, the first transfer pattern ZJ1 overlaps with the data line DL and the source connection region S, and the second transfer pattern ZJ2 overlaps with the first conductive structure EP1 and the drain connection region D.

[0117] As shown in FIG. 1, the first transfer pattern ZJ1 overlaps with the data line DL and the source connection region S, and the second transfer pattern ZJ2 overlaps with the first conductive structure EP1 and the drain connection region D. FIGS. 19-21 As shown in FIG. 1, the first transfer pattern ZJ1 overlaps with the data line DL and the source connection region S, and the second transfer pattern ZJ2 overlaps with the first conductive structure EP1 and the drain connection region D.

[0118] As shown in FIG. 1, the first transfer pattern ZJ1 overlaps with the data line DL and the source connection region S, and the second transfer pattern ZJ2 overlaps with the first conductive structure EP1 and the drain connection region D. FIG. 1 As shown in FIG. 1, the first transfer pattern ZJ1 overlaps with the data line DL and the source connection region S, and the second transfer pattern ZJ2 overlaps with the first conductive structure EP1 and the drain connection region D. FIG. 19 As shown in FIG. 1, the first transfer pattern ZJ1 overlaps with the data line DL and the source connection region S, and the second transfer pattern ZJ2 overlaps with the first conductive structure EP1 and the drain connection region D.

[0119] As shown in FIG. 1, the first transfer pattern ZJ1 overlaps with the data line DL and the source connection region S, and the second transfer pattern ZJ2 overlaps with the first conductive structure EP1 and the drain connection region D.

[0120] As shown in FIG. 1, the first transfer pattern ZJ1 overlaps with the data line DL and the source connection region S, and the second transfer pattern ZJ2 overlaps with the first conductive structure EP1 and the drain connection region D.

[0121] As shown in FIG. 1, the first transfer pattern ZJ1 overlaps with the data line DL and the source connection region S, and the second transfer pattern ZJ2 overlaps with the first conductive structure EP1 and the drain connection region D. FIG. 20 As shown in FIG. 1, the first transfer pattern ZJ1 overlaps with the data line DL and the source connection region S, and the second transfer pattern ZJ2 overlaps with the first conductive structure EP1 and the drain connection region D.

[0122] Exemplarily, the first via hole H1 and the second via hole H2 can be formed synchronously by using the same process, in which case, the thickness of the drain connection region D is substantially equal to the thickness of the source connection region S, and the thickness of the first conductorized region DT1 is substantially equal to the thickness of the second conductorized region DT2.

[0123] In some embodiments, as shown in FIG. 1, the semiconductor pattern further comprises: a third conductorized region DT3 connected between the first conductorized region DT1 and the channel region CH; and a fourth conductorized region DT4 connected between the second conductorized region DT2 and the channel region CH. FIGS. 19-21

[0124] Exemplarily, the thickness of the first conductorized region DT1 is different from the thickness of the third conductorized region DT3, and the thickness of the second conductorized region DT2 is different from the thickness of the fourth conductorized region DT4.

[0125] Exemplarily, after the second conductive layer M2 is formed, the first insulating layer GI can be etched for the second time using the second conductive layer M2 as a mask, and then the semiconductor material in the exposed regions (such as the first conductorized region DT1, the second conductorized region DT2, the third conductorized region DT3, and the fourth conductorized region DT4) in the semiconductor layer ACT can be conductorized using a self-alignment process with the second conductive layer M2 as a mask. The conductorization process can use a dry etching device or an ion implantation device to inject plasma (such as plasma containing at least one of helium, oxygen, nitrogen, chlorine, hydrogen, boron, and phosphorus elements) into the semiconductor material, or use an ion doping process to dope any one or more of the above elements into the semiconductor material to realize conductorization. In this way, the semiconductor material can be conductorized synchronously with the second etching of the first insulating layer GI, thereby simplifying the process.

[0126] In the case of etching the first insulating layer GI for the second time, as shown in FIG. 1, the third conductorized region DT3 and the first insulating layer GI have no overlap in the orthographic projection on the substrate 10, the fourth conductorized region DT4 and the first insulating layer GI have no overlap in the orthographic projection on the substrate 10, and since the first conductorized region DT1 and the second conductorized region DT2 are etched twice, the source connection region S, the drain connection region D, the third conductorized region DT3, and the fourth conductorized region DT4 are etched once, and the channel region CH is not etched, therefore, the thickness of the first conductorized region DT1 is less than the thickness of the source connection region S and the third conductorized region DT3, the thickness of the second conductorized region DT2 is less than the thickness of the drain connection region D and the fourth conductorized region DT4, the thickness of the source connection region S and the third conductorized region DT3 is less than the thickness of the channel region CH, and the thickness of the drain connection region D and the fourth conductorized region DT4 is less than the thickness of the channel region CH. FIGS. 19-21

[0127] ​​Exemplarily, after the second conductive layer M2 is formed, the first insulating layer GI can also not be subjected to secondary etching, and the semiconductor material in the exposed regions (such as the first conductorization region DT1, the second conductorization region DT2, the third conductorization region DT3, and the fourth conductorization region DT4) in the semiconductor layer ACT can be directly conductorized by using the second conductive layer M2 as a mask plate and adopting a self-alignment process. The conductorization process can for example adopt a dry etching device or an ion implantation device to inject plasma (such as plasma containing at least one of helium, oxygen, nitrogen, chlorine, hydrogen, boron, and phosphorus elements) into the semiconductor material, or can adopt an ion doping process to dope any one or more of the above elements into the semiconductor material to realize conductorization.

[0128] Exemplarily, without secondary etching of the first insulating layer GI, the first insulating layer GI covers the surfaces of the third conductorization region DT3 and the fourth conductorization region DT4 away from the substrate 10, and since the source connection region S, the drain connection region D, the first conductorization region DT1, and the second conductorization region DT2 are all subjected to primary over-etching, the third conductorization region DT3, the fourth conductorization region DT4, and the channel region CH are not over-etched, thus the thickness of the first conductorization region DT1 is substantially equal to the thickness of the source connection region S, the thickness of the second conductorization region DT2 is substantially equal to the thickness of the drain connection region DS, the thickness of the source connection region S and the first conductorization region DT1 is less than the thickness of the third conductorization region DT3, the thickness of the drain connection region DS and the second conductorization region DT2 is less than the thickness of the fourth conductorization region DT4, and the thickness of the third conductorization region DT3 and the fourth conductorization region DT4 is substantially equal to the thickness of the channel region CH.

[0129] Exemplarily, the thickness difference between the channel region CH and the source connection region S is greater than or equal to 5 nm and less than or equal to 15 nm. The thickness difference between the channel region CH and the drain connection region D is greater than or equal to 5 nm and less than or equal to 15 nm. The thickness difference between the channel region CH and the first conductorization region DT1 is greater than or equal to 10 nm and less than or equal to 30 nm. The thickness difference between the channel region CH and the second conductorization region DT2 is greater than or equal to 10 nm and less than or equal to 30 nm. The thickness difference between the channel region CH and the third conductorization region DT3 is greater than or equal to 2 nm and less than or equal to 10 nm. The thickness difference between the channel region CH and the fourth conductorization region DT4 is greater than or equal to 2 nm and less than or equal to 10 nm. Exemplarily, the first conductive structures EP1 of different sub-pixels PX are arranged to be separated from each other. For example, in the orthographic projection on the substrate 10, a data line DL is arranged between two first conductive structures EP1 adjacent in the first direction f1, and a scan line GL is arranged between two first conductive structures EP1 adjacent in the second direction f2, and the first conductive structures EP1 do not overlap with the data line DL and the scan line GL.

[0130] Exemplarily, asFIG. 1 and FIG. 19 As shown in FIG. 1A, the first conductive structure EP1 includes a fourth sub-electrode 114 and a fifth sub-electrode 115 connected to each other. As shown in FIG. 1B, in the orthographic projection on the substrate 10, the fifth sub-electrode 115 is located on the side of the fourth sub-electrode 114 close to the gate G, the fifth sub-electrode 115 is located on the side of the gate G away from the first transfer pattern ZJ1, the width of the fifth sub-electrode 115 along the first direction f1 is less than the width of the fourth sub-electrode 114 along the first direction f1, and the fifth sub-electrode 115 overlaps the second transfer pattern ZJ2. The edges of the fourth sub-electrode 114 and the fifth sub-electrode 115 away from the channel region CH are substantially aligned. FIGS. 19-21 As shown in FIG. 1A, the first conductive structure EP1 includes a fourth sub-electrode 114 and a fifth sub-electrode 115 connected to each other. As shown in FIG. 1B, in the orthographic projection on the substrate 10, the fifth sub-electrode 115 is located on the side of the fourth sub-electrode 114 close to the gate G, the fifth sub-electrode 115 is located on the side of the gate G away from the first transfer pattern ZJ1, the width of the fifth sub-electrode 115 along the first direction f1 is less than the width of the fourth sub-electrode 114 along the first direction f1, and the fifth sub-electrode 115 overlaps the second transfer pattern ZJ2. The edges of the fourth sub-electrode 114 and the fifth sub-electrode 115 away from the channel region CH are substantially aligned.

[0131] As shown in FIG. 1A, the first conductive structure EP1 includes a fourth sub-electrode 114 and a fifth sub-electrode 115 connected to each other. As shown in FIG. 1B, in the orthographic projection on the substrate 10, the fifth sub-electrode 115 is located on the side of the fourth sub-electrode 114 close to the gate G, the fifth sub-electrode 115 is located on the side of the gate G away from the first transfer pattern ZJ1, the width of the fifth sub-electrode 115 along the first direction f1 is less than the width of the fourth sub-electrode 114 along the first direction f1, and the fifth sub-electrode 115 overlaps the second transfer pattern ZJ2. The edges of the fourth sub-electrode 114 and the fifth sub-electrode 115 away from the channel region CH are substantially aligned.

[0132] As shown in FIG. 1A, the first conductive structure EP1 includes a fourth sub-electrode 114 and a fifth sub-electrode 115 connected to each other. As shown in FIG. 1B, in the orthographic projection on the substrate 10, the fifth sub-electrode 115 is located on the side of the fourth sub-electrode 114 close to the gate G, the fifth sub-electrode 115 is located on the side of the gate G away from the first transfer pattern ZJ1, the width of the fifth sub-electrode 115 along the first direction f1 is less than the width of the fourth sub-electrode 114 along the first direction f1, and the fifth sub-electrode 115 overlaps the second transfer pattern ZJ2. The edges of the fourth sub-electrode 114 and the fifth sub-electrode 115 away from the channel region CH are substantially aligned. FIGS. 19-21 As shown in FIG. 1A, the first conductive structure EP1 includes a fourth sub-electrode 114 and a fifth sub-electrode 115 connected to each other. As shown in FIG. 1B, in the orthographic projection on the substrate 10, the fifth sub-electrode 115 is located on the side of the fourth sub-electrode 114 close to the gate G, the fifth sub-electrode 115 is located on the side of the gate G away from the first transfer pattern ZJ1, the width of the fifth sub-electrode 115 along the first direction f1 is less than the width of the fourth sub-electrode 114 along the first direction f1, and the fifth sub-electrode 115 overlaps the second transfer pattern ZJ2. The edges of the fourth sub-electrode 114 and the fifth sub-electrode 115 away from the channel region CH are substantially aligned.

[0133] As shown in FIG. 1A, the first conductive structure EP1 includes a fourth sub-electrode 114 and a fifth sub-electrode 115 connected to each other. As shown in FIG. 1B, in the orthographic projection on the substrate 10, the fifth sub-electrode 115 is located on the side of the fourth sub-electrode 114 close to the gate G, the fifth sub-electrode 115 is located on the side of the gate G away from the first transfer pattern ZJ1, the width of the fifth sub-electrode 115 along the first direction f1 is less than the width of the fourth sub-electrode 114 along the first direction f1, and the fifth sub-electrode 115 overlaps the second transfer pattern ZJ2. The edges of the fourth sub-electrode 114 and the fifth sub-electrode 115 away from the channel region CH are substantially aligned.

[0134] As shown in FIG. 1A, the first conductive structure EP1 includes a fourth sub-electrode 114 and a fifth sub-electrode 115 connected to each other. As shown in FIG. 1B, in the orthographic projection on the substrate 10, the fifth sub-electrode 115 is located on the side of the fourth sub-electrode 114 close to the gate G, the fifth sub-electrode 115 is located on the side of the gate G away from the first transfer pattern ZJ1, the width of the fifth sub-electrode 115 along the first direction f1 is less than the width of the fourth sub-electrode 114 along the first direction f1, and the fifth sub-electrode 115 overlaps the second transfer pattern ZJ2. The edges of the fourth sub-electrode 114 and the fifth sub-electrode 115 away from the channel region CH are substantially aligned.

[0135] To avoid signal interference between the second conductive structure EP2 and the gate G, exemplary, the second conductive structure EP2 has no overlap with the gate G in the orthographic projection on the substrate 10. This can reduce the coupling capacitance formed by the second conductive structure EP2 and the gate G, and in turn reduce signal interference.

[0136] Exemplary, as shown in FIG. 1, the second conductive structure EP2 includes a first sub-electrode 111, a second sub-electrode 112 and a third sub-electrode 113. The second sub-electrode 112 and the third sub-electrode 113 are located on the same side of the first sub-electrode 111 and are connected to the first sub-electrode 111 respectively. In the orthographic projection on the substrate 10, the second sub-electrode 112 and the third sub-electrode 113 are oppositely arranged on both sides of the gate G along the first direction f1. FIGS. 19-21

[0137] Exemplary, the gap width between the second sub-electrode 112 and the third sub-electrode 113 is substantially equal to the gap width between two adjacent second conductive structures EP2 (as shown as w1 in FIG. 1). FIG. 21

[0138] To ensure that the second conductive structure EP2 has no overlap with the gate G in the orthographic projection on the substrate 10, the gap width between the second sub-electrode 112 and the third sub-electrode 113 is greater than or equal to the width of the gate G along the first direction f1.

[0139] Exemplary, in the orthographic projection on the substrate 10, the second sub-electrode 112 covers the first transfer pattern ZJ1, and the third sub-electrode 113 covers the second transfer pattern ZJ2. The width of the second sub-electrode 112 along the first direction f1 is less than the width of the first sub-electrode 111 along the first direction f1. The width of the third sub-electrode 113 along the first direction f1 is less than the width of the first sub-electrode 111 along the first direction f1. The width of the second sub-electrode 112 along the first direction f1 can be less than or equal to the width of the third sub-electrode 113 along the first direction f1.

[0140] Exemplary, in the orthographic projection on the substrate 10, the edge of the first sub-electrode 111 away from the second sub-electrode 112 is substantially aligned with the edge of the third sub-electrode 113 away from the second sub-electrode 112. The edge of the first sub-electrode 111 away from the third sub-electrode 113 is substantially aligned with the edge of the second sub-electrode 112 away from the first sub-electrode 111. The edge of the second sub-electrode 112 away from the first sub-electrode 111 is substantially aligned with the edge of the third sub-electrode 113 away from the first sub-electrode 111.

[0141] In some embodiments, as shown in FIG. 2, the second conductive structure EP2 includes a first sub-electrode 211, a second sub-electrode 212 and a third sub-electrode 213. The second sub-electrode 212 and the third sub-electrode 213 are located on the same side of the first sub-electrode 211 and are connected to the first sub-electrode 211 respectively. In the orthographic projection on the substrate 10, the second sub-electrode 212 and the third sub-electrode 213 are oppositely arranged on both sides of the gate G along the first direction f1. FIGS. 19-21 ​​As shown, the display substrate further comprises: a third conductive layer M3 disposed between the second insulating layer PVX and the transparent conductive layer TD, the third conductive layer M3 comprises a plurality of third conductive structures EP3 located at different sub-pixels PX, the third conductive structures EP3 directly contact the second conductive structures EP2 away from the surface of the substrate 10, in the orthographic projection on the substrate 10, the second conductive structures EP2 cover the third conductive structures EP3, and the third conductive structures EP3 cover the third via holes H3 and the second transfer patterns ZJ2.

[0142] Exemplarily, the third conductive structures EP3 of different sub-pixels PX are arranged separately from each other. For example, in the orthographic projection on the substrate 10, a data line DL is arranged between two third conductive structures EP3 adjacent in the first direction f1, and a scan line GL is arranged between two third conductive structures EP3 adjacent in the second direction f2, the third conductive structures EP3 do not overlap the scan line GL, and the third conductive structures EP3 do not overlap or partially overlap the data line DL.

[0143] As shown in FIGS. 19-21 , the transparent conductive layer TD and the third conductive layer M3 are two film layers arranged adjacent in the normal direction of the substrate 10. By arranging the third conductive structures EP3 directly contacting the second conductive structures EP2, in the case that the conductivity of the third conductive layer M3 is greater than that of the transparent conductive layer TD, the impedance and contact resistance of the pixel electrode can be reduced, which is conducive to improving the display uniformity. In addition, by arranging the transparent conductive layer TD covering the third conductive layer M3, the transparent conductive layer TD can protect the third conductive layer M3, thereby improving the stability of the display substrate.

[0144] It should be noted that the third conductive layer M3 is not necessarily arranged, and in the case that the third conductive layer M3 is not arranged, one mask plate process can be reduced, thereby simplifying the process.

[0145] Exemplarily, as shown in FIGS. 19-21 , in the orthographic projection on the substrate 10, the shapes of the second conductive structures EP2 and the third conductive structures EP3 are different, the second conductive structures EP2 cover the first transfer patterns ZJ1, and the third conductive structures EP3 do not overlap the first transfer patterns ZJ1.

[0146] As shown in FIGS. 19-21 , the orthographic projection shape of the second conductive structures EP2 on the substrate 10 is a concave shape with a notch facing the scan line GL, wherein the notch of the concave shape is centrally arranged in the first direction f1 or arranged close to the data line DL (as shown in FIG. 19 ). While the orthographic projection shape of the third conductive structures EP3 on the substrate 10 is an L-shaped structure with an opening facing the channel region CH.

[0147] Exemplarily, as shown inFIGS. 16-21 As shown, the third conductive structure EP3 includes: the eighth sub-electrode 118 and the ninth sub-electrode 119 connected to each other, in the orthographic projection on the substrate 10, the ninth sub-electrode 119 is located on the side of the eighth sub-electrode 118 close to the gate G, the ninth sub-electrode 119 is located on the side of the gate G away from the first transfer pattern ZJ1, the width of the ninth sub-electrode 119 along the first direction f1 is less than the width of the eighth sub-electrode 118 along the first direction f1, and the ninth sub-electrode 119 overlaps the second transfer pattern ZJ2. Among them, the edges of the eighth sub-electrode 118 and the ninth sub-electrode 119 away from the channel region CH are roughly aligned.

[0148] In specific implementation, in the orthographic projection on the substrate 10, the shapes of the second conductive structure EP2 and the third conductive structure EP3 can also be the same, and the third conductive structure EP3 is roughly arranged in the middle of the region of the second conductive structure EP2, and the second conductive structure EP2 completely covers the third conductive structure EP3.

[0149] In some embodiments, as FIGS. 16-18 As shown, the third conductive layer M3 further includes a first shielding pattern ZD1, the first shielding pattern ZD1 is arranged spaced apart from the third conductive structure EP3, and the orthographic projection of the first shielding pattern ZD1 on the substrate 10 covers the orthographic projection of the channel region CH on the substrate 10.

[0150] By arranging the first shielding pattern ZD1 on the side of the channel region CH away from the substrate 10, it can prevent the material of the channel region CH from being affected by light to affect the characteristics of the thin film transistor, and improve the stability of the display substrate.

[0151] In order to protect the first shielding pattern ZD1, exemplarily, as FIGS. 19-21 As shown, the transparent conductive layer TD further includes a protection pattern PT, the protection pattern PT is arranged spaced apart from the second conductive structure EP2, and the orthographic projection of the protection pattern PT on the substrate 10 covers the orthographic projection of the first shielding pattern ZD1 on the substrate 10.

[0152] As FIGS. 19-21 As shown, the protection pattern PT is located between the second sub-electrode 112 and the third sub-electrode 113, the gap width between the protection pattern PT and the second sub-electrode 112 is for example 3 microns, and the gap width between the protection pattern PT and the third sub-electrode 113 is for example 3 microns.

[0153] Exemplarily, as FIG. 21As shown, the gap width w1 between two adjacent second conductive structures EP2 is greater than or equal to 5 microns and less than or equal to 15 microns, for example 10 microns. Such a gap width can ensure that the two adjacent second conductive structures EP2 do not short circuit, and on the other hand, can maximize the area of the second conductive structure EP2, which is conducive to improving display uniformity.

[0154] In some embodiments, as shown in FIG. 1, the sub-pixel PX further includes a fourth conductive structure EC located in the second conductive layer M2 and / or the semiconductor layer ACT, the fourth conductive structure EC overlaps the orthographic projection of the first conductive structure EP1 on the substrate 10, and the fourth conductive structures EC of a plurality of sub-pixels PX arranged along the first direction f1 and / or the second direction f2 are interconnected. FIGS. 19-21 As shown, the sub-pixel PX further includes a fourth conductive structure EC located in the second conductive layer M2 and / or the semiconductor layer ACT, the fourth conductive structure EC overlaps the orthographic projection of the first conductive structure EP1 on the substrate 10, and the fourth conductive structures EC of a plurality of sub-pixels PX arranged along the first direction f1 and / or the second direction f2 are interconnected.

[0155] Exemplarily, the fourth conductive structure EC also overlaps the orthographic projection of the second conductive structure EP2 on the substrate 10.

[0156] In some embodiments, as shown in FIG. 1, the fourth conductive structure EC and the first conductive structure EP1 constitute two plates of a first storage capacitor Cst1, and the fourth conductive structure EC and the second conductive structure EP2 constitute two plates of a second storage capacitor Cst2.

[0157] By arranging the fourth conductive structure EC between the first conductive structure EP1 and the second conductive structure EP2, a sandwich-structured pixel capacitor is formed, which can reduce the number of vias in the display area AA, so that the space saved can be used to expand the area of the pixel electrode and the fourth conductive structure EC, thereby increasing the storage capacitance, which is conducive to improving the pixel density and can more flexibly adjust the size of the storage capacitance according to actual needs. In addition, since the number of vias is reduced, the number of mask plates can be reduced, the process can be simplified, and the cost can be reduced.

[0158] In some embodiments, as shown in FIG. 1, the sub-pixel PX further includes a fourth conductive structure EC located in the second conductive layer M2 and / or the semiconductor layer ACT, the fourth conductive structure EC overlaps the orthographic projection of the first conductive structure EP1 on the substrate 10, and the fourth conductive structures EC of a plurality of sub-pixels PX arranged along the first direction f1 and / or the second direction f2 are interconnected. FIGS. 19-21 As shown, the fourth conductive structure EC covers a part of the fifth sub-electrode 115 and the fourth sub-electrode 114.

[0159] In some embodiments, as shown in FIG. 1, the sub-pixel PX further includes a fourth conductive structure EC located in the second conductive layer M2 and / or the semiconductor layer ACT, the fourth conductive structure EC overlaps the orthographic projection of the first conductive structure EP1 on the substrate 10, and the fourth conductive structures EC of a plurality of sub-pixels PX arranged along the first direction f1 and / or the second direction f2 are interconnected. FIG. 4 and FIG. 10 Exemplarily, the fourth conductive structure EC includes a sixth sub-electrode 116 and a seventh sub-electrode 117 connected to each other, the seventh sub-electrode 117 is located on the side of the sixth sub-electrode 116 close to the gate G in the orthographic projection on the substrate 10, the seventh sub-electrode 117 is located on the side of the second transfer pattern ZJ2 away from the gate G, and the width of the seventh sub-electrode 117 along the first direction f1 is less than the width of the sixth sub-electrode 116 along the first direction f1.

[0160] Exemplarily, the sixth sub-electrode 116 completely covers the fourth sub-electrode 114, and the seventh sub-electrode 117 covers a part of the fifth sub-electrode 115.

[0161] It should be noted that the fourth conductive structure EC arranged in the same layer can be a fifth conductive structure EC1 located in the second conductive layer M2, or a sixth conductive structure EC2 located in the semiconductor layer ACT.

[0162] Exemplarily, the fourth conductive structure EC can include at least one of the fifth conductive structure EC1 located in the second conductive layer M2, and the sixth conductive structure EC2 located in the semiconductor layer ACT.

[0163] In some embodiments, as shown in FIG. 1, the fourth conductive structure EC includes a fifth conductive structure EC1 located in the second conductive layer M2, and the fifth conductive structure EC1 and the first conductive structure EP1 have overlapping in the orthographic projection on the substrate 10. FIGS. 19-21 The fifth conductive structure EC1 of the plurality of sub-pixels PX arranged along the first direction f1 are in communication with each other, and the fifth conductive structure EC1 of two adjacent sub-pixels PX arranged along the second direction f2 are provided with a scan line GL.

[0164] In the embodiment, the fourth conductive structure EC arranged in the same layer is the fifth conductive structure EC1 located in the second conductive layer M2, as shown in FIG. 1, the fifth conductive structure EC1 includes the sixth sub-electrode 116 and the seventh sub-electrode 117 located in the second conductive layer M2 and connected with each other. FIGS. 10-12

[0165] Exemplarily, in the orthographic projection on the substrate 10, the fifth conductive structure EC1, the first transfer pattern ZJ1 and the second transfer pattern ZJ2 are approximately aligned near the edge of the scan line GL.

[0166] Exemplarily, in the orthographic projection on the substrate 10, the fifth conductive structure EC1 and the data line DL have an overlapping area, and the width of the overlapping area along the second direction f2 is less than or equal to the width of the non-overlapping area along the second direction f2 (as shown in FIG. 1). FIGS. 19-21

[0167] By narrowing the width of the overlapping area of the fifth conductive structure EC1 and the data line DL along the second direction f2, the width of the overlapping area along the second direction f2 is less than the width of the non-overlapping area along the second direction f2, so that the parasitic capacitance between the fifth conductive structure EC1 and the data line DL can be reduced, and the signal stability can be improved.

[0168] In some embodiments, as shown in FIG. 1, the fourth conductive structure EC includes a fifth conductive structure EC1 located in the second conductive layer M2, and the fifth conductive structure EC1 and the first conductive structure EP1 have overlapping in the orthographic projection on the substrate 10. FIGS. 19-21 ​​As shown, the fourth conductive structure EC also includes a sixth conductive structure EC2, located in the semiconductor layer ACT. The sixth conductive structure EC2 overlaps with the first conductive structure EP1 in the orthographic projection on the substrate 10. The sixth conductive structure EC2 and the fifth conductive structure EC1 are connected by a fourth via H4 disposed on the first insulating layer GI.

[0169] For example, the semiconductor layer ACT also includes a fifth conductive region DT5, which is separated from the semiconductor pattern. The fifth conductive region DT5 constitutes a sixth conductive structure EC2, that is, the sixth conductive structure EC2 is a conductive semiconductor material.

[0170] In this embodiment, by setting a sixth conductive structure EC2 in the semiconductor layer ACT, the distance between the first conductive structure EP1 and the fourth conductive structure EC can be reduced, which is beneficial to increasing the capacitance of the first storage capacitor Cst1 or reducing the area of ​​the first conductive structure EP1 and the fourth conductive structure EC, thereby improving the pixel density.

[0171] In this embodiment, the fourth conductive structure EC disposed in the same layer is the sixth conductive structure EC2 located in the semiconductor layer ACT, such as... FIGS. 4-6 As shown, the sixth conductive structure EC2 includes a sixth sub-electrode 116 and a seventh sub-electrode 117 located in the semiconductor layer ACT and interconnected. In the orthographic projection on the substrate 10, the edges of the sixth sub-electrode 116 and the seventh sub-electrode 117 located in the semiconductor layer ACT are roughly aligned away from the gate G.

[0172] For example, such as FIGS. 19-21 As shown, in the orthographic projection on the substrate 10, the edge of the sixth conductive structure EC2 is located outside the edge of the fourth via H4, so as to ensure that the first insulating layer GI covers the edge of the sixth conductive structure EC2. This helps to avoid a short circuit between the fifth conductive structure EC1 and the first conductive structure EP1.

[0173] For example, such as FIGS. 19-21 As shown, in the orthographic projection on the substrate 10, the distance between the edge of the sixth conductive structure EC2 and the edge of the fourth via H4 is greater than or equal to half the width of the data line DL along the first direction f1, and less than or equal to twice the width of the data line DL along the first direction f1.

[0174] For example, such as FIGS. 19-21 As shown, a data line DL is provided between the sixth conductive structures EC2 of two adjacent sub-pixels PX arranged along the first direction f1, and a scan line GL is provided between the sixth conductive structures EC2 of two adjacent sub-pixels PX arranged along the second direction f2. In the orthographic projection on the substrate 10, the sixth conductive structure EC2 does not overlap with the scan line GL or the data line DL.

[0175] As shown in the orthogonal projection on the substrate 10, the aperture of the fourth via hole H4 along the first direction f1 is larger than the apertures of the first via hole H1 and the second via hole H2 along the first direction f1, and the aperture of the fourth via hole H4 along the second direction f2 is larger than the apertures of the first via hole H1 and the second via hole H2 along the second direction f2. In this way, the fifth conductive structure EC1 and the sixth conductive structure EC2 are overlapped by the larger via hole, which is conducive to reducing the contact resistance. FIGS. 7-9 As shown in the orthogonal projection on the substrate 10, the aperture of the fourth via hole H4 along the first direction f1 is larger than the apertures of the first via hole H1 and the second via hole H2 along the first direction f1, and the aperture of the fourth via hole H4 along the second direction f2 is larger than the apertures of the first via hole H1 and the second via hole H2 along the second direction f2. In this way, the fifth conductive structure EC1 and the sixth conductive structure EC2 are overlapped by the larger via hole, which is conducive to reducing the contact resistance.

[0176] FIGS. 19-21 As shown in the orthogonal projection on the substrate 10, the aperture of the fourth via hole H4 along the first direction f1 is larger than the apertures of the first via hole H1 and the second via hole H2 along the first direction f1, and the aperture of the fourth via hole H4 along the second direction f2 is larger than the apertures of the first via hole H1 and the second via hole H2 along the second direction f2. In this way, the fifth conductive structure EC1 and the sixth conductive structure EC2 are overlapped by the larger via hole, which is conducive to reducing the contact resistance.

[0177] For example, in the process of performing secondary etching on the first insulating layer GI, the first insulating layer GI is etched for the second time with the second conductive layer M2 as a mask plate, and the first insulating material not covered by the second conductive layer M2 is etched away, so that the edge of the first insulating layer GI is substantially aligned with the edge of the second conductive layer M2.

[0178] For example, in the process of performing secondary etching on the first insulating layer GI, the first insulating layer GI is etched for the second time with the second conductive layer M2 as a mask plate, and the first insulating material not covered by the second conductive layer M2 is etched away, so that the edge of the first insulating layer GI is substantially aligned with the edge of the second conductive layer M2.

[0179] In some embodiments, the first conductive structure EP1, the second conductive structure EP2 and the third conductive structure EP3 are pixel electrodes, and the fourth conductive structure EC, the fifth conductive structure EC1 and the sixth conductive structure EC2 are common electrodes, and the present disclosure is exemplarily described in this way.

[0180] For example, in the process of performing secondary etching on the first insulating layer GI, the first insulating layer GI is etched for the second time with the second conductive layer M2 as a mask plate, and the first insulating material not covered by the second conductive layer M2 is etched away, so that the edge of the first insulating layer GI is substantially aligned with the edge of the second conductive layer M2.

[0181] For example, in the process of performing secondary etching on the first insulating layer GI, the first insulating layer GI is etched for the second time with the second conductive layer M2 as a mask plate, and the first insulating material not covered by the second conductive layer M2 is etched away, so that the edge of the first insulating layer GI is substantially aligned with the edge of the second conductive layer M2.

[0182] For example, in the process of performing secondary etching on the first insulating layer GI, the first insulating layer GI is etched for the second time with the second conductive layer M2 as a mask plate, and the first insulating material not covered by the second conductive layer M2 is etched away, so that the edge of the first insulating layer GI is substantially aligned with the edge of the second conductive layer M2.

[0183] ​Exemplarily, the transparent conductive layer TD can adopt a transparent conductive material such as ITO, IZO, IGZO, IGO, ZTO, and the like metal oxide. The adoption of the metal oxide can improve the oxidation resistance of the transparent conductive layer TD.

[0184] To meet the driving requirements of the color electronic paper, the storage capacitance of each sub-pixel PX is greater than or equal to 1.0 pF and less than or equal to 2.0 pF, such as 1.2 pF. The storage capacitance is the sum of the capacitance values of the first storage capacitance Cst1 and the second storage capacitance Cst2.

[0185] Exemplarily, as shown in FIGS. 19-21 , the data lines DL extend along the column direction (i.e., the second direction f2), the scan lines GL extend along the row direction (i.e., the first direction f1), two adjacent sub-pixels PX in the same column are connected to the same scan line GL, the sub-pixels PX in the same column are connected to two data lines DL, the two data lines DL are located on the two sides of the sub-pixels PX in the column, and two adjacent sub-pixels PX in the same column are connected to different data lines DL.

[0186] The technical solutions provided by the present disclosure will be exemplarily described below. FIGS. 1-57 The technical solutions provided by the present disclosure will be exemplarily described below.

[0187] In the first exemplary embodiment, as shown in FIGS. 19-21 , the display substrate includes a substrate 10, and a first conductive layer M1, a buffer layer BF, a semiconductor layer ACT, a first insulating layer GI, a second conductive layer M2, a second insulating layer PVX, a third conductive layer M3, and a transparent conductive layer TD which are sequentially stacked on one side of the substrate 10, and the first conductive layer M1 is arranged close to the substrate 10.

[0188] As FIGS. 19-21As shown, the first conductive layer M1 includes the data line DL and the first conductive structure EP1. The semiconductor layer ACT includes the semiconductor pattern and the sixth conductive structure EC2, the semiconductor pattern includes the source connection region S, the first conductorization region DT1, the third conductorization region DT3, the channel region CH, the fourth conductorization region DT4, the second conductorization region DT2 and the drain connection region D arranged along the first direction f1 and connected in sequence, and the sixth conductive structure EC2 is the fifth conductorization region DT5. The first insulating layer GI is provided with the first via hole H1, the second via hole H2 and the fourth via hole H4, and the aperture of the fourth via hole H4 is larger than that of the first via hole H1 and the second via hole H2. The second conductive layer M2 includes the scan line GL, the gate G, the first transfer pattern ZJ1, the second transfer pattern ZJ2 and the fifth conductive structure EC1. The second insulating layer PVX is provided with the third via hole H3. The third conductive layer M3 includes the third conductive structure EP3 and the first shielding pattern ZD1 for shielding the channel region CH. The transparent conductive layer TD includes the second conductive structure EP2 and the protection pattern PT for protecting the first shielding pattern ZD1.

[0189] As shown in FIGS. 19-21 , the first transfer pattern ZJ1 realizes the connection of the data line DL and the source connection region S by half covering the first via hole H1, and the second transfer pattern ZJ2 realizes the connection of the first conductive structure EP1 and the drain connection region D by half covering the second via hole H2. The second conductive structure EP2 and the third conductive structure EP3 are directly connected, and the second conductive structure EP2 and the third conductive structure EP3 are connected with the second transfer pattern ZJ2 through the third via hole H3, so as to realize the connection of the second conductive structure EP2, the third conductive structure EP3 and the first conductive structure EP1. The fifth conductive structure EC1 is connected with the sixth conductive structure EC2 through the fourth via hole H4.

[0190] Among them, the storage capacitor includes the first storage capacitor Cst1 and the second storage capacitor Cst2 which are connected in parallel with each other. One of the plates of the first storage capacitor Cst1 is the first conductive structure EP1, the other plate is the fifth conductive structure EC1 and the sixth conductive structure EC2, and the dielectric layer is the buffer layer BF. One of the plates of the second storage capacitor Cst2 is the second conductive structure EP2 and the third conductive structure EP3, the other plate is the fifth conductive structure EC1 and the sixth conductive structure EC2, and the dielectric layer is the second insulating layer PVX.

[0191] Referring to FIGS. 1-21 , the display substrate provided by the embodiment can be prepared by the following steps:

[0192] Step 11: forming a patterned first conductive layer M1 on the substrate 10, as FIGS. 1-3As shown, the first conductive layer M1 includes the data lines DL and the first conductive structure EP1, and can also include a second shielding pattern (not shown in the figure), the orthographic projection of which on the substrate 10 covers the channel region CH.

[0193] Step 12: sequentially form a buffer layer BF and a patterned semiconductor layer ACT on the side of the first conductive layer M1 away from the substrate 10, as shown in FIGS. 4-6 The semiconductor layer ACT includes a semiconductor pattern and a sixth conductive structure EC2, the semiconductor pattern includes, arranged along the first direction f1 and sequentially connected, a source connection region S, a first conductorization region DT1, a third conductorization region DT3, a channel region CH, a fourth conductorization region DT4, a second conductorization region DT2, and a drain connection region D, and the sixth conductive structure EC2 is a fifth conductorization region DT5.

[0194] Step 13: form a patterned first insulating layer GI on the side of the semiconductor layer ACT away from the substrate 10, as shown in FIGS. 7-9 The first insulating layer GI is provided with a first via H1, a second via H2, and a fourth via H4, the aperture of the fourth via H4 is larger than that of the first via H1 and the second via H2. In the orthographic projection on the substrate 10, the first via H1 and the second via H2 are located on both sides of the channel region CH, the first via H1 exposes a part of the data line DL, the source connection region S, and the first conductorization region DT1, the second via H2 exposes a part of the first conductive structure EP1, the drain connection region D, and the second conductorization region DT2, and the fourth via H4 is located in the region of the sixth conductive structure EC2.

[0195] Step 14: form a patterned second conductive layer M2 on the side of the first insulating layer GI away from the substrate 10, as shown in FIGS. 10-12 The second conductive layer M2 includes a scan line GL, a gate G, a first transfer pattern ZJ1, a second transfer pattern ZJ2, and a fifth conductive structure EC1. The gate G is connected on one side of the scan line GL, the gate G overlaps the channel region CH, the first transfer pattern ZJ1 half-covers the first via H1 and is in communication with the data line DL and the source connection region S respectively, the second transfer pattern ZJ2 half-covers the second via H2 and is in communication with the drain connection region D and the first conductive structure EP1 respectively, and the fifth conductive structure EC1 fully covers the fourth via H4 and is in communication with the sixth conductive structure EC2.

[0196] As shown in FIGS. 10-12 After the second conductive layer M2 is formed, the first insulating layer GI is etched again with the second conductive layer M2 as a mask, and then the semiconductor material in the exposed regions (such as the first conductorization region DT1, the second conductorization region DT2, the third conductorization region DT3, and the fourth conductorization region DT4) of the semiconductor layer ACT is conductorized using a self-alignment process with the second conductive layer M2 as a mask.

[0197] Step 15: Form a patterned second insulating layer PVX on the side of the second conductive layer M2 that faces away from the substrate 10, such as... FIGS. 13-15 As shown, a third via H3 is provided on the second insulating layer PVX.

[0198] Step 16: Form a patterned third conductive layer M3 on the side of the second insulating layer PVX facing away from the substrate 10, such as... FIGS. 16-18 As shown, the third conductive layer M3 includes a third conductive structure EP3 and a first shielding pattern ZD1 for shielding the channel region CH. The third conductive structure EP3 fully covers the third via H3 and is connected to the second transition pattern ZJ2.

[0199] Step 17: Form a patterned transparent conductive layer TD on the side of the third conductive layer M3 facing away from the substrate 10, such as... FIGS. 19-21 As shown, the transparent conductive layer TD includes a second conductive structure EP2 and a protective pattern PT for protecting the first shielding pattern ZD1. The second conductive structure EP2 completely covers the third conductive structure EP3, and the protective pattern PT completely covers the first shielding pattern ZD1.

[0200] In the second exemplary embodiment, such as FIGS. 37-39 As shown, the display substrate includes: a substrate 10, and a first conductive layer M1, a buffer layer BF, a semiconductor layer ACT, a first insulating layer GI, a second conductive layer M2, a second insulating layer PVX and a transparent conductive layer TD sequentially stacked on one side of the substrate 10, with the first conductive layer M1 disposed close to the substrate 10.

[0201] like FIGS. 37-39 As shown, the first conductive layer M1 includes a data line DL and a first conductive structure EP1. The semiconductor layer ACT includes a semiconductor pattern and a sixth conductive structure EC2. The semiconductor pattern includes a source connection region S, a first conductive region DT1, a third conductive region DT3, a channel region CH, a fourth conductive region DT4, a second conductive region DT2, and a drain connection region D, arranged and connected sequentially along the first direction f1. The sixth conductive structure EC2 is the fifth conductive region DT5. A first via H1, a second via H2, and a fourth via H4 are provided on the first insulating layer GI. The aperture of the fourth via H4 is larger than the apertures of the first via H1 and the second via H2. The second conductive layer M2 includes a scan line GL, a gate G, a first transition pattern ZJ1, a second transition pattern ZJ2, and a fifth conductive structure EC1. A third via H3 is provided on the second insulating layer PVX. The transparent conductive layer TD includes a second conductive structure EP2.

[0202] like FIGS. 37-39As shown, the first transfer pattern ZJ1 realizes the connection of the data line DL and the source connection region S through the half-coverage of the first via hole H1, and the second transfer pattern ZJ2 realizes the connection of the first conductive structure EP1 and the drain connection region D through the half-coverage of the second via hole H2. The second conductive structure EP2 is connected with the second transfer pattern ZJ2 through the third via hole H3, so as to realize the connection of the second conductive structure EP2 and the first conductive structure EP1. The fifth conductive structure EC1 is connected with the sixth conductive structure EC2 through the fourth via hole H4.

[0203] The storage capacitor includes the first storage capacitor Cst1 and the second storage capacitor Cst2 in parallel with each other. One plate of the first storage capacitor Cst1 is the first conductive structure EP1, the other plate is the fifth conductive structure EC1 and the sixth conductive structure EC2, and the dielectric layer is the buffer layer BF. One plate of the second storage capacitor Cst2 is the second conductive structure EP2, the other plate is the fifth conductive structure EC1 and the sixth conductive structure EC2, and the dielectric layer is the second insulating layer PVX.

[0204] Referring to FIGS. 22-24 The display substrate provided by the embodiment can be prepared by the following steps.

[0205] Step 21: forming a patterned first conductive layer M1 on the substrate 10, as shown in FIG. 2. FIGS. 25-27 As shown, the first conductive layer M1 includes the data line DL and the first conductive structure EP1, and can also include a second shielding pattern (not shown in the figure), the orthographic projection of the second shielding pattern on the substrate 10 covering the channel region CH.

[0206] Step 22: sequentially forming a buffer layer BF and a patterned semiconductor layer ACT on the side of the first conductive layer M1 away from the substrate 10, as shown in FIG. 3. FIGS. 28-30 As shown, the semiconductor layer ACT includes a semiconductor pattern and a sixth conductive structure EC2. The semiconductor pattern includes the source connection region S, the first conductive region DT1, the third conductive region DT3, the channel region CH, the fourth conductive region DT4, the second conductive region DT2 and the drain connection region D arranged along the first direction f1 and connected in sequence, and the sixth conductive structure EC2 is the fifth conductive region DT5.

[0207] Step 23: forming a patterned first insulating layer GI on the side of the semiconductor layer ACT away from the substrate 10, as shown in FIG. 4. FIGS. 31-33As shown, a first via H1, a second via H2, and a fourth via H4 are provided on the first insulating layer GI. The diameter of the fourth via H4 is larger than that of the first via H1 and the second via H2. In the orthographic projection on the substrate 10, the first via H1 and the second via H2 are located on both sides of the channel region CH. The first via H1 exposes a portion of the data line DL, the source connection region S, and the first conductor region DT1. The second via H2 exposes a portion of the first conductive structure EP1, the drain connection region D, and the second conductor region DT2. The fourth via H4 is located within the region of the sixth conductive structure EC2.

[0208] Step 24: Form a patterned second conductive layer M2 on the side of the first insulating layer GI facing away from the substrate 10, such as... FIGS. 31-33 As shown, the second conductive layer M2 includes a scan line GL, a gate G, a first transition pattern ZJ1, a second transition pattern ZJ2, and a fifth conductive structure EC1. The gate G is connected to one side of the scan line GL and overlaps with the channel region CH. The first transition pattern ZJ1 partially covers the first via H1, which is connected to the data line DL and the source connection region S. The second transition pattern ZJ2 partially covers the second via H2, which is connected to the drain connection region D and the first conductive structure EP1. The fifth conductive structure EC1 fully covers the fourth via H4, which is connected to the sixth conductive structure EC2.

[0209] like FIGS. 34-36 As shown, after the second conductive layer M2 is formed, the first insulating layer GI is etched a second time using the second conductive layer M2 as a mask. Then, using the second conductive layer M2 as a mask, a self-aligned process is used to conduct the semiconductor material in the exposed areas (such as the first conductor region DT1, the second conductor region DT2, the third conductor region DT3, and the fourth conductor region DT4) of the semiconductor layer ACT.

[0210] Step 25: Form a patterned second insulating layer PVX on the side of the second conductive layer M2 that faces away from the substrate 10, such as... FIGS. 37-39 As shown, a third via H3 is provided on the second insulating layer PVX.

[0211] Step 26: Form a patterned transparent conductive layer TD on the side of the second insulating layer PVX facing away from the substrate 10, such as... FIGS. 55-57 As shown, the transparent conductive layer TD includes a second conductive structure EP2, which fully covers the third via H3 and is connected to the second transition pattern ZJ2.

[0212] In the third exemplary embodiment, such as FIGS. 55-57As shown in FIG. 1, the display substrate includes a substrate 10, and a first conductive layer M1, a buffer layer BF, a semiconductor layer ACT, a first insulating layer GI, a second conductive layer M2, a second insulating layer PVX and a transparent conductive layer TD which are sequentially arranged on one side of the substrate 10, wherein the first conductive layer M1 is arranged close to the substrate 10.

[0213] As shown in FIG. 2, the first conductive layer M1 includes a data line DL and a first conductive structure EP1. The semiconductor layer ACT includes a semiconductor pattern, and the semiconductor pattern includes a source connection region S, a first conductorization region DT1, a third conductorization region DT3, a channel region CH, a fourth conductorization region DT4, a second conductorization region DT2 and a drain connection region D which are sequentially connected and arranged along a first direction f1. The first insulating layer GI is provided with a first via hole H1 and a second via hole H2. The second conductive layer M2 includes a scan line GL, a gate G, a first transfer pattern ZJ1, a second transfer pattern ZJ2 and a fifth conductive structure EC1. The second insulating layer PVX is provided with a third via hole H3. The transparent conductive layer TD includes a second conductive structure EP2. FIGS. 55-57 As shown in FIG. 3, the first transfer pattern ZJ1 realizes the connection between the data line DL and the source connection region S by half covering the first via hole H1, and the second transfer pattern ZJ2 realizes the connection between the first conductive structure EP1 and the drain connection region D by half covering the second via hole H2. The second conductive structure EP2 is connected with the second transfer pattern ZJ2 through the third via hole H3, so as to realize the connection between the second conductive structure EP2 and the first conductive structure EP1.

[0214] FIGS. 40-42 As shown in FIG. 4, the first transfer pattern ZJ1 realizes the connection between the data line DL and the source connection region S by half covering the first via hole H1, and the second transfer pattern ZJ2 realizes the connection between the first conductive structure EP1 and the drain connection region D by half covering the second via hole H2. The second conductive structure EP2 is connected with the second transfer pattern ZJ2 through the third via hole H3, so as to realize the connection between the second conductive structure EP2 and the first conductive structure EP1.

[0215] As shown in FIG. 5, the first storage capacitor Cst1 and the second storage capacitor Cst2 are connected in parallel. One plate of the first storage capacitor Cst1 is the first conductive structure EP1, and the other plate is the fifth conductive structure EC1. The dielectric layer includes the buffer layer BF and the first insulating layer GI. One plate of the second storage capacitor Cst2 is the second conductive structure EP2, and the other plate is the fifth conductive structure EC1. The dielectric layer is the second insulating layer PVX.

[0216] Referring to FIG. 6, the display substrate provided by the embodiment can be prepared by the following steps: FIGS. 43-45 Step 31: forming a patterned first conductive layer M1 on the substrate 10, as shown in FIG. 7, the first conductive layer M1 includes a data line DL and a first conductive structure EP1, and can also include a second shielding pattern (not shown in the figure), and the orthographic projection of the second shielding pattern on the substrate 10 covers the channel region CH.

[0217] FIGS. 46-48

[0218] ​​​Step 32: Form a buffer layer BF and a patterned semiconductor layer ACT in sequence on the side of the first conductive layer M1 away from the substrate 10, as shown in FIGS. 49-51 The semiconductor layer ACT includes a semiconductor pattern, which includes a source connection region S, a first conductorization region DT1, a third conductorization region DT3, a channel region CH, a fourth conductorization region DT4, a second conductorization region DT2 and a drain connection region D arranged in the first direction f1 and connected in sequence.

[0219] Step 33: Form a patterned first insulating layer GI on the side of the semiconductor layer ACT away from the substrate 10, as shown in FIGS. 49-51 The first insulating layer GI is provided with a first via hole H1 and a second via hole H2. In the orthographic projection on the substrate 10, the first via hole H1 and the second via hole H2 are located on both sides of the channel region CH, the first via hole H1 exposes a part of the data line DL, the source connection region S and the first conductorization region DT1, and the second via hole H2 exposes a part of the first conductive structure EP1, the drain connection region D and the second conductorization region DT2.

[0220] Step 34: Form a patterned second conductive layer M2 on the side of the first insulating layer GI away from the substrate 10, as shown in FIGS. 52-54 The second conductive layer M2 includes a scan line GL, a gate G, a first transfer pattern ZJ1, a second transfer pattern ZJ2 and a fifth conductive structure EC1. The gate G is connected on one side of the scan line GL, the gate G overlaps the channel region CH, the first transfer pattern ZJ1 half covers the first via hole H1 and respectively communicates with the data line DL and the source connection region S, and the second transfer pattern ZJ2 half covers the second via hole H2 and respectively communicates with the drain connection region D and the first conductive structure EP1.

[0221] As shown in FIGS. 55-57 After the second conductive layer M2 is formed, the first insulating layer GI is etched again using the second conductive layer M2 as a mask, and then the semiconductor material in the exposed regions (such as the first conductorization region DT1, the second conductorization region DT2, the third conductorization region DT3 and the fourth conductorization region DT4) in the semiconductor layer ACT is conductorized using a self-alignment process with the second conductive layer M2 as a mask.

[0222] Step 35: Form a patterned second insulating layer PVX on the side of the second conductive layer M2 away from the substrate 10, as shown in FIG. 59 The second insulating layer PVX is provided with a third via hole H3.

[0223] Step 36: Form a patterned transparent conductive layer TD on the side of the second insulating layer PVX away from the substrate 10, as shown in FIG. 60As shown, the transparent conductive layer TD includes a second conductive structure EP2, and the second conductive structure EP2 fully covers the third via hole H3 and is in communication with the second transfer pattern ZJ2.

[0224] In the first to third example embodiments, each step corresponds to a mask plate process, and the display substrate in the first example embodiment is prepared by using seven mask plate processes. In the second and third example embodiments, since the third conductive layer M3 is not provided, the display substrate in the second and third example embodiments is prepared by using six mask plate processes, thereby reducing one mask plate process.

[0225] The display device provided by the present disclosure includes a display substrate as provided in any of the example embodiments. ​ As shown, the display device includes an opposed substrate 171, an electrophoretic solution 172, and a display substrate 173 as provided in any of the example embodiments. The electrophoretic solution 172 is located between the opposed substrate 171 and the display substrate 173, and the second conductive layer M2 is located on the side of the substrate 10 close to the electrophoretic solution.

[0226] The electrophoretic solution 172 includes target particles LZ. The target particles can be electrophoretic particles, such as two-color particles, three-color particles, or four-color particles, etc. The target particles can also be liquid crystal molecules.

[0227] As understood by those skilled in the art, the display device provided by the present disclosure has the advantages of the display substrate 173 described above.

[0228] The display device provided by the present disclosure can be any product or component having a display function, such as electronic paper, electronic price tags, electronic badges, display modules, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, vehicle-mounted display devices, smart watches, fitness wristbands, personal digital assistants, etc.

[0229] The opposed substrate 171 includes an opposed substrate 1711 and an opposed electrode 1712 provided on the side of the opposed substrate 1711 close to the electrophoretic solution 172. The opposed electrode 1712 and the pixel electrode EP2 jointly form an electric field for driving the target particles LZ to move.

[0230] The electrophoretic solution 172 can be an electronic paper film.

[0231] As shown, the display device can further include a driving chip IC bonded to the non-display area NA of the display substrate 173. The driving chip IC is connected to the driving circuit board 182 through a flexible circuit board 181. ​

[0232] ​In the process of displaying a picture, the driving chip IC can be started by the driving circuit board 182, the driving chip IC inputs a scanning signal into the scanning line GL and inputs a data signal into the data line DL, the thin film transistor is turned on, the pixel electrode EP2 of the sub-pixel PX obtains the voltage required by the picture, a pressure difference is formed with the upper layer of the counter electrode 1712, the white particles and the black particles in the electrophoretic solution 172 are separated, and different display gray scale states are formed.

[0233] In the present disclosure, the terms "upper", "lower", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0234] In the present disclosure, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations.

[0235] In the present specification, "electrically connected" and "coupled" include the case where the constituent elements are connected together through an element having a certain electrical effect. The element having a certain electrical effect is not particularly limited as long as it can perform the transmission and reception of electrical signals between the connected constituent elements. Examples of the element having a certain electrical effect include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0236] In the present disclosure, the meaning of "a plurality of" is two or more, and the meaning of "at least one" is one or more, unless specifically limited otherwise. "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C. "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0237] The use of "for" or "configured to" in the present disclosure means open and inclusive language that does not exclude devices that are adapted to or configured to perform additional tasks or steps.

[0238] As used in the present disclosure, "about", "approximately", or "approximately" includes the stated value and the average value within an acceptable deviation range of the specific value, wherein the acceptable deviation range is determined by considering the measurement being discussed and the error related to the measurement of the specific quantity (i.e., the limitations of the measurement system) by a person of ordinary skill in the art.

[0239] As used in this disclosure, "parallel," "perpendicular," "equal," and "flush" include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein an acceptable deviation range for approximate parallelism may be, for example, within 10° or 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein an acceptable deviation range for approximate perpendicularity may also be, for example, within 10° or 5°. "Equal" includes absolute equality and approximate equality, wherein an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one. "Flush" includes absolute flush and approximate flush, wherein an acceptable deviation range for approximate flush may be, for example, a distance between the flushes being less than or equal to 5% of either one's dimension.

[0240] It should be understood that when a layer or element is referred to as being disposed on one side of another layer or substrate, it may be that the layer or element is directly disposed on the other layer or substrate, or it may be that there is an intermediate layer between the layer or element and the other layer or substrate.

[0241] This disclosure describes exemplary embodiments with reference to cross-sectional views and / or plan views as idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown in this disclosure, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0242] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A display substrate comprising a plurality of sub-pixels in a display area, the display substrate comprising: a substrate, and a first conductive layer, a semiconductor layer, a first insulating layer and a second conductive layer sequentially stacked on a side of the substrate, the first conductive layer being disposed close to the substrate; wherein the first conductive layer comprises a data line and a plurality of first conductive structures in different sub-pixels, the semiconductor layer comprises a plurality of semiconductor patterns in different sub-pixels, the semiconductor pattern comprises, in sequence along a first direction, a source connection region, a first conductorization region, a channel region, a second conductorization region and a drain connection region, the second conductive layer comprises a plurality of gate electrodes in different sub-pixels, and a first transfer pattern and a second transfer pattern are oppositely disposed on both sides of the gate electrode along the first direction; and the first insulating layer is provided with a first via and a second via, the first via exposes a part of the data line, the source connection region and the first conductorization region, the second via exposes a part of the first conductive structure, the drain connection region and the second conductorization region, the data line and the source connection region are respectively overlapped with the first transfer pattern through the first via, and the first conductive structure and the drain connection region are respectively overlapped with the second transfer pattern through the second via, and in the orthographic projection on the substrate, the first transfer pattern has no overlap with the first conductorization region, and the second transfer pattern has no overlap with the second conductorization region. The semiconductor pattern further comprises: a third conductorization region connected between the first conductorization region and the channel region, a thickness of the first conductorization region being different from a thickness of the third conductorization region; and a fourth conductorization region connected between the second conductorization region and the channel region, a thickness of the second conductorization region being different from a thickness of the fourth conductorization region. The thickness of the first conductorization region is less than the thickness of the third conductorization region, the thickness of the first conductorization region is less than or equal to the thickness of the source connection region, and the thickness of the third conductorization region is less than or equal to the thickness of the channel region; and the thickness of the second conductorization region is less than the thickness of the fourth conductorization region, the thickness of the second conductorization region is less than or equal to the thickness of the drain connection region, and the thickness of the fourth conductorization region is less than or equal to the thickness of the channel region. The display substrate further comprises: a second insulating layer disposed on a side of the second conductive layer away from the substrate; and a transparent conductive layer disposed on a side of the second insulating layer away from the substrate, the transparent conductive layer comprising a plurality of second conductive structures in different sub-pixels, the second conductive structure being overlapped with the second transfer pattern through a third via provided on the second insulating layer, and the second conductive structure having no overlap with the gate electrode in the orthographic projection on the substrate. 2.The display substrate of claim 1, wherein, ​ ​ ​ 3.The display substrate of claim 2, wherein, ​ ​ 4.The display substrate of claim 1, wherein, ​ ​ ​ 5.The display substrate of claim 4, wherein, The second conductive structure includes a first sub-electrode, a second sub-electrode and a third sub-electrode, the second sub-electrode and the third sub-electrode are located on the same side of the first sub-electrode and are connected with the first sub-electrode respectively, in the orthographic projection on the substrate, the second sub-electrode and the third sub-electrode are oppositely arranged on two sides of the gate electrode along the first direction; and The gap width between the second sub-electrode and the third sub-electrode is substantially equal to the gap width between two adjacent second conductive structures. 6.The display substrate of claim 4, wherein, The display substrate further includes: A third conductive layer is arranged between the second insulating layer and the transparent conductive layer, the third conductive layer includes a plurality of third conductive structures located in different sub-pixels, the surface of the third conductive structure away from the substrate directly contacts the surface of the second conductive structure close to the substrate, in the orthographic projection on the substrate, the second conductive structure covers the third conductive structure, and the third conductive structure covers the third via hole and the second transfer pattern. 7.The display substrate of claim 6, wherein, In the orthographic projection on the substrate, the shape of the second conductive structure is different from that of the third conductive structure, the second conductive structure covers the first transfer pattern, and the third conductive structure does not overlap the first transfer pattern. 8.The display substrate of claim 6, wherein, The third conductive layer further includes a first shielding pattern, the first shielding pattern is arranged in a spaced manner with the third conductive structure, and the orthographic projection of the first shielding pattern on the substrate covers the orthographic projection of the channel region on the substrate; The transparent conductive layer further includes a protection pattern, the protection pattern is arranged in a spaced manner with the second conductive structure, and the orthographic projection of the protection pattern on the substrate covers the orthographic projection of the first shielding pattern on the substrate. 9.The display substrate of claim 4, wherein, In the orthographic projection on the substrate, the gap width between two adjacent second conductive structures is greater than or equal to 5 microns and less than or equal to 15 microns. 10.The display substrate according to any one of claims 1 to 9, wherein The sub-pixel further includes: A fourth conductive structure is located in the second conductive layer and / or the semiconductor layer, the fourth conductive structure overlaps the orthographic projection of the first conductive structure on the substrate, and the fourth conductive structures of a plurality of sub-pixels arranged along the first direction and / or the second direction are interconnected, the second direction being the extension direction of the data line. 11.The display substrate of claim 10, wherein, The first conductive structure includes: A fourth sub-electrode and a fifth sub-electrode connected with each other, in the orthographic projection on the substrate, the fifth sub-electrode is located on the side of the fourth sub-electrode close to the gate electrode, the width of the fifth sub-electrode along the first direction is less than the width of the fourth sub-electrode along the first direction, the fifth sub-electrode overlaps the second transfer pattern, and the fourth conductive structure covers part of the fifth sub-electrode and the fourth sub-electrode. 12.The display substrate of claim 11, wherein, The fourth conductive structure arranged in the same layer includes: The sixth and seventh sub-electrodes are connected to each other, the seventh sub-electrode is located on the side of the sixth sub-electrode close to the gate electrode, the seventh sub-electrode is located on the side of the second transfer pattern away from the gate electrode, the width of the seventh sub-electrode along the first direction is smaller than the width of the sixth sub-electrode along the first direction, the sixth sub-electrode completely covers the fourth sub-electrode, and the seventh sub-electrode covers part of the fifth sub-electrode. 13.The display substrate of claim 10, wherein, The fourth conductive structure comprises: The fifth conductive structure is located on the second conductive layer, the fifth conductive structure overlaps the first conductive structure in the orthographic projection on the substrate, the fifth conductive structures of the plurality of sub-pixels arranged along the first direction are connected to each other, and the fifth conductive structures of two adjacent sub-pixels arranged along the second direction are provided with a scan line, the scan line is located on the second conductive layer and connected to the gate electrode. 14.The display substrate of claim 13, wherein, In the orthographic projection on the substrate, the fifth conductive structure has an overlapping area with the data line, and the width of the overlapping area along the second direction is smaller than or equal to the width of the non-overlapping area along the second direction. 15.The display substrate of claim 13, wherein, The fourth conductive structure further comprises: The sixth conductive structure is located on the semiconductor layer, the sixth conductive structure overlaps the first conductive structure in the orthographic projection on the substrate, the sixth conductive structure is connected to the fifth conductive structure through the fourth via provided on the first insulating layer, and in the orthographic projection on the substrate, the edge of the sixth conductive structure is located in the periphery of the edge of the fourth via; and The sixth conductive structures of two adjacent sub-pixels arranged along the first direction are provided with the data line, and the sixth conductive structures of two adjacent sub-pixels arranged along the second direction are provided with the scan line. 16.The display substrate of claim 15, wherein, In the orthographic projection on the substrate, the distance between the edge of the sixth conductive structure and the edge of the fourth via is greater than or equal to half of the width of the data line along the first direction and smaller than or equal to twice the width of the data line along the first direction. 17.The display substrate of claim 15, wherein, In the orthographic projection on the substrate, the aperture of the fourth via along the first direction is greater than the apertures of the first via and the second via along the first direction, and the aperture of the fourth via along the second direction is greater than the apertures of the first via and the second via along the second direction.

18. The display substrate according to any one of claims 1 to 9, wherein, In the orthographic projection on the substrate, the second conductive layer completely covers the first insulating layer, and part of the edge of the first insulating layer is substantially aligned with the edge of the second conductive layer.

19. A display device comprising: The display substrate as claimed in any one of claims 1 to 18, an electrophoretic solution is located between the display substrate and the counter substrate, and the second conductive layer is located on the side of the substrate close to the electrophoretic solution.

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