Wafer electrostatic processing system and semiconductor detection equipment

Abstract

The utility model provides a wafer electrostatic processing system and semiconductor detection equipment. The wafer electrostatic processing system comprises a discharge probe, an acquisition probe, an electric breakdown module and a signal acquisition module. And the electric breakdown module is electrically communicated with the discharge probe so as to electrically break down the insulating layer on the surface of the processed wafer through the discharge probe. And the signal acquisition module is electrically communicated with the discharge probe and the acquisition probe at the same time so as to acquire an electric signal between the discharge probe and the acquisition probe and further determine the breakdown state of the insulating layer on the surface of the processed wafer. When the electric breakdown module carries out breakdown work, electric signal sampling between the discharge probe and the acquisition probe is carried out in real time so as to determine the breakdown state of the insulating layer on the surface of the processed wafer in real time, whether the surface of the processed wafer is broken down or not can be known in time, and the breakdown process and effect can be mastered in real time; and meanwhile, the electric breakdown module is controlled to work or stop, so that the breakdown process and the electrostatic discharge process are controllable.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor manufacturing, in particular to a wafer electrostatic treatment system and semiconductor detection equipment for wafer electrostatic discharge. BACKGROUND

[0002] In the manufacturing process of the wafer, static electricity has been an important problem that needs to be paid attention to and controlled, and static electricity can cause damage to the wafer device, increase the defective rate, reduce the chip performance and reliability, etc. The wafer surface has an insulating layer for protecting and isolating the material layer of the electronic device. In order to release the wafer static electricity, a probe can be arranged on the surface of the wafer, and then high voltage is applied to the probe, and the insulating layer is broken down by high voltage and the probe. Specifically, the existing wafer electrostatic treatment system first breaks down the insulating layer on the surface of the wafer by using an electric breakdown module, and then collects the electric signal on the wafer by using a signal collection module to determine whether the wafer surface is broken down. However, the existing wafer electrostatic treatment system releases static electricity by the method of breaking down first and then collecting, which is slow in sampling, and cannot know whether the wafer surface is broken down in time every time it is broken down, and the breakdown process and the static electricity release process are uncontrollable. SUMMARY

[0003] In view of the above problems, the utility model is proposed to provide a wafer electrostatic treatment system and semiconductor detection equipment for wafer electrostatic discharge to overcome the above problems or at least partially solve the above problems.

[0004] An object of the utility model is to solve the problem of slow sampling when the wafer surface is broken down, so as to achieve the effect of sampling in time while electric breakdown is performed.

[0005] Another object of the present application is to know whether the wafer surface is broken down in time, so as to achieve the effect that the electric breakdown process and the static electricity release process are controllable.

[0006] Specifically, the utility model provides a wafer electrostatic treatment system, which comprises:

[0007] The discharge probe is configured to be in contact with the surface of the wafer to be processed at one position of the surface of the wafer to be processed;

[0008] The electric breakdown module is electrically connected with the discharge probe to electrically shock the wafer to be processed through the discharge probe;

[0009] The collection probe is configured to be in contact with the surface of the wafer to be processed at another position of the surface of the wafer to be processed;

[0010] A signal collection module, which is electrically connected with the discharge probe and the collection probe, and is configured to collect the electrical signal on the discharge probe or between the discharge probe and the collection probe.

[0011] Optionally, the wafer electrostatic treatment system further comprises a first switching device, the electrical breakdown module and the signal collection module are electrically connected with the discharge probe through the first switching device, so that the electrical breakdown module and the signal collection module are simultaneously turned on or turned off with the discharge probe.

[0012] Optionally, the wafer electrostatic treatment system further comprises a second switching device, which is between the signal collection module and the collection probe, so that the signal collection module is turned on or turned off with the collection probe.

[0013] Optionally, the wafer electrostatic treatment system further comprises:

[0014] An electrostatic elimination module, which is controlled to be electrically connected with the discharge probe and the collection probe, so as to apply voltage to the wafer to be treated through the discharge probe and the collection probe.

[0015] Optionally, the wafer electrostatic treatment system further comprises:

[0016] A third switching device, which is between the electrostatic elimination module and the discharge probe, so as to control the turn-on or turn-off between the electrostatic elimination module and the discharge probe;

[0017] A fourth switching device, which is between the electrostatic elimination module and the collection probe, so as to control the turn-on or turn-off between the electrostatic elimination module and the collection probe.

[0018] Optionally, the third switching device is between the first switching device and the electrostatic elimination module, so that the electrostatic elimination module is turned on with the discharge probe when the third switching device and the first switching device are both turned on.

[0019] The fourth switching device is between the second switching device and the electrostatic elimination module, so that the electrostatic elimination module is turned on with the collection probe when the fourth switching device and the second switching device are both turned on.

[0020] Optionally, the wafer electrostatic treatment system further comprises:

[0021] A processing submodule, and the signal collection module is connected to the processing submodule.

[0022] a turn-on and turn-off control sub-module connected to the processing sub-module, and the processing sub-module controls the first switch device, the second switch device, the third switch device and the fourth switch device through the turn-on and turn-off control sub-module;

[0023] a driving circuit sub-module arranged between the processing sub-module and the electrical breakdown module, so that the processing sub-module controls the electrical breakdown module through the driving circuit sub-module.

[0024] Optionally, the electrical signal is a voltage signal.

[0025] The signal acquisition module comprises an operational amplifier circuit configured to acquire a voltage value on the discharge probe or a voltage difference between the discharge probe and the acquisition probe.

[0026] Optionally, the signal acquisition module or the control module comprises a grounding terminal, and the acquisition probe is configured to be in electrical communication with the grounding terminal, so that the wafer under processing is grounded through the acquisition probe and the signal acquisition module.

[0027] Optionally, the signal acquisition module further comprises an operational amplifier circuit protection resistor arranged between the discharge probe and an input terminal of the operational amplifier circuit.

[0028] A power supply protection resistor is arranged between the electrical breakdown module and the discharge probe.

[0029] The utility model further provides a kind of semiconductor detection equipment, it includes:

[0030] Equipment main body, the equipment main body is used to accommodate wafer under processing;

[0031] Any wafer electrostatic treatment system described above is arranged on the equipment main body, and the discharge probe and the acquisition probe are respectively contacted with the surface of wafer under processing at two different positions of the surface of wafer under processing.

[0032] The wafer electrostatic treatment system and the semiconductor detection equipment have the signal acquisition module, the electric signal on the discharge probe, the electric signal on the acquisition probe or the electric signal sampling between the discharge probe and the acquisition probe are sampled in real time while the electric breakdown module is working, so that the breakdown state of the insulating layer on the wafer surface can be determined in real time, the sampling is timely, and then it can be known in time whether the wafer surface is broken down, the process and effect of the breakdown can be mastered in real time; meanwhile, the wafer electrostatic treatment system can control the electric breakdown module to work according to the sampling result, so that the breakdown process and the electrostatic discharge process are controllable; and the wafer electrostatic treatment system does not need to wait for the acquisition process of the prior scheme of first breakdown and then acquisition, and the speed of the whole electric breakdown process is improved.

[0033] The above and other objects, advantages and features of the present application will become more apparent from the following detailed description of some embodiments thereof, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0034] Some embodiments of the present application will now be described, by way of example only, with reference to the accompanying drawings. Identical or similar components or parts are referred to using the same reference numerals throughout the figures. It should be understood that these drawings are not necessarily to scale. In the figures:

[0035] Figure 1 is a schematic structural block diagram of a wafer electrostatic treatment system according to an embodiment of the present application;

[0036] Figure 2 is a schematic structural block diagram of a wafer electrostatic treatment system according to an embodiment of the present application;

[0037] Figure 3 is a schematic structural block diagram of a wafer electrostatic treatment system according to an embodiment of the present application;

[0038] Figure 4 is a partial structural schematic diagram of a wafer electrostatic treatment system according to an embodiment of the present application.

[0039] In the drawings:

[0040] 10, wafer to be treated; 11, discharge probe; 12, acquisition probe; 20, control module; 21, processing sub-module; 22, on-off control sub-module; 23, driving circuit sub-module; 24, power supply module; 25, power supply system; 31, electric breakdown module; 32, first switching device; 33, signal acquisition module; 34, second switching device; 35, third switching device; 36, fourth switching device; 37, static elimination module; 41, operational amplifier circuit; 42, operational amplifier circuit protection resistor; 43, power supply protection resistor. Detailed Implementation

[0041] The following reference Figures 1 to 4 This invention describes a wafer electrostatic discharge (ESD) system and semiconductor inspection equipment according to embodiments of the present invention. In this description, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature, that is, include one or more of that feature. In the description of the present invention, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. When a feature "includes or contains" one or more of the features it encompasses, unless otherwise specifically described, this indicates that other features are not excluded and may be further included.

[0042] Unless otherwise expressly specified and limited, the terms "set," "install," "connect," "link," "fix," and "couple" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art should be able to understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0043] Furthermore, in the description of this embodiment, "above" or "below" the second feature can include direct contact between the first and second features, or it can include contact between the first and second features through another feature between them. That is, in the description of this embodiment, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," or "below" of the second feature can mean the first feature is directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0044] In the description of this embodiment, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this utility model. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0045] Figure 1 This is a schematic structural block diagram of a wafer electrostatic treatment system according to an embodiment of the present invention, as shown below. Figure 1 As shown, and refer to Figures 2 to 4 This utility model provides a wafer electrostatic treatment system that uses electrical breakdown to break down the insulating layer on the surface of the wafer 10 to release the static electricity on the wafer 10. While electrically breaking down the insulating layer on the surface of the wafer 10, the system can collect the breakdown state of the insulating layer on the surface of the wafer 10 in real time.

[0046] The wafer electrostatic discharge system includes a discharge probe 11, a data acquisition probe 12, an electrical breakdown module 31, and a signal acquisition module 33.

[0047] The discharge probe 11 is configured to contact the surface of the wafer 10 at one location. The acquisition probe 12 is configured to contact the surface of the wafer 10 at another location. That is, the discharge probe 11 and the acquisition probe 12 are arranged at a distance from each other, and both are in contact with the surface of the wafer 10. The discharge probe 11 applies a breakdown voltage to the surface of the wafer 10. Simultaneously, the discharge probe 11 and the acquisition probe 12 cooperate and connect to a signal acquisition module to acquire the electrical signals on the wafer 10.

[0048] The electrical breakdown module 31 is electrically connected to the discharge probe 11 to electrically shock the wafer 10 being processed through the discharge probe 11. That is, the electrical breakdown module 31 is connected to the wafer 10 being processed through the discharge probe 11 and provides high voltage to electrically shock the insulating layer on the surface of the wafer 10 being processed until the insulating layer on the surface of the wafer 10 being processed is broken down.

[0049] The signal acquisition module 33 is electrically connected to both the discharge probe 11 and the acquisition probe 12. The signal acquisition module 33 is configured to acquire the electrical signal on the discharge probe 11, the electrical signal on the acquisition probe 12, or the electrical signal between the discharge probe 11 and the acquisition probe 12. Since the signal acquisition module 33 is also electrically connected to both the discharge probe 11 and the acquisition probe 12 when the discharge probe 11 strikes the processed wafer 10, the signal acquisition module 33 acquires the electrical signal during this process.

[0050] When the insulating layer on the surface of the wafer 10 being processed is broken down, the resistance of the wafer 10 being processed decreases. The wafer 10 being processed is equivalent to a resistor. The discharge probe 11 is equivalent to an electrical connection point at one end of the wafer 10 being processed, and the acquisition probe 12 is equivalent to an electrical connection point at the other end of the wafer 10 being processed.

[0051] With the acquisition probe 12 grounded, the electrical signal at the discharge probe 11 changes with the resistance value of the processed wafer 10, thus reflecting the amount of change in the resistance value of the processed wafer 10 and determining the breakdown state of the insulating layer on the surface of the processed wafer 10. Therefore, the signal acquisition module 33 can acquire the electrical signal on the discharge probe 11 to reflect the amount of change in the resistance value of the processed wafer 10.

[0052] Similarly, when the acquisition probe 12 is not grounded, the electrical signal at the discharge probe 11 will also change with the change in the resistance value of the processed wafer 10, thus reflecting the amount of change in the resistance value of the processed wafer 10. Therefore, the signal acquisition module 33 can be used to acquire the electrical signal on the discharge probe 11 to reflect the amount of change in the resistance value of the processed wafer 10.

[0053] Even when the acquisition probe 12 is not grounded, the electrical signal at the acquisition probe 12 will still change with the change in the resistance value of the processed wafer 10, thus reflecting the amount of change in the resistance value of the processed wafer 10. Therefore, the signal acquisition module 33 can be used to acquire the electrical signal on the acquisition probe 12 to reflect the amount of change in the resistance value of the processed wafer 10.

[0054] Whether the acquisition probe 12 is grounded or not, the difference between the signal at the discharge probe 11 and the signal at the acquisition probe 12, such as the voltage signal, will also change with the change in the resistance value of the processed wafer 10. Therefore, the signal acquisition module 33 can be used to acquire the electrical signal between the discharge probe 11 and the acquisition probe 12 to reflect the amount of change in the resistance value of the processed wafer 10.

[0055] In this embodiment of the invention, when the insulating layer on the surface of the wafer 10 being processed is broken down, the resistance value of the wafer 10 changes, and the electrical signal acquired by the signal acquisition module changes accordingly. The electrical signal can be used to determine whether the insulating layer on the surface of the wafer 10 has been broken down. Specifically, in operation, the wafer electrostatic treatment system of this embodiment first contacts the discharge probe 11 and the acquisition probe 12 with the surface of the wafer 10 being processed. Then, the breakdown module applies a voltage to the surface of the wafer 10 through the discharge probe 11, and the signal acquisition module simultaneously generates an electrical signal. As the breakdown progresses, the resistance value of the wafer 10 gradually decreases, and the electrical signal changes, such as the voltage signal decreasing. The electrical signal is converted into the resistance value of the wafer 10 being processed. Once the wafer 10 reaches the required resistance value, it indicates that the insulating layer on the surface of the wafer 10 has been broken down. Then, the voltage applied to the wafer 10 can be stopped to prevent damage to the wafer 10.

[0056] The wafer electrostatic treatment system of the embodiment of the utility model, because of having signal acquisition module, carries out real time electric signal sampling while carrying out breakdown work in electric breakdown module, to determine the breakdown state of the surface insulating layer of the wafer 10 being treated in real time, sampling in time, and further can know whether the wafer 10 being treated is broken down in time, can grasp the process and effect of breakdown in real time, simultaneously, the wafer electrostatic treatment system can control the work of electric breakdown module according to the sampling result, and further makes the breakdown process and electrostatic release process controllable, and furthermore, the wafer electrostatic treatment system also does not need to wait for the process of the existing scheme of collecting after breakdown, improves the speed of the whole electric breakdown process.

[0057] Furthermore, in the embodiment of the utility model, signal acquisition module 33 needs to cooperate with two probes to collect, signal acquisition module 33 directly utilizes discharge probe 11 to form a collection circuit, and utilizes high voltage electricity provided by electric breakdown module 31 to work, without needing to set power module for signal acquisition module 33 alone, so that the wafer electrostatic treatment system is simple in structure, low in cost, but simultaneously realizes the beneficial effect that electric breakdown and electric signal collection are carried out synchronously.

[0058] In some embodiments of the utility model, the wafer electrostatic treatment system further includes a first switching device 32. The electric breakdown module 31 is electrically connected with the discharge probe 11 through the first switching device 32, and the signal acquisition module 33 is electrically connected with the discharge probe 11 through the first switching device 32. The first switching device 32 makes the electric breakdown module 31 and the signal acquisition module 33 conduct or disconnect with the discharge probe 11 at the same time. By such setting, the number of switching devices can be reduced, so that the wafer electrostatic treatment system is simple in structure, easy to control and low in cost.

[0059] In some embodiments of the utility model, the wafer electrostatic treatment system further includes a control module 20, and the control module 20 is electrically connected with the signal acquisition module 33 and the first switching device 32. The control module 20 is configured to: control the first switching device to make the electric breakdown module 31 and the signal acquisition module 33 conduct with the discharge probe 11 at the same time; and according to the electric signal, control the first switching device 32 to make the electric breakdown module 31 and the signal acquisition module 33 disconnect with the discharge probe 11 at the same time.

[0060] In some embodiments of the utility model, as shown in Figure 2 The wafer electrostatic treatment system further includes a second switching device 34, and the second switching device 34 is between the signal acquisition module 33 and the collection probe 12, so as to make the signal acquisition module 33 conduct or disconnect with the collection probe 12. Further, the control module is further configured to control the second switching device 34 to make the signal acquisition module 34 conduct with the collection probe 12 when the electric breakdown module 31 conducts with the discharge probe 11.

[0061] That is, the control module is configured to, when the electric breakdown is needed, make the electric breakdown module 31 controlled to be in electrical communication with the discharge probe 11 to electrically breakdown the insulating layer on the surface of the wafer under processing 10, and make the signal acquisition module 33 controlled to be in electrical communication with the discharge probe 11 and the acquisition probe 12 at the same time to acquire the electrical signal between the discharge probe 11 and the acquisition probe 12 while electrically breaking down the insulating layer on the surface of the wafer under processing 10, and then the control module determines the breakdown state of the insulating layer on the surface of the wafer under processing 10 according to the electrical signal. And after determining that the insulating layer on the surface of the wafer under processing 10 is broken down, the control module makes the electric breakdown module 31 controlled to be disconnected with the discharge probe 11, stops applying voltage to the wafer under processing 10, and also makes the signal acquisition module 33 controlled to be disconnected with the discharge probe 11 and the acquisition probe 12 at the same time.

[0062] In the embodiments of the utility model, with the electric breakdown, the resistance of the wafer under processing 10 gradually becomes smaller, and the electrical signal changes, such as the voltage signal becomes smaller. The control module 20 converts the electrical signal into the resistance of the wafer under processing 10, and after the wafer under processing 10 reaches the required resistance, it indicates that the insulating layer on the surface of the wafer under processing 10 has been broken down. The control module 20 makes the electric breakdown module 31 disconnected with the discharge probe 11, and also makes the signal acquisition module 33 disconnected with the discharge probe 11 and the acquisition probe 12, to avoid continuously applying voltage to the wafer under processing 10 and causing damage to the wafer under processing 10.

[0063] In some embodiments of the utility model, as shown in Figure 2 The first switching device 32 is a first relay. The first relay is between the electric breakdown module 31 and the discharge probe 11, and between the signal acquisition module 33 and the discharge probe 11, to make the electric breakdown module 31 and the signal acquisition module 33 conductive or disconnected with the discharge probe 11 at the same time. The first relay is used to switch the electric breakdown module 31 and the signal acquisition module 33, and the first relay is electrically connected with the control module 20 and controlled to switch the opening and closing state by the control module 20. Here, the opening and closing state refers to the opening state and the closing state of the switching device, and switching the opening and closing state refers to switching between the opening state and the closing state. It should be understood that when the switching device is in the closing state, the corresponding branch is in the opening state, and when the switching device is in the opening state, the corresponding branch is in the disconnected state. The second switching device 34 is a second relay. The second relay is between the signal acquisition module 33 and the acquisition probe 12, to make the signal acquisition module 33 conductive or disconnected with the acquisition probe 12. The control module controls the second relay to switch the opening and closing state.

[0064] In some embodiments of the utility model, as shown in Figure 3As shown, the wafer electrostatic treatment system further comprises an electrostatic elimination module 37. The electrostatic elimination module 37 is controlled to be electrically connected with the discharge probe 11 and the collection probe 12 to apply a voltage to the wafer 10 to be treated through the discharge probe 11 and the collection probe 12.

[0065] Further, the control module 20 is further configured to cause the electrostatic elimination module 37 to be turned on at the same time with the discharge probe 11 and the collection probe 12 according to the electrical signal. That is, the control module 20 is further configured to cause the electrostatic elimination module to be controlled to be electrically connected with the discharge probe 11 and the collection probe 12 at the same time according to the electrical signal to apply a voltage for electrostatic discharge to the wafer 10 to be treated.

[0066] After the wafer 10 to be treated reaches the required resistance value, the control module 20 causes the electrical breakdown module 31 to be electrically disconnected with the discharge probe 11, and causes the real-time signal collection module 33 to be electrically disconnected with the discharge probe 11 and the collection probe 12 at the same time. Then, the control module 20 causes the electrostatic elimination module 37 to be controlled to be electrically connected with the discharge probe 11 and the collection probe 12 at the same time to apply a voltage for electrostatic discharge to the wafer 10 to be treated, to neutralize the static electricity on the surface of the wafer 10 to be treated, thereby electrostatically eliminating the wafer 10 to be treated and improving the electrostatic elimination speed.

[0067] In some embodiments of the utility model, the wafer electrostatic treatment system comprises a third switching device 35, a fourth switching device 36 and an electrostatic elimination module 37. The third switching device 35 is between the electrostatic elimination module 37 and the discharge probe 11 to control the on or off between the electrostatic elimination module 37 and the discharge probe 11, that is, when the electrostatic elimination module 37 needs to be turned on with the discharge probe 11, the third switching device 35 must be in the closed state of electrical conduction, when the third switching device 35 is in the open state of electrical disconnection, the electrostatic elimination module 37 and the discharge probe 11 must be disconnected, and the third switching device 35 can control the on or off between the electrostatic elimination module 37 and the discharge probe 11. The fourth switching device 36 is between the electrostatic elimination module 37 and the collection probe 12 to control the on or off between the electrostatic elimination module 37 and the collection probe 12. The third switching device 35 and the fourth switching device 36 are controlled to switch the on or off state by the control module 20.

[0068] In some preferred embodiments of the utility model, the third switching device 35 is between the first switching device 32 and the electrostatic elimination module 37 to make the electrostatic elimination module 37 be turned on with the discharge probe 11 when the third switching device 35 and the first switching device 32 are both turned on, and to make the electrostatic elimination module 37 be disconnected with the discharge probe 11 when at least one of the third switching device 35 and the first switching device 32 is turned off.

[0069] The fourth switch device 36 is between the second switch device 34 and the static elimination module 37, so that the static elimination module 37 is connected with the collection probe 12 when the fourth switch device 36 and the second switch device 34 are both turned on, and the static elimination module 37 is disconnected with the collection probe 12 when at least one of the fourth switch device 36 and the second switch device 34 is turned off.

[0070] In the embodiment of the utility model, for the connection circuit composed of the static elimination module 37 and the wafer 10 to be processed, the third switch device 35 and the first switch device 32 are connected in series, and the fourth switch device 36 and the second switch device 34 are connected in series, so that in each group of switch devices, any switch device is in an open state, and the corresponding probe does not apply voltage to the wafer 10 to be processed, which can provide double protection and prevent the wafer 10 to be processed from being damaged after applying the voltage for static discharge, especially in the case of applying high voltage for static discharge to the wafer 10 to be processed.

[0071] In some alternative embodiments of the utility model, the third switch device 35 can be directly arranged between the static elimination module 37 and the discharge probe 11 without the first switch device 32, and the fourth switch device 36 can be directly arranged between the static elimination module 37 and the collection probe 12 without the second switch device 34.

[0072] In some embodiments of the utility model, the third switch device 35 and the fourth switch device 36 can both be relays.

[0073] In some embodiments of the utility model, as shown in Figure 2 and Figure 3 The control module 20 includes a processing submodule 21 and an on-off control submodule 22. The signal acquisition module 33 is connected to the processing submodule 21 to provide an electrical signal to the processing submodule 21. The on-off control submodule 22 is connected to the processing submodule 21, and the processing submodule 21 controls each switch device through the on-off control submodule 22. That is, the processing submodule 21 controls the first switch device 32, the second switch device 34, the third switch device 35 and the fourth switch device 36 to switch the open and closed states through the on-off control submodule 22.

[0074] The processing submodule 21 includes, but is not limited to, a general processor, a special processor, a general processor, a digital signal processor (DSP), a plurality of microprocessors, one or more microprocessors associated with a DSP core, a controller, a microcontroller, an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) circuit, any other type of integrated circuit (IC), and a state machine, etc. The on-off control submodule 22 is mainly used for converting electrical signal instructions into control voltages that can switch the on-off state of each switching device. The on-off control submodule 22 can be composed of circuit modules with different functions, including, for example, filter circuits, amplification circuits, etc.

[0075] In some embodiments of the present application, the electrical breakdown module 31 can include a first power module, which is a device that converts electrical energy of one voltage value into electrical energy of another voltage value in a direct current circuit. The electrical breakdown module 31 can be connected to the power supply system 25 externally. In other embodiments of the present application, the electrical breakdown module 31 can be directly connected to the power supply system.

[0076] The control module 20 further includes a driving circuit submodule 23, which is arranged between the processing submodule 21 and the electrical breakdown module 31, i.e., the driving circuit submodule 23 is connected to the processing submodule 21, and the processing submodule 21 controls the electrical connection state between the electrical breakdown module 31 and the first switching device 32 through the driving circuit submodule 23. The driving circuit submodule 23 is a circuit that can drive the controlled components to act. In the embodiments of the present application, the driving circuit submodule 23 is mainly a circuit that drives the electrical breakdown module 31 to supply power to the first switching device 32. By setting the driving circuit submodule 23, the electrical breakdown module 31 can be effectively controlled.

[0077] In some embodiments of the present application, the control module 20 further includes a power module 24, which is connected to the processing submodule 21, and the power module 24 is externally connected to the power supply system 25. The power supply system 25 supplies power to the entire control module 20 through the power module 24, and the power supply system 25 can also supply power to the electrical breakdown module 31 and the static electricity elimination module 37 at the same time.

[0078] In some embodiments of the present application, as shown in Figure 4As shown, the electrical signal can be a voltage signal. The signal acquisition module 33 mainly includes an operational amplifier circuit 41. The operational amplifier circuit 41 is configured to acquire the voltage value on the discharge probe 11 or the voltage difference between the discharge probe 11 and the collection probe 12. When the voltage is applied by the electrical breakdown module 31, that is, when the electrical breakdown module 31 applies voltage to the wafer 10 to be processed through the discharge probe 11, the operational amplifier circuit 41 can reflect the voltage value at the discharge probe 11 or the voltage difference between the discharge probe 11 and the collection probe 12. When the resistance of the wafer 10 to be processed decreases, the voltage signal generated by the operational amplifier circuit 41 also decreases. Therefore, the operational amplifier circuit 41 can acquire the electrical signal in real time, that is, can reflect the breakdown state of the insulating layer on the surface of the wafer 10 to be processed in real time.

[0079] In some embodiments of the utility model, the operational amplifier circuit 41 can be based on the negative feedback characteristic of the operational amplifier. When the input signal is added to the non-inverting input terminal of the operational amplifier, the voltage difference between the inverting input terminal and the non-inverting input terminal of the operational amplifier tends to zero due to the large amplification of the operational amplifier. Therefore, the voltage of the inverting input terminal is equal to the voltage of the non-inverting input terminal, that is, equal to the input voltage. At the same time, since the feedback resistor is connected between the inverting input terminal and the output terminal of the operational amplifier, according to Ohm's law and Kirchhoff's current law, it can be deduced that the output voltage is equal to the input voltage. The operational amplifier circuit 41 can utilize the characteristics of the high-impedance operational amplifier chip to sample in a larger range under the condition of meeting the input condition.

[0080] In some embodiments of the utility model, when the signal acquisition module 33 is collecting, the wafer 10 to be processed needs to be grounded. The signal acquisition module 33 or the control module 20 includes a grounding terminal, and the collection probe 12 is configured to be in electrical communication with the grounding terminal, so that the wafer 10 to be processed is grounded through the collection probe 12 and the signal acquisition module 33.

[0081] In some embodiments of the utility model, as shown in Figure 4 The signal acquisition module 33 further includes an operational amplifier circuit protection resistor 42. The operational amplifier circuit protection resistor 42 is arranged between the discharge probe 11 and the input terminal of the operational amplifier circuit. The power supply protection resistor 43 is arranged between the electrical breakdown module 31 and the first switching device 32. By arranging the operational amplifier circuit protection resistor 42 and the power supply protection resistor 43, in the case that the voltage provided by the electrical breakdown module 31 is relatively large, the control module 20 and the signal acquisition module 33 are prevented from being damaged by overvoltage, etc.

[0082] The utility model embodiment further provides a semiconductor detection equipment, it includes equipment main part and wafer electrostatic treatment system in any embodiment above. Wafer electrostatic treatment system sets up on equipment main part. Equipment main part is used to accommodate the wafer 10 being handled to promote the wafer 10 being handled and discharge probe 11 and collection probe 12 electric connection. Specifically, discharge probe 11 and collection probe 12 are respectively in the surface of the wafer 10 being handled two different positions and the surface contact of the wafer 10 being handled.

[0083] In some embodiments of the utility model, the semiconductor detection equipment is a charged particle beam imaging device. The charged particle beam imaging device controls the focusing state of the charged particles to make the charged particles interact with the semiconductor sample, and performs imaging by capturing particle signals such as secondary particles and transmission particles. The information such as the morphology, structure, and composition of the sample can be characterized. Common charged particle beam imaging devices include scanning electron microscopes, transmission electron microscopes, and focused ion beam microscopes.

[0084] At this point, those skilled in the art should recognize that, although the utility model has been shown and described in detail herein, many other variations or modifications consistent with the principles of the utility model can be directly determined or deduced from the disclosure of the utility model without departing from the spirit and scope of the utility model. Therefore, the scope of the utility model should be understood and recognized as covering all these other variations or modifications.

Claims

1. A wafer electrostatic treatment system, characterized in that, The system comprises: a discharge probe configured to contact a surface of a wafer under processing at a position of the surface of the wafer under processing; an electrical breakdown module electrically connected with the discharge probe to electrically shock the wafer under processing through the discharge probe; a collection probe configured to contact the surface of the wafer under processing at another position of the surface of the wafer under processing; a signal collection module electrically connected with both the discharge probe and the collection probe, the signal collection module configured to collect an electrical signal on the discharge probe, or to collect an electrical signal on the collection probe, or to collect an electrical signal between the discharge probe and the collection probe.

2. The wafer electrostatic processing system of claim 1, wherein Further comprising: a first switching device, the electrical breakdown module being electrically connected with the discharge probe through the first switching device, and the signal collection module being electrically connected with the discharge probe through the first switching device, so that the electrical breakdown module and the signal collection module are simultaneously turned on or turned off with the discharge probe.

3. The wafer electrostatic processing system of claim 2, wherein, Further comprising: a second switching device between the signal collection module and the collection probe, so that the signal collection module is turned on or turned off with the collection probe.

4. The wafer electrostatic processing system of claim 3, wherein Further comprising: an electrostatic elimination module controllably electrically connected with the discharge probe and the collection probe to apply a voltage to the wafer under processing through the discharge probe and the collection probe.

5. The wafer electrostatic processing system of claim 4, wherein Further comprising: a third switching device between the electrostatic elimination module and the discharge probe to control the turning on or turning off between the electrostatic elimination module and the discharge probe; a fourth switching device between the electrostatic elimination module and the collection probe to control the turning on or turning off between the electrostatic elimination module and the collection probe.

6. The wafer electrostatic processing system according to claim 5, wherein: the third switching device is between the first switching device and the electrostatic elimination module, so that the electrostatic elimination module is turned on with the discharge probe when both the third switching device and the first switching device are turned on, and the electrostatic elimination module is turned off with the discharge probe when at least one of the third switching device and the first switching device is turned off; the fourth switching device is between the second switching device and the electrostatic elimination module, so that the electrostatic elimination module is turned on with the collection probe when both the fourth switching device and the second switching device are turned on, and the electrostatic elimination module is turned off with the collection probe when at least one of the fourth switching device and the second switching device is turned off.

7. The wafer electrostatic processing system of claim 5, wherein, Further comprising a control module, the control module comprising: a processing submodule, the signal collection module being connected to the processing submodule to provide the electrical signal to the processing submodule; A turn-on / off control sub-module is connected to the processing sub-module, and the processing sub-module controls the first, second, third and fourth switch devices through the turn-on / off control sub-module; A driving circuit sub-module is arranged between the processing sub-module and the electrical breakdown module, so that the processing sub-module controls the electrical breakdown module through the driving circuit sub-module.

8. The wafer electrostatic processing system according to claim 7, wherein The electrical signal is a voltage signal; The signal acquisition module comprises an operational amplifier circuit configured to acquire the voltage value on the discharge probe or the voltage difference between the discharge probe and the acquisition probe.

9. The wafer electrostatic processing system according to claim 8, wherein The signal acquisition module or the control module comprises a grounding terminal, and the acquisition probe is configured to be in electrical communication with the grounding terminal, so that the processed wafer is grounded through the acquisition probe and the signal acquisition module.

10. The wafer electrostatic processing system according to claim 8, wherein The signal acquisition module further comprises an operational amplifier circuit protection resistor arranged between the discharge probe and the input terminal of the operational amplifier circuit; A power supply protection resistor is arranged between the electrical breakdown module and the discharge probe.

11. A semiconductor inspection apparatus characterized by comprising: comprising: A device body for accommodating a processed wafer; The wafer electrostatic processing system according to any one of claims 1 to 10 is arranged on the device body, and the discharge probe and the acquisition probe are respectively in contact with the surface of the processed wafer at two different positions on the surface of the processed wafer.

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