Circuit supporting multipath ADPCM hardware operation
By designing a circuit that supports hardware operations for multiple ADPCM channels and utilizing module collaboration and parallel processing techniques, the problems of low efficiency and poor scalability in existing ADPCM multi-channel decoding have been solved, resulting in a high-efficiency and stable multi-channel audio decoding solution.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-27
- Publication Date
- 2026-03-31
AI Technical Summary
Existing technologies for ADPCM multi-channel decoding suffer from insufficient hardware coordination, low decoding efficiency, poor scalability, imperfect timing control, and high data processing latency, making it difficult to meet the real-time and flexibility requirements of multi-channel audio decoding.
A circuit supporting multi-channel ADPCM hardware operation was designed, including an ADPCM arithmetic unit, a cache selection module, an arithmetic counter, an index and presample cache module, and a timing control module. Through the collaborative work between the modules, automated multi-channel ADPCM decoding is achieved. A dual-port memory and a FIFO buffer are used for parallel processing to ensure timing synchronization and data rate matching.
It significantly improves ADPCM decoding efficiency, supports flexible multi-channel expansion, ensures the stability and real-time performance of the decoding process, improves hardware resource utilization, and adapts to the needs of complex multi-channel audio decoding scenarios.
Smart Images
Figure CN224067211U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of audio processing circuit design, and in particular to a circuit that supports multi-channel ADPCM hardware operation. Background Technology
[0002] With the rapid development of audio processing technology, scenarios such as multimedia interaction and audio communication systems place higher demands on multi-channel audio decoding. As a high-efficiency audio compression coding technology, the hardware implementation of multi-channel decoding for ADPCM has become a key breakthrough. Traditional audio decoding solutions, due to outdated architecture and insufficient hardware coordination, struggle to meet the efficiency and flexibility requirements of modern audio systems when dealing with multi-channel ADPCM decoding, making the development of new hardware circuit designs an urgent industry need.
[0003] Existing technologies for ADPCM multi-channel decoding suffer from significant hardware-level deficiencies. On one hand, many solutions rely on software to participate in the decoding process, such as software-controlled parameter switching and computation scheduling, resulting in low decoding efficiency and an inability to meet the demands of real-time scenarios. On the other hand, the lack of efficient collaboration mechanisms between hardware modules, such as the ADPCM arithmetic unit and parameter buffer, leads to poor interoperability, resulting in high data processing latency, wasted hardware resources, and an inability to handle the task pressure of concurrent decoding of multiple audio streams.
[0004] On the other hand, existing solutions lack scalability and stability. The fixed circuit architecture requires hardware redesign when expanding decoding paths, resulting in high costs and low flexibility. The imperfect timing control mechanism easily leads to parameter extraction misalignment and chaotic operation timing during multi-path round-robin decoding, causing decoding errors and affecting audio quality. Furthermore, the lack of optimization in details such as data rate matching and parallel buffer read / write processing further limits the performance of the decoding circuit, making it unsuitable for complex multi-channel audio decoding scenarios and hindering the overall efficiency of the audio processing system. Summary of the Invention
[0005] In order to overcome the shortcomings and deficiencies of the existing technology, this application proposes a circuit that supports multi-channel ADPCM hardware operation.
[0006] A circuit that supports multi-channel ADPCM hardware operation includes an ADPCM arithmetic unit, a cache selection module, an operation counter, an index and presample cache module, and an index and presample cache setting module.
[0007] The ADPCM processor is connected to the ADPCM compressed value input unit, the cache selection module, and the PCM value output unit, respectively.
[0008] The cache selection module is connected to the Index and Presample cache module and the operation counter; the operation counter is connected to the Index and Presample cache setting module and the ADPCM operator.
[0009] The Index and Presample cache setting module is connected to the Index and Presample cache module. The ADPCM compression value input unit is used to input the ADPCM compression value. The cache selection module selects the corresponding storage unit in the Index and Presample cache modules based on the value of the operation counter, extracts the Index value and Presample value, and inputs them to the ADPCM processor. The ADPCM processor performs calculations based on the input ADPCM compression value, Index value, and Presample value, outputs the PCM value to the PCM value output unit, and simultaneously drives the operation counter to count. The Index and Presample cache setting module controls the cyclic counting value of the operation counter, clearing it to 0 when the count value reaches the preset number of channels, thus achieving cyclic counting. The operation counter controls the cache selection module to extract and store the Index and Presample cache positions, completing the round-robin processing of multi-channel ADPCM decoding.
[0010] Furthermore, the Index and Presample cache module includes multiple storage units, each corresponding to the Index value storage area and Presample value storage area for one audio decoding path; the number of storage units matches the number of audio paths supported for decoding, and when it is necessary to expand the decoding path, the size of the cyclic Index table is modulated by increasing the number of storage units.
[0011] Furthermore, the cache selection module includes a multiplexing circuit. The input port of the multiplexing circuit is connected to the output of each storage unit of the Index and Presample cache modules, and the control port is connected to the counting output of the arithmetic counter. The counting value output by the arithmetic counter serves as a selection signal, driving the multiplexing circuit to select the Index value and Presample value of the corresponding storage unit from the Index and Presample cache modules and input them to the ADPCM arithmetic unit.
[0012] Furthermore, the operation counter is a programmable counter, which includes a counting module, a comparison module, and a clearing module. The counting module accumulates the count after each ADPCM operation. The comparison module compares the count value with the index and the path number threshold preset by the Presample cache setting module. When the count value reaches the threshold, the clearing module clears the counting module, forming a cyclic counting mechanism.
[0013] Furthermore, the Index and Presample cache setting module includes a register group, which is used to store preset channel number parameters. When two-channel decoding needs to be configured, the register group stores a threshold of 2, and the operation counter is triggered to be cleared when it counts to 2. When multi-channel decoding needs to be configured, the threshold parameters in the register group are modified to adapt to different channel number requirements.
[0014] Furthermore, the ADPCM operator integrates a data processing unit and a state update unit. The data processing unit performs ADPCM decoding operations based on the input ADPCM compressed value, Index value, and Presample value to generate a PCM value. The state update unit updates the Index value and Presample value according to the operation result and controls the storage of the updated Index value and Presample value into the corresponding storage units in the Index and Presample cache modules.
[0015] Furthermore, it also includes a timing control module, which is connected to the ADPCM arithmetic unit, the buffer selection module, and the arithmetic counter. The timing control module generates a synchronization clock signal to control the timing synchronization of ADPCM compressed value input, Index and Presample value extraction, ADPCM arithmetic, PCM value output, and counting operations, ensuring the orderly execution of the multi-path decoding process.
[0016] Furthermore, the Index and Presample cache module adopts a dual-port memory design, with one port used by the cache selection module to read the Index and Presample values, and the other port used by the ADPCM arithmetic unit to write the updated Index and Presample values, thus completing the parallel processing of read and write operations.
[0017] Furthermore, a data buffer is provided between the ADPCM compressed value input unit and the ADPCM processor. The data buffer is used to cache the input ADPCM compressed values and match the input rate of ADPCM compressed values for different channels with the processing rate of the ADPCM processor.
[0018] Furthermore, the PCM value output unit integrates a FIFO buffer, which is used to buffer the PCM values output by the ADPCM operator, supporting the sequential output of PCM values after multi-channel decoding to meet the timing requirements of subsequent audio processing modules.
[0019] Beneficial effects:
[0020] This invention proposes a circuit that supports multi-channel ADPCM hardware operation. The application boasts outstanding hardware automation capabilities. Through the collaborative operation of modules such as a cache selection module, an operation counter, and an ADPCM arithmetic unit, it can automatically complete ADPCM compressed value input, Index and Presample value extraction, decoding operation, and result storage without software intervention, significantly improving decoding efficiency. Multi-channel expansion is flexible and convenient. Based on the storage unit design of the Index and Presample cache modules, the size of the cyclic Index table can be easily adjusted by simply increasing the number of storage units, easily adapting to the decoding needs of two or more audio channels, demonstrating strong scalability. The circuit architecture is optimized and efficient. The dual-port memory design enables parallel processing of cache read and write operations. The timing control module ensures timing synchronization of each stage, and the data buffer and FIFO buffer coordinate data rates to avoid data loss and ensure ordered output. The cyclic control mechanism is stable. The operation counter, combined with the cache setting module, forms a cyclic count, precisely controlling the cache position extraction and storage, ensuring stable and reliable multi-channel decoding rotation. This meets real-time requirements while improving hardware resource utilization, providing an efficient, flexible, and stable ADPCM decoding solution for multi-audio channel scenarios. Attached Figure Description
[0021] Figure 1 This is a circuit module composition diagram of this utility model. Detailed Implementation
[0022] It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. The following describes the application in further detail with reference to the accompanying drawings and specific embodiments.
[0023] Figure 1 As shown, a circuit supporting multi-channel ADPCM hardware operation includes an ADPCM arithmetic unit, a cache selection module, an operation counter, an Index and Presample cache module, and an Index and Presample cache setting module.
[0024] This circuit uses hardware module collaboration as its core to construct a multi-channel ADPCM decoding system. The ADPCM arithmetic unit is the main body for decoding operations, the cache selection module is responsible for parameter extraction, the operation counter controls the channel switching rhythm, the Index and Presample cache modules store the decoding parameters of each channel, and the Index and Presample cache setting modules are used to configure the channel parameter thresholds. The five modules work together to form a complete multi-channel decoding link.
[0025] The ADPCM arithmetic unit is connected to the ADPCM compressed value input unit, the cache selection module, and the PCM value output unit, respectively; the cache selection module is connected to the Index and Presample cache module and the arithmetic counter; the arithmetic counter is connected to the Index and Presample cache setting module and the ADPCM arithmetic unit; and the Index and Presample cache setting module is connected to the Index and Presample cache module.
[0026] The ADPCM processor acts as the central hub, receiving compressed data from the ADPCM compressed value input unit, obtaining decoding parameters (Index value, Presample value) from the buffer selection module, and outputting the decoded PCM value to the PCM value output unit. The buffer selection module relies on the count result of the operation counter to accurately select parameters for the corresponding path from the Index and Presample buffer modules. The operation counter is driven by the ADPCM processor and controlled by thresholds from the Index and Presample buffer setting modules, forming a counting cycle. The Index and Presample buffer setting modules directly configure the storage rules of the Index and Presample buffer modules to ensure that parameter storage matches the number of paths.
[0027] The ADPCM compression value input unit is used to input ADPCM compression values. The cache selection module selects the corresponding storage unit in the Index and Presample cache modules based on the value of the operation counter, extracts the Index and Presample values, and inputs them to the ADPCM processor. The ADPCM processor performs calculations based on the input ADPCM compression value, Index value, and Presample value, outputs the PCM value to the PCM value output unit, and simultaneously drives the operation counter to count. The Index and Presample cache setting module controls the cyclic count value of the operation counter. When the count value reaches the preset number of channels, it is cleared to 0 to achieve cyclic counting. The operation counter controls the cache selection module to extract and store the Index and Presample cache positions, completing the round-robin processing of multi-channel ADPCM decoding.
[0028] The ADPCM compressed value input unit serves as the data entry point, continuously inputting data to be decoded. The cache selection module acts as a "parameter scheduler," retrieving historical parameters (Index value, Presample value) for the corresponding channel from the Index and Presample cache modules based on the count value of the operation counter (e.g., a count value of 0 selects channel 0, a count value of 1 selects channel 1). The ADPCM operator merges the compressed value and parameters, performs decoding operations, outputs the PCM value, and simultaneously triggers the operation counter to increment by 1. When the count value reaches the preset number of channels in the Index and Presample cache setting modules (e.g., a count value of 2 for two channels), the counter is cleared to 0, returning to the initial counting state, driving the cache selection module to cyclically switch storage locations, ultimately achieving multi-channel decoding in a round-robin manner, processing data from each channel sequentially like an assembly line.
[0029] The Index and Presample caching module includes multiple storage units, each corresponding to the Index value storage area and Presample value storage area for one audio decoding path; the number of storage units matches the number of audio paths supported for decoding, and when it is necessary to expand the decoding path, the size of the cyclic Index table is modulated by increasing the number of storage units.
[0030] This module acts as a "database" for multi-channel parameters. Each storage unit is dedicated to one audio decoding channel, independently storing the index value (decoding index parameter) and presample value (decoding preset sample value) for that channel. For example, when decoding two channels, the module contains two storage units; if it needs to be expanded to four channels, only two more storage units need to be added, without large-scale changes to the circuit. By flexibly adding or removing storage units, it can easily adapt to different channel requirements, demonstrating the scalability of the hardware design.
[0031] The cache selection module includes a multiplexing circuit. The input port of the multiplexing circuit is connected to the output of each storage unit of the Index and Presample cache modules, and the control port is connected to the count output of the arithmetic counter. The count value output by the arithmetic counter serves as a selection signal, driving the multiplexing circuit to select the Index value and Presample value of the corresponding storage unit from the Index and Presample cache modules and input them to the ADPCM arithmetic unit.
[0032] The core of the cache selection module is a multiplexer circuit. Its input ports connect to the outputs of each storage unit in the Index and Presample cache modules, acting like multiple data channels. The count value of the operation counter serves as the "selection instruction." For example, when the count value is 1, the multiplexer circuit receives the instruction and immediately connects the output channel of storage unit 1, accurately sending the Index and Presample values of that unit to the ADPCM arithmetic unit. This ensures that the correct path parameters are called in each round of calculation, achieving automatic switching of multi-path parameters.
[0033] The operation counter is a programmable counter, which includes a counting module, a comparison module, and a clearing module. The counting module accumulates the count after each ADPCM operation. The comparison module compares the count value with the index and the path number threshold preset by the Presample cache setting module. When the count value reaches the threshold, the clearing module clears the counting module, forming a cyclic counting mechanism.
[0034] The operation counter acts as the "rhythm controller" for multi-path decoding. After each ADPCM operation, the counting module increments the count like a clockwork mechanism. The comparison module monitors the count in real time and compares it with the preset path number threshold (e.g., 2 for two paths) set by the Index and Presample cache setting modules. When the count reaches the threshold, the reset module immediately activates, resetting the count to 0, forming a "count-compare-reset" loop mechanism. This mechanism ensures that the count circulates within the path number range, precisely controlling the switching rhythm of the cache selection module.
[0035] The Index and Presample cache setting module includes a register group, which is used to store preset channel number parameters. When two-channel decoding needs to be configured, the register group stores a threshold of 2, and the operation counter is reset when it counts to 2. When multi-channel decoding needs to be configured, the threshold parameters in the register group are modified to adapt to different channel number requirements.
[0036] This module serves as the "control center" for channel configuration, storing key parameters through a register set. Taking two-channel decoding as an example, when the register set is written with a threshold of 2, the operation counter automatically resets to zero when it reaches 2. To upgrade to three channels, simply change the register set threshold to 3, and the operation counter will then cycle according to the new rule. This design allows for flexible and controllable channel configuration, eliminating the need to modify hardware circuitry; different scenarios can be adapted simply by modifying register parameters in software.
[0037] The ADPCM processor integrates a data processing unit and a state update unit. The data processing unit performs ADPCM decoding operations based on the input ADPCM compressed value, Index value, and Presample value to generate PCM values. The state update unit updates the Index value and Presample value according to the operation results and controls the storage of the updated Index value and Presample value into the corresponding storage units in the Index and Presample cache modules.
[0038] The ADPCM processor employs a "dual-unit collaborative" architecture. The data processing unit is the executor of the decoding operation, much like a factory production line, processing the input ADPCM compressed value, Index value, and Presample value according to the ADPCM algorithm and outputting the PCM value. The state update unit acts as a "parameter manager," updating the Index value and Presample value (dynamic parameters required for decoding) based on the operation results, and precisely controlling the storage of the new parameters in the corresponding storage units of the Index and Presample cache modules, preparing the latest parameters for the next round of decoding of that path, and ensuring the continuity of the decoding process.
[0039] It also includes a timing control module, which is connected to the ADPCM arithmetic unit, the buffer selection module, and the arithmetic counter. The timing control module generates a synchronization clock signal to control the timing synchronization of ADPCM compressed value input, Index and Presample value extraction, ADPCM arithmetic, PCM value output, and counting operations, ensuring the orderly execution of the multi-path decoding process.
[0040] The timing control module acts as the circuit's "time manager," generating a synchronized clock signal to set a unified time reference for the operation of each module. For example, on the rising edge of the clock, the ADPCM compression value input unit receives data, the buffer selection module synchronously extracts parameters, the ADPCM arithmetic unit starts calculations, the PCM value output unit receives the results, and the arithmetic counter performs counting. Through strict timing synchronization, data conflicts or operational chaos are avoided, ensuring that multi-path decoding behaves like a precise mechanical clock, with each step executing at the correct time.
[0041] The Index and Presample cache module adopts a dual-port memory design. One port is used for the cache selection module to read the Index value and the Presample value, and the other port is used for the ADPCM arithmetic unit to write the updated Index value and the Presample value, thus completing the parallel processing of read and write operations.
[0042] The dual-port memory design enables the Index and Presample cache modules to perform dual functions. One port is dedicated to outputting parameters to the cache selection module (read operation), while the other port independently receives updated parameters written by the ADPCM arithmetic unit (write operation). This parallel processing mechanism breaks the traditional memory read-write mutual exclusion limitation, allowing read and write operations to be performed simultaneously, significantly improving parameter access efficiency and avoiding decoding latency caused by read-write waiting.
[0043] A data buffer is provided between the ADPCM compressed value input unit and the ADPCM processor. The data buffer is used to cache the input ADPCM compressed values and match the input rate of ADPCM compressed values of different channels with the processing rate of the ADPCM processor.
[0044] The data buffer acts as a "buffer" for data transmission. When the input rate of ADPCM compressed values from different channels does not match the processing rate of the ADPCM processor (e.g., the input rate is faster than the processing rate), the buffer temporarily stores the compressed values, much like a reservoir regulating water flow. After the processor finishes processing the current data, it retrieves subsequent data from the buffer, preventing data loss or computational errors due to rate differences and ensuring the stability of the decoding process.
[0045] The PCM value output unit integrates a FIFO buffer, which is used to buffer the PCM values output by the ADPCM operator. It supports the sequential output of PCM values after multi-channel decoding to meet the timing requirements of subsequent audio processing modules.
[0046] The FIFO (First-In, First-Out) buffer acts as the "order maintainer" for PCM value output. During multi-channel decoding, the PCM values of each channel are stored in the buffer in the order they are decoded. Subsequent audio processing modules read them in the same order, ensuring that the data output timing matches the processing requirements. For example, the PCM values of channels decoded first are output first, and those decoded later are output later, avoiding data corruption, adapting to the fixed timing flow of downstream audio processing modules, and ensuring the coordination of the entire audio processing system.
[0047] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application. Therefore, if such modifications and variations fall within the scope of this application and its equivalents, this application intends to include such modifications and variations.
[0048] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various equivalent changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A circuit supporting multi-channel ADPCM hardware operation, characterized in that, The ADPCM operator, the cache selection module, the operation counter, the Index and Presample cache module, and the Index and Presample cache setting module are included. The ADPCM operator is connected with the ADPCM compression value input unit, the cache selection module, and the PCM value output unit. The cache selection module is connected with the Index and Presample cache module and the operation counter, and the operation counter is connected with the Index and Presample cache setting module and the ADPCM operator. The Index and Presample cache setting module is connected with the Index and Presample cache module. The ADPCM compression value input unit is used to input the ADPCM compression value. The cache selection module selects the corresponding storage unit in the Index and Presample cache module according to the value of the operation counter, extracts the Index value and the Presample value, and inputs them to the ADPCM operator. The ADPCM operator performs operation based on the input ADPCM compression value, Index value, and Presample value, outputs the PCM value to the PCM value output unit, and drives the operation counter to count. The Index and Presample cache setting module controls the loop count value of the operation counter, and clears 0 when the count value reaches the preset channel number, to realize loop counting. The operation counter controls the cache selection module to extract and store the Index and Presample cache positions, and completes the rotation processing of multi-channel ADPCM decoding.
2. The circuit of claim 1, wherein, The Index and Presample cache module includes a plurality of storage units, each of which corresponds to an Index value storage area and a Presample value storage area of one audio decoding channel. The number of storage units matches the number of audio channels supported by decoding. When it is necessary to expand the decoding channel, the size of the loop Index table is modulated by increasing the number of storage units.
3. The circuit of claim 1, wherein The cache selection module includes a multi-channel selection circuit. The input port of the multi-channel selection circuit is connected with the output end of each storage unit of the Index and Presample cache module, and the control port is connected with the count output end of the operation counter. The count value output by the operation counter is used as a selection signal to drive the multi-channel selection circuit to select the Index value and the Presample value of the corresponding storage unit from the Index and Presample cache module and input them to the ADPCM operator.
4. The circuit of claim 1, wherein The operation counter is a programmable counter, including a counting module, a comparison module, and a clear module. The counting module accumulates the count after each ADPCM operation. The comparison module compares the count value with the threshold value of the number of channels preset by the Index and Presample cache setting module. When the count value reaches the threshold value, the clear module performs a clear operation on the counting module, forming a loop counting mechanism.
5. The circuit of claim 1, wherein The Index and Presample cache setting module includes a register group for storing a preset channel number parameter; when two-channel decoding is required, the register group stores a threshold value of 2, and the operation counter counts to 2 to trigger zero clearing; when multi-channel decoding is required, the threshold parameter in the register group is modified to adapt to different channel number requirements.
6. The circuit of claim 1, wherein The ADPCM operator internally integrates a data processing unit and a state updating unit; the data processing unit performs ADPCM decoding operation based on the input ADPCM compressed value, Index value and Presample value to generate a PCM value; The state updating unit updates the Index value and Presample value according to the operation result, and controls the storage of the updated Index value and Presample value in the corresponding storage unit of the Index and Presample cache module.
7. The circuit of claim 1, wherein It also includes a timing control module connected with the ADPCM operator, the cache selection module and the operation counter; the timing control module generates a synchronous clock signal to control the timing synchronization of ADPCM compressed value input, Index and Presample value extraction, ADPCM operation, PCM value output and counting operation, ensuring the orderly execution of the multi-channel decoding process.
8. The circuit of claim 1, wherein The Index and Presample cache module adopts a dual-port memory design, one port of which is used for the Index value and Presample value reading by the cache selection module, and the other port is used for the ADPCM operator to write the updated Index value and Presample value, completing parallel processing of read and write operations.
9. The circuit of claim 1, wherein A data buffer is arranged between the ADPCM compressed value input unit and the ADPCM operator, which is used to buffer the input ADPCM compressed value, matching the input rate of different channel ADPCM compressed values and the processing rate of the ADPCM operator.
10. The circuit of claim 1, wherein The PCM value output unit integrates a FIFO buffer, which is used to buffer the PCM value output by the ADPCM operator, supports the sequential output of the PCM value after multi-channel decoding, and meets the timing requirements of the subsequent audio processing module.