Grid driving control circuit, display driving chip, display panel and display device

Abstract

The utility model provides a grid driving control circuit, a display driving chip, a display panel and a display device. The circuit comprises a plurality of gate drive control units, each gate drive control unit comprises a decoding module, an electric balance control module, an electric balance function module and a signal output module, and the decoding module is used for outputting a decoding output signal according to a digital control signal; the electric balance control module is used for generating a function control signal according to the digital control signal and the electric balance starting signal; the electric balance function module is used for opening or closing an electric balance function according to the function control signal, and controlling the signal output module to increase an intermediate voltage between the lowest voltage and the highest voltage of the gate driving signal under the condition that the electric balance function is opened; and the signal output module is used for outputting a gate driving signal according to the decoding output signal under the condition that the electric balance function is closed, so that the area of a display driving chip is reduced.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display driving, and particularly relates to a gate driving control circuit, a display driving chip, a display panel and a display device. BACKGROUND

[0002] In a display device, a timing controller outputs a digital control signal for controlling the working timing of a gate driving control circuit according to a display control signal. A gate on array (GOA) circuit generally includes a plurality of GOA sub-circuits, and each GOA sub-circuit outputs a scanning signal to one or more rows of pixel units in a display panel to control the opening and closing of the one or more rows of pixel units. The gate driving control circuit can be provided with n (n is an integer greater than 0) gate driving control units, each of which can be connected to one or more GOA sub-circuits and receive k (k is an integer greater than 0, for example, k=3) digital control signals, open or close the EQ function according to the k digital control signals, and output a gate driving signal meeting the level requirement of the corresponding GOA sub-circuit in the case of opening or closing the EQ function. By opening the EQ function, an intermediate voltage can be added between the lowest voltage and the highest voltage of the gate driving signal, and the transition between the lowest voltage and the highest voltage is completed through the intermediate voltage, thereby reducing the power consumption of the gate driving control circuit for driving the display panel. However, the n gate driving control units need to receive k*n digital control signals. The timing controller and the gate driving control circuit are usually far apart in chip layout, and a long wiring distance is required. Therefore, although the addition of the EQ function in the gate driving control circuit can reduce the power consumption, it increases the chip area of the gate driving control circuit, thereby increasing the area of the display driving chip. UTILITY MODEL CONTENT

[0003] In view of the above problems, the present disclosure provides a gate driving control circuit, a display driving chip, a display panel and a display device, which aims to reduce the chip area of the gate driving control circuit while reducing the power consumption through the EQ function, thereby reducing the area of the display driving chip.

[0004] According to a first aspect of the present disclosure, a gate driving control circuit is provided, comprising:

[0005] a plurality of gate driving control units, each of which includes a decoding module, a level balance control module, a level balance function module and a signal output module, wherein,

[0006] the decoding module is configured to output a decoding output signal according to a digital control signal;

[0007] the level balance control module is configured to generate a function control signal according to the digital control signal and a level balance opening signal;

[0008] The power balancing function module is used to turn the power balancing function on or off according to the function control signal. When the power balancing function is on, the signal output module is controlled to add an intermediate voltage between the lowest and highest voltages of the gate drive signal.

[0009] The signal output module is used to output a gate drive signal according to the decoded output signal when the power balance function is turned off.

[0010] Optionally, the digital control signal is a 2-bit binary signal, including a 0th bit signal and a 1st bit signal. The power balance control module generates a function control signal based on the digital control signal and the power balance activation signal, including:

[0011] The electrical balance control module receives the digital control signal and the electrical balance activation signal, and generates the functional control signal based on the digital control signal and the electrical balance activation signal.

[0012] Optionally, the power balance control module includes an AND gate, a level converter, a first NOT gate, and a second NOT gate. The input of the AND gate receives the inverted signals of the 0th bit signal and the 1st bit signal. The output of the AND gate is connected to the input of the level converter, and the output of the level converter provides a first function control signal.

[0013] The input of the first NOT gate receives the electrical balance activation signal, and the output provides a second function control signal;

[0014] The input of the second NOT gate receives the electrical balance enable signal, and the output provides a third function control signal.

[0015] Optionally, the digital control signal is a 2-bit binary signal, including a 0th bit signal and a 1st bit signal. The power balance control module generates a function control signal based on the digital control signal and the power balance activation signal, including:

[0016] The power balance control module receives the digital control signal, generates the power balance activation signal based on the digital control signal, and generates the function control signal based on the digital control signal and the power balance activation signal.

[0017] Optionally, the power balance control module includes an AND gate, a level converter, a first NOT gate, a second NOT gate, a third NOT gate, and a D flip-flop. The input of the AND gate receives the inverted signals of the 0th bit signal and the 1st bit signal. The output of the AND gate is connected to the input of the level converter, and the output of the level converter provides a first function control signal.

[0018] The reset terminal of the D flip-flop receives the 0th bit signal, the clock signal input terminal receives the 1st bit signal, the Q output terminal is connected to the input terminal of the third NOT gate, and the output terminal of the third NOT gate provides the electrical balance enable signal.

[0019] The input of the first NOT gate receives the electrical balance activation signal, and the output provides a second function control signal;

[0020] The input of the second NOT gate receives the electrical balance enable signal, and the output provides a third function control signal.

[0021] Optionally, the power balancing module includes a first transistor, a second transistor, and a third transistor.

[0022] The control terminal of the first transistor is connected to the output terminal of the first NOT gate to receive the second function control signal. The first path terminal is connected to the first voltage source, and the second path terminal is connected to the first path terminal of the second transistor.

[0023] The control terminal of the second transistor is connected to the output terminal of the second NOT gate to receive the third function control signal, and the second path terminal is connected to the reference ground potential.

[0024] The control terminal of the third transistor is connected to the output terminal of the level converter, receives the first function control signal, and the first path terminal is connected to the connection node between the second path terminal of the first transistor and the first path terminal of the second transistor.

[0025] Optionally, the signal output module includes a fourth transistor and a fifth transistor.

[0026] The control terminals of the fourth and fifth transistors are connected to the output terminals of the decoding module, respectively receiving the first decoded output signal and the second decoded output signal. The first path terminal of the fourth transistor is connected to the second voltage source. The connection node between the second path terminal of the fourth transistor and the first path terminal of the fifth transistor is connected to the second path terminal of the third transistor. The second path terminal of the fifth transistor is connected to the third voltage source. The connection node between the second path terminal of the fourth transistor and the first path terminal of the fifth transistor and the connection node between the second path terminal of the third transistor outputs a gate drive signal.

[0027] According to a second aspect of this disclosure, a display driver chip is provided, comprising:

[0028] The array substrate row driving circuit includes multiple array substrate row driving sub-circuits. Each array substrate row driving sub-circuit is connected to one or more rows of pixel units in the display panel. It outputs a scan signal to the one or more rows of pixel units according to the gate driving signal to control the opening and closing of the one or more rows of pixel units.

[0029] The source drive circuit is connected to the multi-column pixel units of the display panel to provide display data to the multi-column pixel units;

[0030] The gate drive control circuit as described in any of the preceding claims enables or disables the power balance function according to the digital control signal and the power balance enable signal, and provides a gate drive signal to the array substrate row drive circuit when the power balance function is enabled or disabled.

[0031] According to a third aspect of this disclosure, a display panel is provided, comprising:

[0032] The display area includes pixel units arranged in an array;

[0033] The bonding area includes the display driver chip as described above;

[0034] The display panel includes at least one selected from cathode ray tube display panels, digital light processing display panels, liquid crystal display panels, light-emitting diode display panels, organic light-emitting diode display panels, quantum dot display panels, micro-LED display panels, mini-LED display panels, field emission display panels, plasma display panels, electrophoretic display panels, or electrowetting display panels.

[0035] According to a fourth aspect of this disclosure, a display device is provided, comprising:

[0036] The display panel includes pixel units arranged in an array;

[0037] The display driver chip described above.

[0038] This disclosure brings the following beneficial effects:

[0039] The gate drive control circuit disclosed herein includes a decoding module, an electrical balance control module, an electrical balance function module, and a signal output module in each gate drive control unit. The decoding module outputs a decoded output signal based on the digital control signal. The electrical balance control module generates a function control signal based on the digital control signal and the electrical balance enable signal. The electrical balance function module enables or disables the electrical balance function based on the function control signal. When the electrical balance function is enabled, the control signal output module adds an intermediate voltage between the minimum and maximum voltages of the gate drive signal. When the electrical balance function is disabled, the signal output module outputs the gate drive signal based on the decoded output signal. By adding the electrical balance enable signal, the number of bits of the digital control signal can be reduced while achieving the electrical balance function, thereby reducing the wiring area of ​​the data control signal. This reduces power consumption through the EQ function while simultaneously reducing the chip area of ​​the gate drive control circuit and the area of ​​the display driver chip.

[0040] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure are realized and obtained through the structures particularly pointed out in the description and the drawings.

[0041] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0042] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0043] Figure 1 This diagram illustrates the structure of a display device in the related art.

[0044] Figure 2A Show Figure 1 A schematic diagram of the structure of the gate drive control unit;

[0045] Figure 2B The truth table of the relevant signals in the relevant technology is shown;

[0046] Figure 2C The waveform of the gate drive signal in the related technology is shown;

[0047] Figure 3 This diagram illustrates the structure of a display device according to an embodiment of the present disclosure;

[0048] Figure 4A Show Figure 3 A schematic diagram of the structure of the gate drive control unit;

[0049] Figure 4B A truth table of a relevant signal provided according to an embodiment of this disclosure is shown;

[0050] Figure 4C A waveform diagram of a related signal provided according to an embodiment of the present disclosure is shown;

[0051] Figure 5 This diagram illustrates the structure of a display device according to an embodiment of the present disclosure;

[0052] Figure 6A Show Figure 5 A schematic diagram of the structure of the gate drive control unit;

[0053] Figure 6B A truth table of a relevant signal provided according to an embodiment of this disclosure is shown;

[0054] Figure 6CA waveform diagram of a related signal provided according to an embodiment of the present disclosure is shown. Detailed Implementation

[0055] Various embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various portions in the drawings are not drawn to scale.

[0056] The following terms are used in this article:

[0057] The EQ (equalizer) function allows the gate drive control circuit in the Display Driver Integrated Circuit (DDIC) to output a clock signal to the Gate on Array (GOA) circuit in the display panel. The GOA circuit then outputs a scan signal under the clock signal, thereby controlling the content displayed on the display panel. The composition of the clock signal is related to whether the EQ function is enabled. The EQ function adds an intermediate voltage to the signal, facilitating the transition between the lowest and highest voltages, thus reducing the power consumption of the gate drive control circuit driving the display panel.

[0058] Figure 1 A schematic diagram of the structure of a display device in related technologies is shown. For example... Figure 1 As shown, the display device 100 includes a gate drive control circuit 110, a GOA circuit 120, a source drive circuit 140, and a display panel 130. It should be noted that the gate drive control circuit 110, the GOA circuit 120, and the source drive circuit 140 can be implemented using separate driver chips or integrated into a single display driver chip. The display panel 130 includes at least one selected from cathode ray tube display panels, digital light processing display panels, liquid crystal display panels, light-emitting diode display panels, organic light-emitting diode display panels, quantum dot display panels, Micro-LED display panels, Mini-LED display panels, field emission display panels, plasma display panels, electrophoretic display panels, or electrowetting display panels.

[0059] In some embodiments, the display panel 130 includes a display area and a bonding area. The display area includes pixel units arranged in an array (e.g., N rows and M columns of pixel units, where N and M are integers greater than 0), and the bonding area includes a display driver chip. It should be noted that the gate drive control circuit 110, the GOA circuit 120, and the source drive circuit 140 may also be disposed outside the display panel. In some embodiments, the GOA circuit 120 includes multiple GOA sub-circuits (not shown in the figure). The gate drive control circuit 110 includes multiple gate drive control units 111. For ease of description,Figure 1 The diagram shows n gate drive control units 111 (where n is an integer greater than 0 and less than or equal to N). Each gate drive control unit 111 can be connected to one or more GOA sub-circuits, outputting a gate drive signal CGOUT that meets the level requirements of the corresponding GOA sub-circuit. Each GOA sub-circuit can be connected to one or more rows of pixel units, outputting scan signals to those rows to control their on / off states. The source drive circuit 140 can be connected to M columns of pixel units to provide display data to them.

[0060] In some embodiments, the display device 100 further includes a timing controller (not shown). The timing controller can receive display control signals and output digital control signals S that control the operating timing of the gate drive control unit 111 according to the display control signals. For example, the timing controller can output k digital control signals for each gate drive control unit 111 (where k is an integer greater than 0, such as k=3). The display control signals include, but are not limited to, power signals, image signals, mode control signals, etc. The digital control signals S include a start of video frame (STV) signal and a clock signal. Figure 2A Show Figure 1 A schematic diagram of the gate drive control unit. (See diagram below.) Figure 2A As shown, the gate drive control unit 111 includes a decoding module 210, an EQ function module 220, and a signal output module 230.

[0061] In some embodiments, the decoding module 210 generates a corresponding decoded output signal according to a preset mapping relationship based on the input digital control signal S. Taking the digital control signal S<2:0> as an example, the decoding module 210 can output eight different decoded output signals based on the digital control signal S<2:0>. The EQ function module 220 enables or disables the EQ function under the control of the decoded output signal. When the EQ function is enabled, the control signal output module 230 adds an intermediate voltage between the lowest voltage VGLO and the highest voltage VGHO of the gate drive signal CGOUT. When the EQ function is disabled, the signal output module 230 outputs the gate drive signal CGOUT according to the decoded output signal.

[0062] In some embodiments, the EQ function module 220 includes transistors M1 and M2. The control terminals of transistors M1 and M2 are connected to the output terminals of the decoding module 210, receiving the decoding output signals VSP_SELB and GND_SEL from the decoding module 210, respectively. The first path terminal of transistor M1 is connected to the voltage source VSP. The second path terminal of transistor M1 is connected to the first path terminal of transistor M2, and the second path terminal of transistor M2 is connected to the reference ground potential GND. In some embodiments, the signal output module 230 includes transistors M3 and M4. The control terminals of transistors M3 and M4 are connected to the output terminals of the decoding module 210, receiving the decoding output signals VGH_SEL and VGL_SEL from the decoding module 210, respectively. The first path terminal of transistor M3 is connected to the voltage source VGHO. The connection node between the second path terminal of transistor M3 and the first path terminal of transistor M4 is connected to the connection node between the second path terminal of transistor M1 and the first path terminal of transistor M2. The second path terminal of transistor M4 is connected to the voltage source VGLO. Taking a liquid crystal display as an example, VGHO and VGLO are the on and off voltages of the TFT in the pixel unit. The connection node between the second path terminal of transistor M3 and the first path terminal of transistor M4 outputs a gate drive signal CGOUT. In some embodiments, transistors M1, M2, M3, and M4 are high-voltage transistors.

[0063] Figure 2B This shows a truth table for digital control signals and gate drive signals in related technologies. For example... Figure 2B As shown, taking the digital control signal S<2:0> as an example, when the digital control signal S<2:0> is "000", the gate drive signal CGOUT is VGLO; when the digital control signal S<2:0> is "001", the gate drive signal CGOUT is GND; when the digital control signal S<2:0> is "010", the gate drive signal CGOUT is VGHO; when the digital control signal S<2:0> is "011", the gate drive signal CGOUT is VSP; when the digital control signal S<2:0> is "100", "101", "110", or "111", the gate drive signal CGOUT is "HIZ". When the digital control signal S<2:0> is "001" and "011", the EQ function module 220 enables the EQ function; when the digital control signal S<2:0> is in other cases, the EQ function module 220 disables the EQ function. Figure 2C The waveform of the gate drive signal in the related technology is shown. For example... Figure 2CAs shown, the solid line represents the gate drive signal CGOUT output when the EQ function is disabled. The minimum voltage of the gate drive signal CGOUT is VGLO, and the maximum voltage is VGHO. The dashed line represents the gate drive signal CGOUT output when the EQ function is enabled. At the rising edge, the gate drive signal CGOUT adds an intermediate voltage VSP or GND between the minimum voltage VGLO and the maximum voltage VGHO. At the falling edge, the gate drive signal CGOUT adds an intermediate voltage GND between the minimum voltage VGLO and the maximum voltage VGHO. In some embodiments, the power consumption consumed by the gate drive control circuit to drive the display panel can be expressed as:

[0064] P=V*i=V*(V*C PANEL *f)

[0065] Where P is the power consumption consumed by the gate drive control circuit to drive the display panel, V = VGHO - VGLO, C PANEL Here, f represents the display panel capacitance, and f is the scanning frequency of the GOA sub-circuit. It can be understood that by adding an intermediate voltage between the lowest voltage VGLO and the highest voltage VGHO of the gate drive signal CGOUT, the transition between the lowest and highest voltages is completed through this intermediate voltage, thus reducing the power consumption consumed by the gate drive control circuit driving the display panel.

[0066] However, each gate drive control unit 111 needs to receive k digital control signals, and n gate drive control units 111 need to receive k*n digital control signals. The timing controller and the gate drive control circuit are typically far apart in the chip layout, requiring long wiring distances. Therefore, while adding an EQ function to the gate drive control circuit 110 in related technologies can reduce power consumption, it increases the chip area of ​​the gate drive control circuit 110, thereby increasing the chip area of ​​the display driver circuit.

[0067] Based on this, the present disclosure provides a gate drive control circuit to reduce power consumption while reducing chip area.

[0068] Figure 3 A schematic diagram of a display device according to an embodiment of the present disclosure is shown. Figure 3 As shown, the display device 300 includes a gate drive control circuit 310, a GOA circuit 320, a source drive circuit 340, and a display panel 330. For ease of description, only a detailed description is provided here. Figure 1 Display device 100 and Figure 3 The differences between the display device 300 and the display device 300.

[0069] In some embodiments, the gate drive control circuit 310 includes a plurality of gate drive control units 311. For ease of description, Figure 3The diagram shows n gate drive control units 311 (where n is an integer greater than 0 and less than or equal to N). In some embodiments, the timing controller can output k-1 digital control signals (where k is an integer greater than 0, for example, k=3) to each gate drive control unit 311 according to the display control signal, and can also output one EQ enable signal EQ_SEL to the n gate drive control units 311. Figure 4A Show Figure 3 A schematic diagram of the gate drive control unit. (See diagram below.) Figure 4A As shown, the gate drive control unit 311 includes a decoding module 410, an EQ control module 420, an EQ function module 430, and a signal output module 440.

[0070] In some embodiments, the decoding module 410 generates a corresponding decoded output signal according to a preset mapping relationship based on the digital control signal S. In some embodiments, the digital control signal is a 2-bit binary signal. Taking the digital control signal S<1:0> as an example, the decoding module 410 can output four decoded output signals based on the digital control signal S<1:0>. In some embodiments, the EQ control module 420 generates a function control signal based on the digital control signal S and the EQ enable signal EQ_SEL. The EQ function module 430 enables or disables the EQ function according to the function control signal. When the EQ function is enabled, the control signal output module 440 adds an intermediate voltage between the lowest voltage VGLO and the highest voltage VGHO of the gate drive signal CGOUT. When the EQ function is disabled, the signal output module 440 outputs the gate drive signal CGOUT according to the decoded output signal.

[0071] In some embodiments, the EQ control module 420 receives a digital control signal S and an electrical balance enable signal EQ_SEL, and generates a function control signal based on the digital control signal S and the electrical balance enable signal EQ_SEL. In some embodiments, the EQ control module 420 includes an AND gate U1, a level shifter 421, a NOT gate E1, and a NOT gate E2. The input of the AND gate U1 receives the 0th bit signal S. <0> and the first bit signal S <1> The inverted signal is connected to the output of AND gate U1, which is connected to the input of level converter 421. The output of level converter 421 provides the function control signal VSPGND_SEL. The input of NOT gate E1 receives the EQ enable signal EQ_SEL, and its output provides the function control signal VSP_SELB. The input of NOT gate E2 receives the EQ enable signal EQ_SEL, and its output provides the function control signal GND_SEL. In some embodiments, the EQ function module 430 includes transistors M5, M6, and M7. The control terminal of transistor M5 is connected to the output of NOT gate E1, receives the function control signal VSP_SELB, its first path terminal is connected to the voltage source VSP, and its second path terminal is connected to the first path terminal of transistor M6. The control terminal of transistor M6 is connected to the output of NOT gate E2, receives the function control signal GND_SEL, and its second path terminal is connected to the reference ground potential GND. The control terminal of transistor M7 is connected to the output terminal of level converter 421, receiving the function control signal VSPGND_SEL. The first path terminal of transistor M7 is connected to the connection node between the second path terminal of transistor M5 and the first path terminal of transistor M6. In some embodiments, the signal output module 440 includes transistors M3 and M4. The control terminals of transistors M3 and M4 are connected to the output terminal of decoding module 410, receiving the decoding output signals VGH_SEL and VGL_SEL from decoding module 410, respectively. The first path terminal of transistor M3 is connected to voltage source VGHO. The connection node between the second path terminal of transistor M3 and the first path terminal of transistor M4 is connected to the second path terminal of transistor M7. The second path terminal of transistor M4 is connected to voltage source VGLO. The connection node between the second path terminal of transistor M3 and the first path terminal of transistor M4 and the second path terminal of transistor M7 outputs the gate drive signal CGOUT. It should be noted that transistors M5 and M6 have opposite conduction types, and transistors M3 and M4 have opposite conduction types. In some embodiments, transistors M5 and M6 can be medium-voltage transistors, while transistors M7, M3, and M4 can be high-voltage transistors. It is understood that... Figure 2A Compared to the gate drive control unit in the previous version, by adding a high-voltage transistor M7, both transistors M5 and M6 can be set as medium-voltage transistors, which can reduce the number of high-voltage transistors and thus reduce power consumption.

[0072] Figure 4BA truth table of a relevant signal provided according to an embodiment of this disclosure is shown. For example... Figure 4B As shown, taking the digital control signal S<1:0> as an example, when the digital control signal S<1:0> is “00” and the EQ enable signal EQ_SEL is “x”, the gate drive signal CGOUT is VGLO; when the digital control signal S<1:0> is “01” and the EQ enable signal EQ_SEL is “0”, the gate drive signal CGOUT is GND; when the digital control signal S<1:0> is “01” and the EQ enable signal EQ_SEL is “1”, the gate drive signal CGOUT is VSP; when the digital control signal S<1:0> is “11” and the EQ enable signal EQ_SEL is “x”, the gate drive signal CGOUT is VGHO; when the digital control signal S<1:0> is “10” and the EQ enable signal EQ_SEL is “x”, the gate drive signal CGOUT is “HIZ”. Figure 4C A waveform diagram of a related signal provided according to an embodiment of this disclosure is shown. For example... Figure 4C As shown in the waveform diagram of the gate drive signal CGOUT, the solid line represents the gate drive signal CGOUT output when the EQ function is disabled. The minimum voltage of the gate drive signal CGOUT is VGLO, and the maximum voltage is VGHO. The dashed line represents the gate drive signal CGOUT output when the EQ function is enabled. At the rising edge, an intermediate voltage VSP is added between the minimum voltage VGLO and the maximum voltage VGHO. At the falling edge, an intermediate voltage GND is added between the minimum voltage VGLO and the maximum voltage VGHO. The following section will combine... Figures 4A to 4CTo explain, when the digital control signal S<1:0> is "00" and the EQ enable signal EQ_SEL is "x", the function control signal VSPGND_SEL is "0", transistor M7 is off, and transistors M3 and M4 are controlled by the decoder output signals VGH_SEL and VGL_SEL respectively. Transistor M3 is off, and transistor M4 is on, and the gate drive signal CGOUT is VGLO. When the digital control signal S<1:0> is "01" and the EQ enable signal EQ_SEL is "1", the function control signal VSPGND_SEL is "1", VSP_SELB is "0", GND_SEL is "0", transistors M7 and M5 are on, transistor M6 is off, and the gate drive signal CGOUT is pulled high to the intermediate voltage VSP. When the digital control signal S<1:0> is "11" and the EQ enable signal EQ_SEL is "x", the function control signal VSPGND_SEL is "0", transistor M7 is off, and transistors M3 and M4 are controlled by the decoder output signals VGH_SEL and VGL_SEL. Transistor M4 is off, transistor M3 is on, and the gate drive signal CGOUT is VGHO. When the digital control signal S<1:0> is "01" and the EQ enable signal EQ_SEL is "0", the function control signal VSPGND_SEL is "1", VSP_SELB is "1", GND_SEL is "1", transistors M7 and M6 are on, transistor M5 is off, and the gate drive signal CGOUT is pulled low to the intermediate voltage GND. When the digital control signal S<1:0> is “00” and the EQ enable signal EQ_SEL is “x”, the function control signal VSPGND_SEL is “0”, transistor M7 is turned off, and transistors M3 and M4 are turned on under the control of the decoder output signals VGH_SEL and VGL_SEL. Transistor M3 is turned off and transistor M4 is turned on, and the gate drive signal CGOUT is VGLO.

[0073] Understandably, at the rising edge, an intermediate voltage VSP is added between the lowest voltage VGLO and the highest voltage VGHO of the gate drive signal CGOUT; at the falling edge, an intermediate voltage GND is added between the lowest voltage VGLO and the highest voltage VGHO of the gate drive signal CGOUT. This intermediate voltage completes the transition between the lowest and highest voltages, reducing the power consumption of the gate drive control circuit driving the display panel. Each gate drive control unit 411 needs to receive k-1 digital control signals. Since n gate drive control units 411 share one EQ enable signal EQ_SEL, the n gate drive control units 411 need to receive (k-1)*n digital control signals and one EQ enable signal EQ_SEL. This reduces the wiring area in the gate drive control circuit 411, thereby reducing the chip area of ​​the gate drive control circuit.

[0074] Figure 5 A schematic diagram of a display device according to an embodiment of the present disclosure is shown. Figure 5 As shown, the display device 500 includes a gate drive control circuit 510, a GOA circuit 520, a source drive circuit 540, and a display panel 530. For ease of description, only a detailed description is provided here. Figure 1 Display device 100 and Figure 5 The differences between the display device 500 and the display device 500.

[0075] In some embodiments, the gate drive control circuit 510 includes a plurality of gate drive control units 511. For ease of description, Figure 5 The diagram shows n gate drive control units 511 (where n is an integer greater than 0 and less than or equal to N). In some embodiments, the timing controller can output k-1 digital control signals (where k is an integer greater than 0, for example, k=3) to each gate drive control unit 511 according to the display control signal. Figure 6A Show Figure 5 A schematic diagram of the gate drive control unit. (See diagram below.) Figure 6A As shown, the gate drive control unit 511 includes a decoding module 610, an EQ control module 620, an EQ function module 630, and a signal output module 640.

[0076] In some embodiments, the decoding module 610 generates a corresponding decoded output signal according to a preset mapping relationship based on the input digital control signal S. Taking the digital control signal S<1:0> as an example, the decoding module 610 can output four types of decoded output signals based on the digital control signal S<1:0>. In some embodiments, the EQ control module 620 receives the digital control signal S, generates an EQ enable signal EQ_SEL based on the digital control signal S, and generates a function control signal based on the digital control signal S and the EQ enable signal EQ_SEL. The EQ function module 630 enables or disables the EQ function according to the function control signal. When the EQ function is enabled, the control signal output module 640 adds an intermediate voltage between the lowest voltage VGLO and the highest voltage VGHO of the gate drive signal CGOUT. When the EQ function is disabled, the signal output module 640 outputs the gate drive signal CGOUT according to the decoded output signal.

[0077] In some embodiments, the EQ control module 620 includes an AND gate U1, a level shifter 621, a NOT gate E1, a NOT gate E2, a NOT gate E3, and a D flip-flop 622. The input of the AND gate U1 receives a digital control signal S. <0> and digital control signal S <1> The inverted signal is connected to the output of AND gate U1 and then to the input of level converter 621. The output of level converter 621 provides the function control signal VSPGND_SEL. The reset terminal Rst_n of D flip-flop 622 receives the digital control signal S. <0> The clock signal input terminal Clk receives the digital control signal S. <1> The Q output is connected to the input of NOT gate E3, and the output of NOT gate E3 provides the EQ enable signal EQ_SEL. The input of NOT gate E1 receives the EQ enable signal EQ_SEL, and its output provides the function control signal VSP_SELB. The input of NOT gate E2 receives the EQ enable signal EQ_SEL, and its output provides the function control signal GND_SEL. It should be noted that... Figure 6A The EQ function module 630 and signal output module 640 are in conjunction with Figure 4A The EQ function module 430 and the signal output module 440 are the same, so they will not be described again here.

[0078] Figure 6B A truth table of a relevant signal provided according to an embodiment of this disclosure is shown. For example... Figure 6B As shown, taking the digital control signal S<1:0> as an example, when the digital control signal S<1:0> is “00”, the gate drive signal CGOUT is VGLO; when the digital control signal S<1:0> is “01”, the gate drive signal CGOUT rises to GND or falls to VSP; when the digital control signal S<1:0> is “11”, the gate drive signal CGOUT is VGHO; when the digital control signal S<1:0> is “10”, the gate drive signal CGOUT is “HIZ”. Figure 6C A waveform diagram of a related signal provided according to an embodiment of this disclosure is shown. For example... Figure 6C As shown in the waveform diagram of the gate drive signal CGOUT, the solid line represents the gate drive signal CGOUT output when the EQ function is disabled. The minimum voltage of the gate drive signal CGOUT is VGLO, and the maximum voltage is VGHO. The dashed line represents the gate drive signal CGOUT output when the EQ function is enabled. At the rising edge, the gate drive signal CGOUT adds an intermediate voltage VSP between the minimum voltage VGLO and the maximum voltage VGHO. At the falling edge, the gate drive signal CGOUT adds an intermediate voltage GND between the minimum voltage VGLO and the maximum voltage VGHO. The following section will combine... Figures 6A to 6CTo explain, when the digital control signal S<1:0> is "00", the Q output of the D flip-flop 622 is "0", the EQ enable signal EQ_SEL is "1", and the function control signal VSPGND_SEL is "0". Transistor M7 is off. Under the control of the decoder output signals VGH_SEL and VGL_SEL, transistor M3 is off and transistor M4 is on, and the gate drive signal CGOUT is VGLO. When the digital control signal S<1:0> is "01", the function control signal VSPGND_SEL is "1", the EQ enable signal EQ_SEL is still "1", VSP_SELB is "0", GND_SEL is "0", transistors M7 and M5 are on, transistor M6 is off, and the gate drive signal CGOUT is pulled high to the intermediate voltage VSP. When the digital control signal S<1:0> is "11", the function control signal VSPGND_SEL is "0", the Q output of the D flip-flop 622 is "1", the EQ enable signal EQ_SEL is "0", transistor M7 is off, and transistors M3 and M4 are controlled by the decoder output signals VGH_SEL and VGL_SEL. Transistor M4 is off, transistor M3 is on, and the gate drive signal CGOUT is VGHO. When the digital control signal S<1:0> is "01", the function control signal VSPGND_SEL is "1", the EQ enable signal EQ_SEL is still "0", VSP_SELB is "1", GND_SEL is "1", transistors M7 and M6 are on, transistor M5 is off, and the gate drive signal CGOUT is pulled low to the intermediate voltage GND. When the digital control signal S<1:0> is “00”, the function control signal VSPGND_SEL is “0”, the Q output of the D flip-flop 622 is “0”, the EQ enable signal EQ_SEL is “1”, VSP_SELB is “0”, GND_SEL is “0”, transistor M7 is off, and transistors M3 and M4 are controlled by the decoder output signals VGH_SEL and VGL_SEL. Transistor M3 is turned off, transistor M4 is turned on, and the gate drive signal CGOUT is VGLO.

[0079] It is understandable that each gate drive control unit 411 needs to receive k-1 digital control signals, and n gate drive control units 111 need to receive (k-1)*n digital control signals. The EQ control module 620 generates an EQ enable signal EQ_SEL based on the digital control signal S, saving the wiring area of ​​the EQ enable signal EQ_SEL. While reducing power consumption, it further reduces the wiring area in the gate drive control circuit, thereby reducing the chip area of ​​the gate drive control circuit.

[0080] In summary, the gate drive control circuit provided in this disclosure includes a decoding module, an electrical balance control module, an electrical balance function module, and a signal output module in each gate drive control unit. The decoding module outputs a decoded output signal based on the digital control signal. The electrical balance control module generates a function control signal based on the digital control signal and the electrical balance enable signal. The electrical balance function module enables or disables the electrical balance function based on the function control signal. When the electrical balance function is enabled, the control signal output module adds an intermediate voltage between the minimum and maximum voltages of the gate drive signal. When the electrical balance function is disabled, the signal output module outputs the gate drive signal based on the decoded output signal. By adding the electrical balance enable signal, the number of bits in the digital control signal can be reduced while achieving the electrical balance function, thereby reducing the wiring area of ​​the data control signal. This reduces power consumption through the EQ function while simultaneously reducing the chip area of ​​the gate drive control circuit and the area of ​​the display driver chip.

[0081] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating this disclosure and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of this disclosure.

Claims

1. A gate drive control circuit, comprising: a plurality of gate drive control units, each of the gate drive control units comprising a decoding module, a level balance control module, a level balance function module and a signal output module, wherein the decoding module is configured to output a decoding output signal according to a digital control signal; the level balance control module is configured to generate a function control signal according to the digital control signal and a level balance enable signal; the level balance function module is configured to turn on or turn off a level balance function according to the function control signal, and control the signal output module to increase an intermediate voltage between a lowest voltage and a highest voltage of a gate drive signal when the level balance function is turned on; the signal output module is configured to output the gate drive signal according to the decoding output signal when the level balance function is turned off.

2. The gate drive control circuit of claim 1, wherein, the digital control signal is a 2-bit binary signal comprising a 0th bit signal and a 1st bit signal, and the level balance control module generates the function control signal according to the digital control signal and the level balance enable signal comprises: the level balance control module receives the digital control signal and the level balance enable signal, and generates the function control signal according to the digital control signal and the level balance enable signal.

3. The gate drive control circuit of claim 2, wherein, the level balance control module comprises an AND gate, a level shifter, a first NOT gate and a second NOT gate, an input end of the AND gate receives the 0th bit signal and an inverted signal of the 1st bit signal, an output end of the AND gate is connected to an input end of the level shifter, and an output end of the level shifter provides a first function control signal; an input end of the first NOT gate receives the level balance enable signal, and an output end thereof provides a second function control signal; an input end of the second NOT gate receives the level balance enable signal, and an output end thereof provides a third function control signal.

4. The gate drive control circuit of claim 1, wherein, the digital control signal is a 2-bit binary signal comprising a 0th bit signal and a 1st bit signal, and the level balance control module generates the function control signal according to the digital control signal and the level balance enable signal comprises: the level balance control module receives the digital control signal, generates the level balance enable signal according to the digital control signal, and generates the function control signal according to the digital control signal and the level balance enable signal.

5. The gate drive control circuit of claim 4, wherein, the level balance control module comprises an AND gate, a level shifter, a first NOT gate, a second NOT gate, a third NOT gate and a D flip-flop, an input end of the AND gate receives the 0th bit signal and an inverted signal of the 1st bit signal, an output end of the AND gate is connected to an input end of the level shifter, and an output end of the level shifter provides a first function control signal; a reset end of the D flip-flop receives the 0th bit signal, a clock signal input end thereof receives the 1st bit signal, a Q output end thereof is connected to an input end of the third NOT gate, and an output end of the third NOT gate provides the level balance enable signal; an input end of the first NOT gate receives the level balance enable signal, and an output end thereof provides a second function control signal; an input end of the second NOT gate receives the level balance enable signal, and an output end thereof provides a third function control signal.

6. The gate drive control circuit according to claim 3 or 5, wherein The electric balance function module comprises a first transistor, a second transistor and a third transistor, The control end of the first transistor is connected to the output end of the first NAND gate, receives the second function control signal, the first passage end is connected to a first voltage source, and the second passage end is connected to the first passage end of the second transistor, The control end of the second transistor is connected to the output end of the second NAND gate, receives the third function control signal, and the second passage end is connected to a reference ground potential, The control end of the third transistor is connected to the output end of the electric level converter, receives the first function control signal, the first passage end is connected to the connection node of the second passage end of the first transistor and the first passage end of the second transistor.

7. The gate drive control circuit of claim 6, wherein, The signal output module comprises a fourth transistor and a fifth transistor, The control ends of the fourth transistor and the fifth transistor are connected to the output end of the decoding module, respectively receive a first decoding output signal and a second decoding output signal, the first passage end of the fourth transistor is connected to a second voltage source, the connection node of the second passage end of the fourth transistor and the first passage end of the fifth transistor is connected to the second passage end of the third transistor, the second passage end of the fifth transistor is connected to a third voltage source, and the connection node of the second passage end of the fourth transistor and the first passage end of the fifth transistor outputs a gate driving signal.

8. A display driving chip, characterized in that, Comprise: An array substrate row driving circuit comprising a plurality of array substrate row driving sub-circuits, each array substrate row driving sub-circuit being connected to one or more rows of pixel units in a display panel and outputting a scanning signal to the one or more rows of pixel units according to a gate driving signal to control the opening and closing of the one or more rows of pixel units; A source driving circuit connected to a plurality of columns of pixel units of the display panel to provide display data to the plurality of columns of pixel units; The gate driving control circuit according to any one of claims 1 to 7 opens or closes the electric balance function according to a digital control signal and an electric balance opening signal, and provides a gate driving signal to the array substrate row driving circuit in the case of opening or closing the electric balance function.

9. A display panel, characterized by, Comprise: A display area comprising pixel units arranged in an array; A binding area comprising the display driving chip according to claim 8; The display panel comprises at least one selected from a cathode ray tube display panel, a digital light processing display panel, a liquid crystal display panel, a light emitting diode display panel, an organic light emitting diode display panel, a quantum dot display panel, a Mirco-LED display panel, a Mini-LED display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel or an electrowetting display panel.

10. A display device, characterized by comprising: Comprise: A display panel comprising pixel units arranged in an array; The display driving chip according to claim 8.

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