Electrostatic discharge output circuit satisfying HBM mode and MM mode

Abstract

The utility model discloses an electrostatic discharge output circuit satisfying an HBM mode and an MM mode, and relates to the technical field of electrostatic discharge generators. The circuit comprises a PWM chip and two relay switch groups. The switch end of the second relay is connected with the first equipment to-be-tested interface; the switch end of the fourth relay is connected in parallel with a third capacitor and a second resistor. According to the electrostatic discharge output circuit meeting the HBM mode and the MM mode in the technical scheme, the HMB mode and the MM mode are integrated into two modes and can be switched freely, the two modes can be tested by the same equipment, the cost can be saved, the selection is more flexible, and a test circuit does not need to be repeatedly built when the same equipment is operated; the problems of conversion from a circuit model to an actual circuit and the influence of parasitic inductance in the implementation process are solved, and therefore control over the current waveform is achieved more accurately.

Description

Technical Field

[0001] This utility model belongs to the field of electrostatic discharge generator technology, and in particular relates to an electrostatic discharge output circuit that satisfies both HBM mode and MM mode. Background Technology

[0002] Currently, electrostatic discharge generators require devices with two discharge modes to simultaneously meet the electrostatic discharge output design schemes of both HBM and MM modes, and to comply with JESD22-A115-A and JEDEC_JESD22-A114E-Y2007 standards. The circuit models for HBM and MM mode electrostatic discharge output are shown in the attached manual. Figure 1 and attached Figure 2 As shown, the performance of the circuit model is affected by its parasitic inductance. Precautions must be taken in the tester to avoid recharge transients and multiple pulses.

[0003] Current circuit models only have these two individual modes and fail to combine them into a single circuit. Currently, the same device under test requires testing in both modes sequentially. If the two modes could be combined, allowing the same device to test both modes, it would save costs, make the selection more flexible, and eliminate the need to repeatedly build experimental routes when operating the same device, greatly improving efficiency. Therefore, this technical solution proposes an electrostatic discharge output circuit that satisfies both HBM and MM modes. Utility Model Content

[0004] This invention provides an electrostatic discharge output circuit that satisfies both HBM and MM modes, thus solving the above problems.

[0005] To solve the above-mentioned technical problems, this utility model is achieved through the following technical solution:

[0006] This utility model provides an electrostatic discharge output circuit that satisfies both HBM and MM modes, including a PWM chip at the high-voltage end for controlling the duty cycle to output a push-pull circuit, a first resistor connected to the PWM chip for reducing current, and two sets of relay switches connected in parallel from the first resistor.

[0007] The two sets of relay switch groups include a first group consisting of a first relay switch and a second relay switch connected in series, and a second group consisting of a third relay switch and a fourth relay switch connected in series.

[0008] A first capacitor is connected between the first relay switch and the second relay switch and then grounded; a second capacitor is connected between the third relay switch and the fourth relay switch and then grounded; the second relay switch terminal is connected to the first device under test interface; the fourth relay switch terminal is connected in parallel with a third capacitor and a second resistor, and the third capacitor is connected in series with the third resistor and then grounded; the second resistor terminal is connected to the second device under test interface; the PWM chip, the first device under test interface, and the second device under test interface are all grounded.

[0009] Furthermore, the first device test interface and the second device test interface are respectively equipped with a first shorting wire and a second shorting wire for shorting the high voltage to ground to test the current.

[0010] Furthermore, the first device under test interface and the second device under test interface are respectively equipped with a first load current measuring line with a fourth resistor and a second load test current measuring line with a fifth resistor; the resistance values ​​of the fourth resistor and the fifth resistor are both 500Ω.

[0011] Furthermore, the first capacitor is 200pF, and the second capacitor is 100pF.

[0012] Furthermore, the second resistor is 1500Ω, and the third resistor is 68Ω.

[0013] The present invention has the following advantages over the prior art:

[0014] (1) Through the electrostatic discharge output circuit that satisfies both HBM mode and MM mode in this technical solution, HMB mode and MM mode are integrated into two modes that can be switched at will, and the same device can be used to test two modes.

[0015] (2) It can save costs and offer more flexible options, and there is no need to repeatedly build test circuits when operating the same equipment;

[0016] (3) Solve the conversion from circuit model to actual circuit, as well as the influence of parasitic inductance during implementation, so as to achieve more accurate control of current waveform.

[0017] Of course, any product implementing this utility model does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this utility model, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 The circuit model diagram for the existing MM mode;

[0020] Figure 2 The circuit model diagram for the existing HBM mode;

[0021] Figure 3 This is a circuit diagram showing the electrostatic discharge output circuit that satisfies both HBM and MM modes in this technical solution.

[0022] Figure 4 The current waveform diagram is shown when the voltage is set to 250V and R1 is 50Ω in HBM mode in this technical solution.

[0023] Figure 5 The diagram shows the current waveform when the voltage is set to 250V and R1 is 1500Ω in HBM mode in this technical solution.

[0024] The attached diagram lists the components represented by each number as follows:

[0025] U1 - PWM chip, R6 - first resistor, S1 - first relay switch, S3 - second relay switch, S2 - third relay switch, S4 - fourth relay switch, C1 - first capacitor, C2 - second capacitor, C3 - third capacitor, R1 - second resistor, R5 - third resistor, D1 - first device under test interface, D2 - second device under test interface, short1 - first jumper wire, short2 - second jumper wire, R4 - fourth resistor, R3 - fifth resistor. Detailed Implementation

[0026] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0027] Please see Figure 1-2The diagrams shown are the existing MM mode and HBM mode circuit models, respectively. In both circuit models, S11 is a single-pole double-throw relay. After the high voltage fully charges capacitor C11, the relay instantly switches from left to right. When externally short-circuited to ground or with a 500-ohm load (one end connected to Terminal A, the other to Terminal B), capacitor C11 forms a loop with the external wiring to release the high voltage. After release, single-pole double-throw relay S21 closes to ensure complete release of the high voltage in the capacitor. Voltage loss occurs when single-pole double-throw relay S11 releases the high voltage. Due to the small capacitance, the single-pole double-throw relay has a period of inactivity, during which a small amount of voltage is consumed. Furthermore, the two circuit models cannot be switched arbitrarily; they can only be operated independently. Because the single-pole double-throw relay S21 in both circuit models has a discharge relay, parasitic inductance is generated during small current discharges, resulting in abnormal small current waveforms.

[0028] like Figure 3 As shown, in order to solve the above problems, this technical solution proposes an electrostatic discharge output circuit that satisfies both HBM mode and MM mode, including a PWM chip U1 at the high-voltage end for controlling the duty cycle to output a push-pull circuit, a first resistor R6 connected to the PWM chip U1 for reducing current, and two sets of relay switches connected in parallel from the first resistor R6.

[0029] The two sets of relay switches include a first set consisting of a first relay switch S1 and a second relay switch S3 connected in series, and a second set consisting of a third relay switch S2 and a fourth relay switch S4 connected in series.

[0030] A first capacitor C1 is connected between the first relay switch S1 and the second relay switch S3 and then grounded; a second capacitor C2 is connected between the third relay switch S2 and the fourth relay switch S4 and then grounded; the second relay switch S3 is connected to the first device under test interface D1; the fourth relay switch S4 is connected in parallel with a third capacitor C3 and a second resistor R1, and the third capacitor C3 is connected in series with a third resistor R5 and then grounded; the second resistor R1 is connected to the second device under test interface D2; the PWM chip U1, the first device under test interface D1, and the second device under test interface D2 are all grounded.

[0031] Among them, the first device test interface D1 and the second device test interface D2 are respectively equipped with a first shorting wire short1 and a second shorting wire short2 for shorting the high voltage to ground to test the current.

[0032] Among them, the first device test interface D1 and the second device test interface D2 are respectively equipped with a first load current measurement line with a fourth resistor R4 and a second load test current measurement line with a fifth resistor R3; the resistance values ​​of the fourth resistor R4 and the fifth resistor R3 are both 500Ω.

[0033] The first capacitor C1 is 200pF and the second capacitor C2 is 100pF.

[0034] The second resistor R1 is 1500Ω and the third resistor R5 is 68Ω.

[0035] Equipment testing is divided into short-circuit testing and testing with a 500Ω load.

[0036] The "Short" connection shorts the high voltage to ground for the test current. The 500Ω connection of the fourth resistor R4 and the fifth resistor R3 is for the test current with a 500Ω load. Figure 4 The figure shows the current waveform when the voltage is set to 250V and R1 is 50Ω in HBM mode for this solution; Figure 5 The figure shows the current waveform when the voltage is set to 250V and R1 is 1500Ω in HBM mode of this scheme.

[0037] The working principle of this technical solution is as follows:

[0038] First, the high-voltage section uses a PWM chip, U1, to control the duty cycle and output the push-pull circuit. The voltage is then boosted to the required value by a voltage multiplier circuit.

[0039] A 58MΩ resistor, i.e., the first resistor R6, is connected in series at the high-voltage end to reduce the current. After the resistor, the circuit splits into two parts (e.g., ...). Figure 3 The addition of the first relay switch S1 and the third relay switch S2 to split the circuit before the high voltage will reduce the redundant circuits in the two modes, thereby reducing the impact of parasitic inductance on the waveform.

[0040] The upper part is MM, and the lower part is HBM.

[0041] When MM mode is selected, the first relay switch S1 is closed and the third relay switch S2 is open. High voltage enters the first capacitor C1 for energy storage. When static electricity needs to be released, the second relay switch S3 is controlled by a high-speed pulse signal to quickly close and then open. The closing time is approximately 100ms, thereby achieving the instantaneous release of high voltage to mimic the instantaneous release of static electricity.

[0042] When HBM mode is selected, the third relay switch S2 is closed and the first relay switch S1 is open. High voltage enters the second capacitor C2 for energy storage. When static electricity needs to be released, the fourth relay switch S4 closes and then opens quickly. Because HBM mode requires a high current waveform, a third capacitor C3, a second resistor R1, and a third resistor R5 are added. After the voltage is released from the fourth relay switch S4, it enters the third capacitor C3 and the third resistor R5 to store the released charge again before release. This allows the rising edge of the static current waveform to rise slowly, meeting the national standard requirements for the HBM static current rising edge and also solving the problem of parasitic inductance affecting the waveform. After the charge is released from the third capacitor C3, the second resistor R1 further limits the current, ensuring that the peak current is between 150mA and 190mA when the voltage is set to 250V (as per international standards). Figure 4 , Figure 5 Different resistors result in different peak current values.

[0043] This technical solution utilizes an electrostatic discharge output circuit that satisfies both HBM and MM modes, integrating them into two freely switchable modes. This allows for testing both modes on the same device, offering cost savings and greater flexibility, while eliminating the need to repeatedly build test circuits for the same equipment. It also resolves the conversion between circuit models and actual circuits, as well as the impact of parasitic inductance during implementation. This results in more precise control over the current waveform.

[0044] The preferred embodiments of this utility model disclosed above are merely illustrative of the present utility model. These preferred embodiments do not exhaustively describe all details, nor do they limit the utility model to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this utility model, thereby enabling those skilled in the art to better understand and utilize it. This utility model is limited only by the claims and their full scope and equivalents.

Claims

1. An electrostatic discharge output circuit satisfying HBM mode and MM mode, characterized by, The PWM chip (U1) for controlling the duty ratio of the output of the push-pull circuit, the first resistor (R6) connected with the PWM chip (U1) for reducing current, and two groups of relay switch groups connected in parallel with the first resistor (R6); The two groups of relay switch groups include a first group composed of the first relay switch (S1) and the second relay switch (S3) connected in series, and a second group composed of the third relay switch (S2) and the fourth relay switch (S4) connected in series; The first capacitor (C1) is connected between the first relay switch (S1) and the second relay switch (S3) and then grounded, and the second capacitor (C2) is connected between the third relay switch (S2) and the fourth relay switch (S4) and then grounded; the second relay switch (S3) is connected with the first device under test interface (D1); the fourth relay switch (S4) is connected in parallel with the third capacitor (C3) and the second resistor (R1), and the third capacitor (C3) is connected in series with the third resistor (R5) and then grounded; the second resistor (R1) is connected with the second device under test interface (D2); the PWM chip (U1), the first device under test interface (D1), and the second device under test interface (D2) are grounded.

2. The electrostatic discharge output circuit satisfying HBM mode and MM mode according to claim 1, wherein The first shorting line (short1) and the second shorting line (short2) are respectively installed on the first device under test interface (D1) and the second device under test interface (D2) for short-circuiting the high voltage and the ground to test the current.

3. The electrostatic discharge output circuit according to claim 1, wherein The first load current test line with the fourth resistor (R4) and the second load current test line with the fifth resistor (R3) are respectively installed on the first device under test interface (D1) and the second device under test interface (D2); the resistance values of the fourth resistor (R4) and the fifth resistor (R3) are both 500Ω.

4. The electrostatic discharge output circuit according to claim 1, wherein The first capacitor (C1) is 200pF, and the second capacitor (C2) is 100pF.

5. The electrostatic discharge output circuit according to claim 1, wherein The second resistor (R1) is 1500Ω, and the third resistor (R5) is 68Ω.

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