Multi-channel pure analog sequential circuit for gallium arsenide radio frequency doubling chip

Abstract

The utility model relates to a gallium arsenide radio frequency multiplication chip power supply sequential circuit. Most existing sequential circuits are based on clock modules, need to write and debug codes, and are complex in structure and high in development and maintenance cost. The utility model provides a multichannel pure analog time sequence circuit for a gallium arsenide radio frequency multiplication chip, the output end of a voltage conversion module is connected with a time sequence module, the output time sequence of the output end of the time sequence module is realized through the time sequence module, and the time sequence module is formed by a switching diode, an NPN triode, a PMOS field effect transistor and three resistors. When the radio frequency chip works and is powered on, voltage is firstly added to the grid electrode and then added to the drain electrode; during power failure, the drain electrode is switched off before the grid electrode, the grid electrode and the drain electrode of the chip are protected, and the chip is prevented from being damaged; according to the utility model, a pure analog circuit realizes sequential control, and a circuit structure without an inductive element has higher robustness in a high-frequency radio-frequency environment, so that the influence of electromagnetic interference is reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to a gallium arsenide radio frequency frequency multiplication chip power supply timing circuit, more specifically, relate to a kind of for gallium arsenide radio frequency frequency multiplication chip multi-channel pure analog timing circuit. BACKGROUND

[0002] Gallium arsenide radio frequency frequency multiplier has important application in wireless communication field, and specific power supply configuration is needed for work, for example, positive voltage is provided for drain, and negative voltage is provided for gate.This bipolar power supply mode can effectively control the working state of radio frequency frequency multiplier, ensure correct biasing and stability and performance in high-frequency environment.The voltage sequence is critical, because wrong voltage sequence can cause device damage or performance degradation.However, with the continuous development of radio frequency technology, the design of radio frequency cavity tends to miniaturization and high integration, which puts higher requirements on the design of power supply circuit.

[0003] At present, common timing circuit design mainly relies on single-chip microcomputer and clock module to realize the opening and power-off timing of voltage.This circuit structure realizes precise timing control through programming, and is widely used in electronic systems requiring multiple voltage rails.Although the single-chip microcomputer solution has the advantages of precision and flexibility, the circuit relying on single-chip microcomputer to realize timing control has some problems that cannot be ignored in the specific application of radio frequency frequency multiplier, for example, single-chip microcomputer and its peripheral circuit will occupy a large space, and for radio frequency frequency multiplier requiring high integration, space limitation becomes a key bottleneck, and radio frequency cavity needs compact structure to maintain specific resonance frequency or adapt to small devices, which makes the single-chip microcomputer solution impractical;and the circuit based on single-chip microcomputer and clock module needs to write and debug code, which increases the development complexity and maintenance difficulty of the circuit.In addition, the electromagnetic compatibility problem of single-chip microcomputer system is more prominent in high-frequency radio frequency environment, and additional shielding measures may be needed, further increasing the burden of circuit structure.Therefore, there is an urgent need for a timing circuit with simple structure, small size and capable of meeting the power supply requirements of gallium arsenide radio frequency frequency multiplication chip to meet the needs of miniaturization and simplification of radio frequency cavity. SUMMARY

[0004] In view of the problems and deficiencies of the prior art, the purpose of the utility model is to provide a kind of for gallium arsenide radio frequency frequency multiplication chip multi-channel pure analog timing circuit, based on the working principle and cavity structure of gallium arsenide radio frequency frequency multiplier chip, input voltage VCC is converted through voltage conversion module, timing module and multi-voltage output module, meets the requirements of the opening and shutdown timing of chip gate and drain, ensures that the voltage acts on radio frequency frequency multiplication chip gate first and then acts on radio frequency frequency multiplication chip drain when power-on using timing module;When power-off, the radio frequency frequency multiplication chip drain voltage is turned off first, and then the radio frequency frequency multiplication chip gate voltage is turned off, to protect the gate and drain of radio frequency frequency multiplication chip and avoid damage to the chip.

[0005] To achieve the above object, the utility model provides the following technical scheme:

[0006] A kind of for gallium arsenide radio frequency frequency multiplication chip multi-channel pure analog timing circuit, including voltage conversion module and timing module, the output end of voltage conversion module is connected timing module, the output timing of the output end VD of timing module is realized by timing module, wherein: the input end VCC of voltage conversion module is connected respectively the input end of linear voltage regulator chip LDO1 and the input end of linear voltage regulator chip LDO2, the output VI of linear voltage regulator chip LDO1 is connected the input end of voltage inverter U1, after conversion by linear voltage regulator chip LDO2, output V+, the output-VI of voltage inverter U1 and the output V+ of linear voltage regulator chip LDO2 are connected respectively two input ends of timing module;

[0007] Timing module includes switch diode D1, NPN triode U5 and PMOS field effect tube Q1, the cathode of switch diode D1 is connected the output-VI of voltage inverter U1, the anode of switch diode D1 is connected the emitter of NPN triode U5, the base of NPN triode U5 is connected the anode of switch diode D1 by resistance R5, the base of NPN triode U5 is grounded by resistance R6, the collector of NPN triode U5 is connected the gate of PMOS field effect tube Q1, resistance R7 is connected between the gate and source of PMOS field effect tube Q1, the source of PMOS field effect tube Q1 is connected the output V+ of linear voltage regulator chip LDO2, and the drain of PMOS field effect tube Q1 is the output VD of timing module.

[0008] Further, it further includes multi-voltage output module, the input end of multi-voltage output module, i.e. the input end of voltage dividing network is connected the output-VI of voltage inverter U1, and different voltage values are output by several operational amplifiers in voltage dividing network.

[0009] Further, the voltage dividing network includes several series-connected voltage dividing resistors, and the voltage dividing network is grounded through the several series-connected voltage dividing resistors;The positive input end of each operational amplifier is connected between two adjacent voltage dividing resistors, and a resistance is connected between the negative input end and the output end of each operational amplifier, to form a high-precision voltage follower, and the output end of each operational amplifier is a constant voltage source with a wide load range.

[0010] Further, the voltage dividing resistors of the voltage dividing network are not less than three, and the operational amplifiers are not less than two.

[0011] Further, the input end of the voltage inverter U1 is grounded through the capacitor C6, the output end of the voltage inverter U1 is grounded through the parallel capacitor C8, and the capacitor C7 is connected between the CFLY+ end and the CFLY- end of the voltage inverter U1.

[0012] Further, the output end of the linear voltage stabilizer LDO2 is grounded through the resistor R14 and the resistor R13, and the ADJ end of the linear voltage stabilizer LDO2 is grounded through the capacitor C9, and the capacitor C9 is connected with the resistor R13 in parallel.

[0013] In summary, the application has the following beneficial effects:

[0014] (1) The power-on and power-off timing control of the radio frequency chip is realized by using a pure analog circuit, without the need of a microcontroller and complex peripheral components, so that the circuit board space can be significantly reduced, and the structure is simple and small in size, and easy to integrate.

[0015] (2) The inductive element is not used, so that the performance degradation caused by the inductor under high-frequency signals is avoided, the robustness is higher in a high-frequency radio frequency environment, the influence of electromagnetic interference is reduced, and the stability and reliability of the utility model are significantly improved.

[0016] (3) The positive voltage and the negative voltage output by the voltage conversion module have a wide load range characteristic, and the load change will not affect the stability of the output voltage. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 The utility model discloses a multi-channel timing circuit.

[0018] Figure 1 The utility model discloses a multi-channel timing circuit.

[0019] Figure 2 The utility model discloses a multi-channel timing circuit.

[0020] Figure 3 The utility model discloses a multi-channel timing circuit. DETAILED DESCRIPTION

[0021] The utility model will be further explained in detail in connection with the drawings.

[0022] It should be noted that, for the sake of convenience, the direction in the following description is consistent with the direction of the drawings, but does not limit the structure of the utility model.

[0023] As shown in Figure 1 The utility model discloses a kind of multi-channel pure analog timing circuit for gallium arsenide radio frequency frequency multiplication chip, including voltage conversion module and timing module, the output end of voltage conversion module is connected timing module, the output timing of the output end VD of timing module is realized by timing module, wherein:

[0024] The input end VCC of the voltage conversion module is connected with the input end of the linear voltage stabilizing chip LDO1 and the input end of the linear voltage stabilizing chip LDO2 after being filtered and stabilized by the capacitor T1. The output VI of the linear voltage stabilizing chip LDO1 is connected with the input end of the voltage inverter U1, and the output V+ is outputted after being converted by the linear voltage stabilizing chip LDO2. The output-VI of the voltage inverter U1 and the output V+ of the linear voltage stabilizing chip LDO2 are connected with two input ends of the timing module respectively. The output V+ is outputted by the linear voltage stabilizer LDO2. The linear voltage stabilizer itself realizes strong robustness to load change through closed-loop feedback control and dynamic current adjustment, and the output voltage is not affected by the subsequent load. The output end of the linear voltage stabilizer LDO2 is grounded through the resistor R14 and the resistor R13. By adjusting the resistance values of the resistor R13 and the resistor R14, the appropriate V+ is outputted to meet the drain voltage of the gallium arsenide radio frequency frequency multiplication chip. The ADJ end of the linear voltage stabilizer LDO2 is grounded through the capacitor C9, and the capacitor C9 is connected with the resistor R13 in parallel. The input end of the voltage inverter U1 is grounded through the capacitor C6, the output end of the voltage inverter U1 is grounded through the parallel capacitor C8, and the capacitor C7 is connected between the CFLY+ end and the CFLY- end of the voltage inverter U1.

[0025] The timing module comprises the switching diode D1, the NPN triode U5 and the PMOS field effect tube Q1. The cathode of the switching diode D1 is connected with the output-VI of the voltage inverter U1, the anode of the switching diode D1 is connected with the emitter of the NPN triode U5, and the switching diode D1 can avoid high reverse voltage, thereby protecting the emitter of the NPN triode U5. The base of the NPN triode U5 is connected with the anode of the switching diode D1 through the resistor R5, and the base of the NPN triode U5 is grounded through the resistor R6. The resistance values of the resistor R5 and the resistor R6 determine the establishment speed of the base current, thereby changing the time required for the NPN triode U5 to switch from the cut-off state to the conduction state, and further changing the switching behavior of the PMOS field effect tube Q1. The collector of the NPN triode U5 is connected with the gate of the PMOS field effect tube Q1, and the resistor R7 is connected between the gate and the source of the PMOS field effect tube Q1. The resistor R7 plays a role in limiting the gate current, and the resistor R7 can accelerate the turn-off of the PMOS field effect tube Q1 when the power is turned off. The timing module composed of the switching diode D1, the NPN triode U5, the PMOS field effect tube Q1, the resistor R5, the resistor R6 and the resistor R7 realizes that the voltage is first added to the gate and then to the drain when the radio frequency chip is powered on, and the drain is turned off before the gate when the power is turned off, thereby protecting the gate and the drain of the chip and avoiding damage to the chip. The source of the PMOS field effect tube Q1 is connected with the output V+ of the linear voltage stabilizing chip LDO2, and the drain of the PMOS field effect tube Q1 is the output VD of the timing module.

[0026] The utility model also includes multi -voltage output module, the input end of multi -voltage output module is the input end of voltage divider network connects voltage inverter U1's output-VI, and voltage divider network outputs different voltage values through several operational amplifiers. Figure 1 In the embodiment shown, the voltage divider resistors are four, namely resistors R9, R10, R11 and R12, and different voltage values are output between adjacent two voltage divider resistors. Since the voltage values generated by the voltage divider network will be affected by the subsequent RF chip VG end load, in the utility model, the operational amplifiers and resistors are used to form high-precision voltage followers to convert the output different voltage values into several constant voltage sources with wide load characteristics. Figure 1 In the embodiment shown, the operational amplifiers are three, namely operational amplifier U2, U3 and U4, corresponding to constant voltage sources VG1, VG2 and VG3. The voltage follower output impedance value is extremely low, which can drive the load from high resistance state (more than 1MΩ) to low resistance state (10 ohm level), ensuring that the gate voltage remains stable when the load fluctuates sharply.

[0027] As shown in Figure 2 and Figure 3 The power-on timing diagram and power-off timing diagram of the utility model are shown in Figure 2 and Figure 3 The positive voltage is the voltage value required by the gallium arsenide RF frequency multiplication chip drain, and the negative voltage is the voltage value required by the gallium arsenide RF frequency multiplication chip gate. As Figure 2 It is obvious that when the voltage VCC is powered on, the negative voltage first reaches the voltage value required by the RF frequency multiplication chip gate, and then the positive voltage rises and reaches the voltage value required by the RF frequency multiplication chip drain, which meets the required power-on timing and ensures the correct bias of the RF frequency multiplication chip. Figure 3As can be seen, the positive voltage, i.e. the drain voltage of the radio frequency frequency doubling chip, is first reduced to 0V at the moment of turning off the external voltage VCC, and then the negative voltage, i.e. the drain of the radio frequency frequency doubling chip, is turned off, which is consistent with the power-off timing of the radio frequency frequency doubling chip. By using the timing module of the utility model, the voltage is first applied to the gate of the radio frequency frequency doubling chip and then to the drain of the radio frequency frequency doubling chip at the power-on time; at the power-off time, the drain voltage of the radio frequency frequency doubling chip is first turned off, and then the gate voltage of the radio frequency frequency doubling chip is turned off, thereby protecting the gate and the drain of the chip and avoiding damage to the chip.

[0028] It is obvious for those skilled in the art that the utility model is not limited to the details of the above exemplary embodiments, and the utility model can be realized in other specific forms without departing from the spirit or essential characteristics of the utility model. Therefore, no matter from which point of view, the embodiments should be regarded as exemplary and non-restrictive, and the scope of the utility model is defined by the appended claims rather than the above description, and therefore all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the utility model. Any reference signs in the claims should not be regarded as limiting the claims involved.

Claims

1. A multi-channel pure analog timing circuit for gallium arsenide radio frequency frequency multiplier chips, characterized by, The voltage conversion module and the timing module are included, the output end of the voltage conversion module is connected to the timing module, and the output timing of the output end VD of the timing module is realized through the timing module, wherein: The input end VCC of the voltage conversion module is connected to the input end of the linear voltage stabilizing chip LDO1 and the input end of the linear voltage stabilizing chip LDO2 respectively, the output VI of the linear voltage stabilizing chip LDO1 is connected to the input end of the voltage inverter U1, the output V+ is output after being converted through the linear voltage stabilizing chip LDO2, and the output -VI of the voltage inverter U1 and the output V+ of the linear voltage stabilizing chip LDO2 are connected to two input ends of the timing module respectively. The timing module includes a switching diode D1, an NPN triode U5 and a PMOS field effect tube Q1, the cathode of the switching diode D1 is connected to the output -VI of the voltage inverter U1, the anode of the switching diode D1 is connected to the emitter of the NPN triode U5, the base of the NPN triode U5 is connected to the anode of the switching diode D1 through the resistor R5, the base of the NPN triode U5 is grounded through the resistor R6, the collector of the NPN triode U5 is connected to the gate of the PMOS field effect tube Q1, the resistor R7 is connected between the gate and the source of the PMOS field effect tube Q1, the source of the PMOS field effect tube Q1 is connected to the output V+ of the linear voltage stabilizing chip LDO2, and the drain of the PMOS field effect tube Q1 is the output VD of the timing module.

2. A multi-channel pure analog timing circuit for gallium arsenide radio frequency frequency multiplier chips as defined in claim 1, wherein, The multiple voltage output module is further included, the input end of the multiple voltage output module, namely the input end of the voltage dividing network, is connected to the output -VI of the voltage inverter U1, and the voltage dividing network outputs different voltage values through a plurality of operational amplifiers.

3. A multi-channel all-analog timing circuit for GaAs RF frequency multiplier chips as defined in claim 2, wherein, The voltage dividing network includes a plurality of series-connected voltage dividing resistors, and the voltage dividing network is grounded through the plurality of series-connected voltage dividing resistors; the positive input ends of the plurality of operational amplifiers are connected between two adjacent voltage dividing resistors respectively, the resistor is connected between the reverse input end and the output end of each operational amplifier, thereby forming a high-precision voltage follower, and the output end of each operational amplifier is a constant voltage source with a wide load range characteristic.

4. A multi-channel pure analog timing circuit for gallium arsenide radio frequency frequency multiplier chips as defined in claim 3, wherein, The voltage dividing resistors of the voltage dividing network are not less than three, and the operational amplifiers are not less than two.

5. A multi-channel all-analog timing circuit for GaAs RF frequency multiplier chips as defined in claim 1, wherein, The input end of the voltage inverter U1 is grounded through the capacitor C6, the output end of the voltage inverter U1 is grounded through the parallel capacitor C8, and the capacitor C7 is connected between the CFLY+ end and the CFLY- end of the voltage inverter U1.

6. A multi-channel all-analog timing circuit for GaAs RF frequency multiplier chips as defined in claim 1, wherein, The output end of the linear voltage stabilizing chip LDO2 is grounded through the resistor R14 and the resistor R13, the ADJ end of the linear voltage stabilizing chip LDO2 is grounded through the capacitor C9, and the capacitor C9 is connected in parallel with the resistor R13.

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