Extensible node HDMI intelligent wire harness system based on optical fiber

Abstract

The utility model discloses an extensible node HDMI intelligent wire harness system based on an optical fiber. The system comprises a root node, at least one child node and an optical transmission link. The root node receives a signal through the HDMI input interface, the signal is coded and serialized by the FPGA chip after being processed by the decoding chip, and then the signal is converted into an optical signal through the SFP optical module and is transmitted through an optical fiber; each child node is provided with an uplink SFP interface and a downlink SFP interface, an FPGA chip of each child node forwards one path of received optical signals to realize cascade expansion, deserializes and decodes the other path of signals to restore video data, and finally outputs the signals through an HDMI encoding chip and an output interface; the system adopts single-fiber optical transmission and FPGA programmable processing technologies, has the characteristics of low cost, high reliability, easiness in deployment and programmability, and is suitable for scenes requiring high-definition video signal distributed transmission and expansion.

Description

TECHNICAL FIELD

[0001] The utility model relates to multimedia signal transmission technical field, concretely relates to a scalable node HDMI intelligent wiring harness system based on optical fiber. BACKGROUND

[0002] CN 105045549 A discloses a kind of VGA and PS / 2 signal transmission system based on FPGA, to realize the single-fiber light transmission of high-definition VGA signal without delay without compression and the transparent transmission of PS / 2 keyboard mouse, the invention fails to realize VGA signal cascade;CN 110049295 B discloses a kind of single-fiber multi-channel video transmission receiver, the technical scheme of the invention solves the transmission problem of long-distance single-fiber multi-input video data by DVI / HDMI optical fiber module, optical fiber to DVI / HDMI module solves, but the invention does not disclose cascade transmission technical scheme.Existing multimedia signal transmission technology uses HDMI distributor cascade to realize cascade, with high cost, cascade layer number is within 3 layers, the following defects are possessed by the existing cascade mode to realize multi-node HDMI input signal transmission:

[0003] 1. high cost: need multi-stage distributor series connection, equipment and wiring cost increase significantly;

[0004] 2. poor expansibility: cascade layer number is limited (usually ≤3 layers), it is difficult to meet large-scale node demand;

[0005] 3. signal attenuation is serious: signal quality drops obviously when long-distance transmission;

[0006] 4. wiring is complex: need to connect multiple cables, occupy space and maintain difficult;

[0007] Therefore, in view of the above disclosed patents, we have developed a kind of scalable node HDMI intelligent wiring harness system based on optical fiber, which can save cost and realize multi-stage cascade. CONTENT OF UTILITY MODEL

[0008] The utility model aims at at least one of the technical problems existing in the prior art, and therefore, the utility model embodiment proposes a scalable node HDMI intelligent wiring harness system based on optical fiber, adopts single-fiber optical transmission, FPGA programmable processing and distributed node architecture, and has low cost, high reliability, easy deployment and programmable characteristics.

[0009] To achieve the above purpose, the utility model provides the following technical scheme: a scalable node HDMI intelligent wiring harness system based on optical fiber, characterized by comprising: root node, at least one subnode, at least one optical transmission link, at least two SFP optical modules;

[0010] The root node comprises an HDMI decoding chip, a root node FPGA chip, and a root node SFP interface, and is configured to receive an HDMI input signal; the HDMI decoding chip decodes the HDMI input signal into RGB parallel data, a pixel clock, and a line field synchronization signal; the root node FPGA chip performs 8b / 10b encoding and serialization processing on the RGB parallel data to generate a high-speed serial signal connected with the SFP interface; and the SFP optical module is connected with the root node SFP interface to convert the high-speed serial signal into an optical signal and transmit the optical signal through an optical transmission link;

[0011] The sub-node is configured to cascade a next sub-node and output an HDMI input signal, and comprises a sub-node FPGA chip, an HDMI encoding chip, a sub-node uplink SFP interface, and a sub-node downlink SFP interface; the sub-node uplink SFP interface is connected with an SFP optical module in series at one end of the optical transmission link, and the other end of the optical transmission link is connected with the root node SFP optical module; the sub-node FPGA chip is connected with the sub-node uplink SFP interface and the sub-node downlink SFP interface; after receiving the root node optical signal, the sub-node FPGA chip processes the root node optical signal in two ways: a first path optical signal is connected with an SFP optical module through the sub-node downlink SFP interface and is forwarded to a sub-node uplink SFP interface of a next sub-node, the sub-node FPGA chip performs deserialization and 8b / 10b decoding on a second path optical signal, restores RGB parallel data, and generates a synchronization signal; and the HDMI encoding chip encodes the restored RGB parallel data and outputs an HDMI input signal through an HDMI interface;

[0012] The optical transmission link comprises an LC optical fiber jumper for transmitting optical signals between the root node and the sub-node.

[0013] Further, the SFP optical module is an SFP+ packaged single-mode or multi-mode optical module.

[0014] Further, the root node and the sub-node FPGA chips realize serialization and deserialization through an integrated SerDes interface.

[0015] Further, the 8b / 10b encoding is configured to ensure direct current balance and clock recovery of signal transmission.

[0016] Further, the sub-node FPGA chip performs clock reconfiguration and equalization on the first path forwarded optical signal to eliminate accumulated jitter in cascade transmission, and the sub-node independently controls display content of an HDMI output signal.

[0017] Further, the optical transmission link further comprises a backup optical transmission link, and the FPGA chip of the sub-node automatically switches to the backup optical transmission link when the main optical transmission link is detected to be faulty, thereby supporting ring topology deployment.

[0018] Further, the HDMI decoding chip of the root node and the HDMI encoding chip of the sub-node respectively support HDMI2.0 protocol, and are compatible with 4K@60Hz resolution and HDCP2.2 encryption standard.

[0019] Compared with the prior art, the utility model has the advantages that:

[0020] The multi-node intelligent HDMI wire harness system designed according to the above scheme solves the problems of poor cascading expansibility, serious signal attenuation, complex wiring, high cost and the like in the prior art scheme. The multi-node intelligent HDMI wire harness system in the embodiment adopts single-fiber optical transmission, FPGA programmable processing and distributed nodes with low cost, high reliability, easy deployment and programmable characteristics. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 A schematic diagram of an expandable node HDMI intelligent wire harness system based on optical fibers according to an embodiment of the utility model;

[0022] Figure 2 A schematic diagram of a root node internal module framework of an expandable node HDMI intelligent wire harness system based on optical fibers according to an embodiment of the utility model;

[0023] Figure 3 A schematic diagram of a sub-node internal module framework of an expandable node HDMI intelligent wire harness system based on optical fibers according to an embodiment of the utility model;

[0024] Figure 4 A system block diagram of an expandable node HDMI intelligent wire harness system based on optical fibers according to an embodiment of the utility model;

[0025] Figure 5 A signal processing flowchart of an expandable node HDMI intelligent wire harness system based on optical fibers according to an embodiment of the utility model. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the utility model will be clearly and completely described below with reference to the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the utility model.

[0027] Please refer toFigure 1 and Figure 5 The utility model discloses a kind of scalable node HDMI intelligent wiring harness systems based on optical fiber, and the system includes root node, at least one subnode, at least one optical transmission link, at least two SFP optical modules;

[0028] Please refer to Figure 2 Root node includes HDMI input interface, HDMI decoding chip, root node FPGA chip, root node SFP interface;

[0029] Please refer to Figure 3 Subnode includes uplink SFP interface, downlink SFP interface, subnode FPGA chip, HDMI decoding chip, HDMI output interface;

[0030] Root node HDMI input interface connects host HDMI interface, and root node SFP interface connects SFP optical module again with first optical transmission link one end, another SFP optical module is connected to the other end of first optical transmission link, and another end of another SFP optical module is connected with the uplink SFP interface of first subnode, and the downlink SFP interface of first subnode is connected with the second optical transmission link one end after connecting SFP optical module, and the next subnode uplink SFP interface is connected after the other end of second optical transmission link is connected SFP optical module again, and multiple subnodes are realized in this way in series.

[0031] Specifically, the connection relationship of each part is that root node FPGA chip receives HDMI input signal, and after decoding, data format reorganization, 8b / 10b encoding and serialization are carried out through FPGA, and optical signal transmission is converted through SFP optical module;

[0032] Subnode receives optical signal through optical module, and is processed by two ways after subnode FPGA chip, one way of optical signal is directly forwarded to the uplink SFP interface of lower node through downlink SFP interface, SFP optical module;Another way is through FPGA chip deserialization, decoding, restores RGB signal and generates clock and line field signal, and after outputting through HDMI encoding chip, it is outputted to display device by HDMI output interface;

[0033] In the embodiment, SFP optical module can adopt single-mode / multi-mode optical module.

[0034] Optical transmission link includes LC interface optical fiber, and can support 1m-20km transmission distance.

[0035] Further, please refer to Figure 2 In the embodiment, the root node part is further described as follows:

[0036] The root node hardware components include a root node chipset: including an HDMI decoding chip and an FPGA chip. In the embodiment, the HDMI decoding chip can be selected from the model MS7200 chip, which supports the HDMI 2.0 protocol, has a maximum resolution of 4K@60Hz, is compatible with HDCP 2.2, and ensures high-quality decoding of the HDMI input signal source.

[0037] In the embodiment, the root node FPGA chip can be selected from the model XCZU4EV-SFVC784-1-I. The chip adopts the Xilinx Zynq UltraScale+ MPSoC architecture, integrates an ARM Cortex-A53 processor and a programmable logic unit, realizes the collaborative design of signal processing and control, supports a high-speed SerDes interface (16.3 Gbps) to meet the 8b / 10b encoding and serialization requirements, and has a dynamic reconfigurable feature to support subsequent protocol upgrades, such as the HDMI 2.1 protocol.

[0038] Please refer to Figure 3 In the embodiment, the sub-node part is further described as follows:

[0039] The sub-node includes an HDMI encoding chip, an FPGA chip, an SFP interface, an HDMI output interface, and an SFP+ optical module. The HDMI encoding chip can be selected from the model MS7210, which can be designed in combination with the MS7200 chip, supports RGB to TMDS signal conversion, and has an output compatible with the HDMI standard interface. The sub-node FPGA chip can be selected from the same FPGA chip as the root node. The root node and the sub-node simplify the supply chain management by using the same chip model, while ensuring the consistency of the encoding and decoding logic.

[0040] The root node HDMI decoding chip outputs R, G, B, HS / VS, pclk, and I2C to the root node FPGA chip, and the root node FPGA chip outputs to the SFP interface, realizing SFP photoelectric conversion.

[0041] The sub-node SFP interface receives the optical signal from the root node, performs photoelectric conversion, and then inputs to the sub-node FPGA chip. The FPGA chip outputs R, G, B, HS / VS, pclk, and I2C signals to the HDMI encoding chip, which outputs TDMS high-speed signals and low-speed auxiliary signals to the HDMI output interface, connects the HDMI data line, and then outputs to the display. At the same time, the sub-node FPGA chip outputs electrical signals to the SFP interface, realizes photoelectric conversion, and then connects the SFP interface of the next level sub-node through the optical module and the optical fiber line. Similarly, the next level sub-node processing method is connected with the current level sub-node connection method.

[0042] The optical module connected with the child node SFP interface can select SFP+ optical module, for example, a single-mode module can be used, for example, the model is: Finisar FTLX1475D3BCL, which supports 1310nm wavelength, and the transmission distance can reach 20km, and is suitable for cross-floor or long-distance industrial scenarios;

[0043] The SFP+ optical module connected with the child node SFP interface can also be a multi-mode module, such as the model: H3C SFP-10G-SR; this model supports 850nm wavelength, and the transmission distance is ≤550m, and is suitable for short-distance dense deployment scenarios.

[0044] For optical transmission link, the transmission medium can be selected as LC single-mode optical fiber jumper, which has low loss (≤0.3dB / km), anti-electromagnetic interference, and is suitable for complex electromagnetic conditions in industrial environment; supports hot plug, and is convenient for on-site maintenance and expansion.

[0045] Please refer to Figure 4 and Figure 5 , the working principle and process of the system are described.

[0046] In this embodiment, the root node signal processing process is described.

[0047] 1. HDMI input signal input and decoding process:

[0048] The root node HDMI decoding chip, that is, the MS7200 chip, receives the HDMI TMDS signal, decodes it into RGB 4:4:4 format, pixel clock (PCLK) and line field synchronization signal (HSYNC / VSYNC); supports EDID simulation function, and ensures compatibility with signal source device.

[0049] 2. Root node FPGA data processing process:

[0050] The root node FPGA chip arranges the RGB signal decoded by the HDMI decoding chip according to the pixel point order, reorganizes the data, generates parallel data stream; then, 8b / 10b encoding is realized through Xilinx IP core, to ensure DC balance and clock recovery; the built-in GTY transceiver of the FPGA chip is used to serialize the 10b data stream into 10Gbps high-speed signal, and after the serialization high-band signal is converted into optical signal, the SFP optical module is driven to send.

[0051] Please refer to Figure 4 and Figure 5 , the working principle and process of the system are described.

[0052] 1. Sub-node optical signal receiving and branching process:

[0053] The sub-node FPGA chip receives the optical signal transmitted by the optical module through the SFP interface, and processes it in two ways:

[0054] In the first way, the sub-node forwarding path is that the sub-node FPGA chip directly forwards the optical signal received by the SFP interface to the lower node through the lower SFP interface, and the signal delay is less than 1 μs;

[0055] In the second way, the sub-node FPGA chip decoding path is that the sub-node FPGA chip performs clock data recovery (CDR), deserialization and 8b / 10b decoding on the optical signal received by the SFP interface, restores the RGB parallel data.

[0056] 2, HDMI input signal regeneration process:

[0057] The sub-node FPGA chip generates PCLK, HSYNC / VSYNC signals synchronized with the source end, ensuring that the display device has no tearing or jitter;

[0058] The sub-node HDMI encoding MS7210 chip re-encodes the RGB signal into an HDMI TMDS signal, which is output to the display terminal through the HDMI interface.

[0059] 3, Sub-node cascade expansion

[0060] Through signal regeneration and dynamic power control, multiple sub-nodes are cascaded and expanded, and the implementation is as follows:

[0061] Each sub-node FPGA chip performs clock reconfiguration and equalization on the forwarding signal to eliminate accumulated jitter and implement signal regeneration strategy;

[0062] The sub-node selects the SFP optical module, which supports DOM (digital optical monitoring) and automatically adjusts the transmission power according to the transmission distance, performs dynamic power control, and prolongs the service life of the module.

[0063] In this embodiment, to improve the reliability of the system, the reliability and fault tolerance are described as follows:

[0064] A double-fiber link can be deployed at a key sub-node. When the FPGA chip detects a main link failure, it automatically switches to a backup optical transmission link to realize signal transmission link redundant path configuration.

[0065] A "ring topology" deployment can also be used to avoid single-point failure and system paralysis.

[0066] To further improve the reliability of the system, the SFP optical module supports hot plugging, and the SFP interface and fiber jumper support hot plugging, which is convenient for on-site maintenance and node expansion.

[0067] To verify the experimental effect of the system, the following examples and test data, laboratory test results:

[0068] Transmission distance:

[0069] Single-mode optical fiber: after 20km transmission, the signal bit error rate (BER) is less than 1E-12;

[0070] Multimode optical fiber: after 300m transmission, there is no visible loss of picture quality.

[0071] Cascading performance: 10 levels of sub-nodes in series, end-to-end delay < 5ms, meeting the real-time monitoring requirements;

[0072] The synchronization error of each node is less than 1 frame (16ms@60Hz). Cost comparison example:

[0073] Traditional scheme: 10-node system requires 9 HDMI distributors + 300m copper cable, total cost is about $4500;

[0074] The scheme of the application: 10-node system only needs 10 SFP modules + 200m single-mode optical fiber, the total cost is about $1200. The technical scheme of the embodiment significantly reduces the cost.

[0075] The expandable node HDMI intelligent wiring harness system based on optical fiber in the utility model can be used in the following typical application scenarios.

[0076] Smart city traffic command center: single signal source drives multiple intersection monitoring screens, supports dynamic information switching;

[0077] Medical operating room multi-screen system: the main surgeon operating table signal is synchronized to the auxiliary screen in real time, and the optical fiber anti-interference feature avoids electromagnetic interference risk;

[0078] Theme park immersive experience: long-distance series of multiple projection devices, realizing seamless visual linkage.

[0079] The multi-node intelligent HDMI wiring harness system designed according to the above scheme solves the problems of poor cascading expansion, serious signal attenuation, complex wiring, high cost and other problems in the prior art. The multi-node intelligent HDMI wiring harness system in the embodiment adopts single-fiber optical transmission, FPGA programmable processing and distributed nodes with low cost, high reliability, easy deployment and programmable characteristics.

[0080] It is to be noted that, in the present document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0081] While the embodiments of the present application have been illustrated and described, it will be understood by those skilled in the art that various changes, modifications, substitutions, and alterations can be made therein without departing from the spirit and scope of the application, which is defined by the appended claims and their equivalents.

Claims

1. A scalable node fiber-based HDMI intelligent harness system, characterized by, The application relates to a root node, at least one sub-node, at least one optical transmission link and at least two SFP optical modules. The root node comprises an HDMI input interface, an HDMI decoding chip, a root node FPGA chip and a root node SFP interface, the HDMI input interface is used for receiving an HDMI input signal, the HDMI decoding chip decodes the HDMI input signal into RGB parallel data, a pixel clock and a line field synchronization signal, the root node FPGA chip performs 8b / 10b encoding and serialization processing on the RGB parallel data to generate a high-speed serial signal connected with the SFP interface, and the SFP optical module is connected with the root node SFP interface to convert the high-speed serial signal into an optical signal and transmit the optical signal through the optical transmission link. The sub-node is used for cascading a next sub-node and outputting an HDMI input signal, and the sub-node comprises a sub-node FPGA chip, an HDMI encoding chip, a sub-node upper connection SFP interface, a sub-node lower connection SFP interface and an HDMI output interface, the sub-node upper connection SFP interface is connected with one SFP optical module and one end of the optical transmission link in series, and the other end of the optical transmission link is connected with the root node SFP optical module; the sub-node FPGA chip is connected with the sub-node upper connection SFP interface and the sub-node lower connection SFP interface, the sub-node FPGA chip processes two paths after receiving the root node optical signal: the first path optical signal is connected with an SFP optical module through the sub-node lower connection SFP interface and is forwarded to a sub-node upper connection SFP interface of a lower sub-node, the sub-node FPGA chip performs deserialization and 8b / 10b decoding on the second path optical signal, restores RGB parallel data and generates a synchronization signal, the HDMI encoding chip encodes the restored RGB parallel data into an HDMI output signal, and the HDMI output interface outputs the HDMI output signal. The optical transmission link comprises an LC optical fiber jumper for transmitting the optical signal. The SFP optical module is an SFP+ packaged single-mode or multi-mode optical module.

2. The scalable node fiber-based HDMI intelligent harness system of claim 1, wherein, The root node and the sub-node FPGA chips realize serialization and deserialization through integrated SerDes interfaces.

3. The scalable node fiber-based HDMI intelligent harness system of claim 1, wherein, The 8b / 10b encoding is used for guaranteeing direct current balance and clock recovery of signal transmission.

4. The scalable node fiber-based HDMI intelligent harness system of claim 1, wherein, The sub-node FPGA chip performs clock reorganization and equalization on the first path forwarding optical signal to eliminate accumulated jitter in cascaded transmission, and the sub-node independently controls display content of the HDMI output signal.

5. The scalable node fiber-based HDMI intelligent harness system of claim 1, wherein, The optical transmission link further comprises a backup optical transmission link, the sub-node FPGA chip automatically switches to the backup optical transmission link when detecting that a main optical transmission link fails, and supports ring topology deployment.

6. The scalable node fiber-based HDMI intelligent harness system of claim 1, wherein, The root node HDMI decoding chip and the sub-node HDMI encoding chip respectively support HDMI2.0 protocol, and are compatible with 4K@60Hz resolution and HDCP2.2 encryption standards.

7. The scalable node fiber-based HDMI intelligent harness system of claim 1, wherein, ​

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