LED chip with vertical structure and light-emitting device

Abstract

The utility model discloses a vertical-structure LED chip and a light-emitting device. The vertical-structure LED chip comprises a substrate, a bonding metal layer, a first insulating layer, a second reflection structure and an epitaxial laminated layer, wherein the bonding metal layer and the first insulating layer are located on the surface of one side of the substrate. The epitaxial laminated layer comprises a first type semiconductor layer, an active layer and a second type semiconductor layer which are sequentially laminated in the direction away from the substrate; the epitaxial laminated layer is provided with a through hole which at least penetrates through the first type semiconductor layer and the active layer and exposes part of the second type semiconductor layer; and bosses corresponding to the through holes are arranged on the surface of one side, deviating from the active layer, of the second type semiconductor layer. The boss corresponding to the through hole is arranged, so that the light emitted by the LED chip is more fully scattered in the through hole area, the light emitting efficiency of the LED chip is improved, and the brightness of the LED chip in the through hole area is improved.

Description

Technical Field

[0001] This utility model relates to the field of light-emitting diode technology, and more specifically, to a vertical structure LED chip and light-emitting device. Background Technology

[0002] LED chips are the core components of solid-state lighting terminals, possessing numerous advantages such as long lifespan, high reliability, and high electro-optical conversion efficiency. Improving the brightness of LED chips relies on enhancing two efficiencies: internal quantum efficiency and external quantum efficiency. The improvement of external quantum efficiency primarily depends on techniques such as growing distributed Bragg reflectors, forming mirrors on semiconductor stacks, and roughening the surface to increase light extraction efficiency.

[0003] Existing LED chips include horizontal and vertical structures. Vertical LEDs are obtained by transferring the semiconductor structure to a substrate with better conductivity and thermal conductivity, and removing the original epitaxial growth substrate. Existing through-hole vertical LED chips include through-holes that penetrate at least through a first-type semiconductor layer and an active layer, exposing a portion of the surface of a second-type semiconductor layer. A bonding metal layer forms an electrical connection with the second-type semiconductor layer through this through-hole.

[0004] To improve external quantum efficiency, the principle of forming a reflector on a semiconductor structure is to use a reflective layer to reflect the light emitted from the epitaxial layer to the light-emitting surface, thereby improving the reflection efficiency. Some existing through-hole vertical structure LED chips, in addition to setting a reflective layer on the side of the first type semiconductor layer away from the active layer, also form a reflective layer on the bonding metal layer to improve the reflected light output. However, even with the addition of a reflective layer on the bonding metal layer, the light reflected from the through-hole region of the semiconductor structure is not sufficiently scattered by the light-emitting surface. This results in an increase in the amount of reflected light output but not a simultaneous increase in the amount of light output from the through-hole region, making the through-hole region of the semiconductor structure significantly darker than other light-emitting regions.

[0005] To improve external quantum efficiency, surface roughening enhances the light extraction efficiency of LED chips by utilizing the uneven structure of the LED's light-emitting surface to scatter or guide light at the total internal reflection angle out of or out of the chip, thereby increasing the proportion of light that can be emitted outside the LED. However, most existing LED chips roughen the entire light-emitting surface without considering the difference between the via region and other light-emitting regions of the semiconductor structure, thus failing to effectively improve the scattering efficiency of the via region. Utility Model Content

[0006] In view of this, the present invention provides a vertical structure LED chip and a light-emitting device, which can improve the brightness of the through-hole area of ​​the vertical structure LED chip.

[0007] To achieve the above objectives, the technical solution adopted by this utility model is as follows:

[0008] A vertical LED chip, comprising:

[0009] substrate;

[0010] A bonding metal layer, a first insulating layer, a second reflective structure, and an epitaxial stack are sequentially located on one side surface of the substrate;

[0011] The epitaxial stack includes a first type semiconductor layer, an active layer, and a second type semiconductor layer stacked sequentially in a direction away from the substrate; the epitaxial stack has vias that penetrate at least the first type semiconductor layer and the active layer and expose a portion of the second type semiconductor layer; a boss corresponding to the via is provided on the surface of the second type semiconductor layer away from the active layer;

[0012] The second reflective structure covers the surface of the epitaxial stack facing the substrate and is electrically connected to the first type of semiconductor layer; the second reflective structure exposes a portion of the surface facing away from the substrate to form an electrical connection with the outside.

[0013] The first insulating layer covers the surface of the second reflective structure facing the substrate and extends into the through hole;

[0014] The bonding metal layer bonds the first insulating layer and the substrate, and conducts electricity between the substrate and the second type semiconductor layer.

[0015] Furthermore, it also includes a first metallic reflective layer;

[0016] The first metal reflective layer covers at least a portion of the surface of the first insulating layer facing the substrate and extends into the via to be electrically connected to the second type semiconductor layer.

[0017] Furthermore, the protrusion is formed by etching the second type of semiconductor layer;

[0018] Alternatively, the material of the boss may include one or more of titanium nitride, magnesium fluoride, silicon oxide, and undoped semiconductor materials.

[0019] Furthermore, the second reflective structure includes a second insulating layer, a second metallic reflective layer, and a conductive blocking layer; the second insulating layer is disposed on the surface of the epitaxial stack facing the substrate and extends into the via;

[0020] The second metal reflective layer covers a portion of the second insulating layer facing the surface of the substrate, and is electrically connected to the first type of semiconductor layer through the second insulating layer;

[0021] The conductive barrier layer covers the exposed surface of the second metal reflective layer and exposes a portion of the surface facing away from the substrate to form an electrical connection with the outside.

[0022] Furthermore, the projection of the first metal reflective layer onto a first plane parallel to the substrate and the projection of the second metal reflective layer onto the first plane have an overlapping area;

[0023] The outer contour line of the projection of the boss onto the first plane is located within the overlapping area.

[0024] Furthermore, the overlapping area near the edge line of the through hole is the first edge line of the second metal reflective layer;

[0025] The distance L between the outer contour line of the projection of the boss onto the first plane and the first edge line is 1um-6um, including the endpoint value.

[0026] Furthermore, the height difference ΔH between the surface of the boss facing away from the substrate and the surface of the second type semiconductor layer facing away from the substrate ranges from 0.5um to 1.5um, including the endpoint value.

[0027] Furthermore, the second type semiconductor layer has a roughened structure on the surface away from the substrate and / or the boss has a roughened structure on the surface and sidewalls away from the substrate.

[0028] Furthermore, the roughened structure is a protrusion structure with at least two sizes.

[0029] Furthermore, the epitaxial stack is also provided with a first groove; the first groove divides the epitaxial stack into a light-emitting region and a peripheral region surrounding the light-emitting region; the through-hole and the boss are both located in the light-emitting region; the surface of the peripheral region away from the substrate and the surface of the boss away from the substrate are at the same horizontal height.

[0030] Furthermore, the first groove penetrates the epitaxial stack.

[0031] This application also provides a light-emitting device, including a vertically structured LED chip as described in any of the above claims.

[0032] Compared with the prior art, the technical solution provided by this utility model has at least the following advantages:

[0033] The vertical structure LED chip of this application includes a substrate and a bonding metal layer, a first insulating layer, a second reflective structure, and an epitaxial stack located on one side surface of the substrate. The epitaxial stack includes a first type semiconductor layer, an active layer, and a second type semiconductor layer sequentially stacked in a direction away from the substrate; the epitaxial stack has vias that penetrate at least the first type semiconductor layer and the active layer, and expose a portion of the second type semiconductor layer; a boss corresponding to the via is provided on the side surface of the second type semiconductor layer away from the active layer; the second reflective structure covers the surface of the epitaxial stack facing the substrate and is electrically connected to the first type semiconductor layer; the second reflective structure exposes a portion of its surface away from the substrate to form an electrical connection with the outside; the first insulating layer covers the surface of the second reflective structure facing the substrate and extends into the via; the bonding metal layer bonds the first insulating layer and the substrate, and conducts electricity between the substrate and the second type semiconductor layer.

[0034] The vertical structure LED chip of this application, due to the above-mentioned structural configuration, by providing a boss corresponding to the via on the side surface of the second type semiconductor layer away from the active layer, makes the light emitted by the LED chip more fully scattered in the via region, thereby improving the light emission efficiency of the LED chip and increasing the brightness of the LED chip in the via region.

[0035] A roughening structure is provided on the surface of the second type semiconductor layer away from the substrate and / or on the surface and sidewalls of the protrusions away from the substrate to improve the light extraction efficiency of the LED chip. The roughening structure is configured as a protrusion structure with at least two sizes, which can further improve the light extraction efficiency of the LED chip.

[0036] The peripheral region's surface facing away from the substrate and the boss's surface facing away from the substrate are at the same horizontal height, which allows the light emitted and reflected from the light-emitting area to be better distributed within a single core particle rather than spilling out, and can also release some stress to improve the problem of epitaxial layer detachment. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0038] Figure 1 This is a cross-sectional structural diagram of a vertical LED chip according to this application;

[0039] Figure 2 This is a cross-sectional view of another vertical LED chip in this application.

[0040] Figure 3-11This is a schematic diagram of the fabrication process of the vertical structure LED chip in this application.

[0041] Figure label:

[0042] Substrate 1; Bonding metal layer 2; First metal reflective layer 3; First insulating layer 4; Second reflective structure 5; Second insulating layer 51; Second hole 511; Second metal reflective layer 52; Conductive barrier layer 53; Epitaxial stack 6; First type semiconductor layer 61; Active layer 62; Second type semiconductor layer 63; Boss 631; Through hole 64; First trench 65; Overlapping region M; Passivation layer 7; Growth substrate 8; N electrode 9. Detailed Implementation

[0043] To make the content of this utility model clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0044] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0045] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0046] like Figure 1 , 2 As shown, this application provides a vertical structure LED chip, which includes a substrate 1 and a bonding metal layer 2, a first insulating layer 4, a second reflective structure 5, and an epitaxial stack 6 located on one side surface of the substrate 1. The substrate 1 is made of one or more of, but not limited to, Si, Cu, CuW, and Mo. The bonding metal layer is made of one or more of, but not limited to, Au, Sn, Ti, and Ni.

[0047] The epitaxial stack 6 includes a first type semiconductor layer 61, an active layer 62, and a second type semiconductor layer 63 sequentially stacked along a direction away from the substrate 1; the epitaxial stack 6 has vias 64 that penetrate at least the first type semiconductor layer 61 and the active layer 62 and expose a portion of the second type semiconductor layer 63. Figure 4 (As shown in the diagram); a boss 631 corresponding to the via 64 is provided on the surface of the second semiconductor layer 63 facing away from the active layer 62. One of the first semiconductor layer 61 and the second semiconductor layer 63 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. This application uses the example of the first semiconductor layer 61 being a P-type semiconductor layer and the second semiconductor layer 63 being an N-type semiconductor layer for illustration; in this application, the P-type semiconductor layer is P-GaN and the N-type semiconductor layer is N-GaN, but it is not limited to these. In actual use, the materials of the P-type semiconductor layer and the N-type semiconductor layer can be selected as needed. It should be understood that the via 64 may only penetrate the first semiconductor layer 61 and the active layer 62, or the via 64 may extend into the second semiconductor layer 63 to a certain thickness, but not penetrate the second semiconductor layer 63.

[0048] The second reflective structure 5 covers the surface of the epitaxial stack 6 facing the substrate 1 and is electrically connected to the first semiconductor layer 61; the second reflective structure 5 exposes a portion of its surface facing away from the substrate 1 to form an electrical connection with the outside; the first insulating layer 4 covers the surface of the second reflective structure 5 facing the substrate and extends into the via 64. The bonding metal layer 2 bonds the first insulating layer 4 and the substrate 1, and conducts electricity between the substrate 1 and the second semiconductor layer 63.

[0049] Due to the above-mentioned structural configuration, the vertical structure LED chip of this application has a protrusion 631 corresponding to the via 64 on the surface of the second semiconductor layer 63 facing away from the active layer 62, which makes the light emitted by the LED chip more fully scattered in the via 64 region, thereby improving the light emission efficiency of the LED chip and the brightness of the LED chip in the via 64 region.

[0050] In a preferred embodiment based on the above embodiments, the vertical structure LED chip further includes a first metal reflective layer 3. The first metal reflective layer 3 at least covers a portion of the surface of the first insulating layer 4 facing the substrate 1 and extends into the via to be electrically connected to the second type semiconductor layer 63. The provision of the first metal reflective layer 3 increases the reflected light in the via region, further improving the brightness of the LED chip in the via region.

[0051] Specifically, the bonding metal layer 2 extends into the via 64, and the portion of the first metal reflective layer 3 extending into the via 64 encloses the bonding metal layer 2 within the via 64. The first insulating layer 4 covers not only the surface of the first metal reflective layer 3 facing away from the substrate 1, but also the exposed surface of the bonding metal layer 2 facing away from the substrate 1. An N-electrode 9 is also provided on the substrate surface facing away from the epitaxial stack 6. The material of the N-electrode 9 includes, but is not limited to, one or more of Al, Au, Pt, Ti, Ni, and Cr. The first metal reflective layer 3 includes, but is not limited to, a silver reflector.

[0052] In a preferred embodiment, such as Figure 2 As shown, the vertical structure LED chip also includes a passivation layer 7 disposed on the side of the epitaxial stack 6 away from the substrate 1.

[0053] Preferably, in any of the above embodiments, the protrusion 631 is formed by etching the second type semiconductor layer 63. Alternatively, the material of the protrusion 631 includes one or more of titanium nitride, magnesium fluoride, silicon oxide, and undoped semiconductor materials. The undoped semiconductor material can be the same material as the second type semiconductor layer 63, but without N-type or P-type doping. For example, when the second type semiconductor layer 63 is N-GaN, the protrusion can be undoped GaN. The former case is exemplified in this application.

[0054] Preferably, based on any of the above embodiments, the second reflective structure 5 includes a second insulating layer 51, a second metal reflective layer 52, and a conductive barrier layer 53. The second insulating layer 51 is disposed on the surface of the epitaxial stack 6 facing the substrate 1 and extends into the via 64. The second metal reflective layer 52 covers a portion of the surface of the second insulating layer 51 facing the substrate 1 and penetrates the second insulating layer 51 to be electrically connected to the first type semiconductor layer 61. The conductive barrier layer 53 covers the exposed surface of the second metal reflective layer 52 and exposes a portion of its surface facing away from the substrate 1 to form an electrical connection with the outside.

[0055] The second metal reflective layer 52 includes, but is not limited to, a silver reflector, and the conductive barrier layer 53 is made of, but is not limited to, one or more of Au, Pt, Ti, Ni, and Cr. The conductive barrier layer 53 is exposed on a portion of its surface facing away from the substrate 1 by etching the epitaxial stack 6 and the second insulating layer 51 to form an electrical connection with the outside. The first insulating layer 4 covers the surface and sidewalls of the conductive barrier layer 53 facing the substrate 1, insulating and isolating the conductive barrier layer 53 from the first metal reflective layer and the bonding metal layer.

[0056] Optionally, the second insulating layer 51 is provided with a plurality of first holes exposing the first type semiconductor layer 61, and the second metal reflective layer 52 forms an electrical connection with the first type semiconductor layer 61 by being embedded in each of the first holes. This arrangement makes the current distribution more uniform.

[0057] In a preferred embodiment, the projection of the first metal reflective layer 3 onto a first plane parallel to the substrate 1 overlaps with the projection of the second metal reflective layer 52 onto the first plane. The outer contour of the projection of the boss 631 onto the first plane lies within the overlapping area.

[0058] More preferably, the edge line of the overlapping area near the through hole 64 is the first edge line of the second metal reflective layer 52; the distance L between the outer contour line of the projection of the boss 631 on the first plane and the first edge line is 1um-6um, including the endpoint value.

[0059] During the actual research process, the applicant discovered that if the outer contour line of the projection of the boss 631 on the first plane is not within the overlapping area and is located on the side of the overlapping area closer to the through hole 64, the boss 631 cannot improve the brightness of the through hole area; if the outer contour line of the projection of the boss 631 on the first plane is not within the overlapping area and is located on the side of the overlapping area farther from the through hole 64, the effect of the boss 631 in improving the brightness of the through hole area is poor. Therefore, this application improves the brightness of the through hole area by setting the outer contour line of the projection of the boss 631 on the first plane to be within the overlapping area. Moreover, the distance L between the outer contour line of the projection of the boss 631 on the first plane and the first edge line is set in the range of 1um-6um, further improving the brightness improvement effect of the boss 631 on the through hole area.

[0060] The overlapping area is located near the through hole 64. Figure 1 The figure shows that the overlapping area M of the first metal reflective layer 3 and the second metal reflective layer 52 is located within the overlapping area M. As can be seen from the figure, the extension line of the outer contour of the boss 631 lies within the overlapping area M. In this application, the boss is taken as a rectangle, and its outer contour is... Figure 1 The outline of the sidewall of the central boss. That is, Figure 1 The plane containing the second metal reflective layer 52 located on the sidewall of the second insulating layer 51 facing the substrate 1 and towards the through hole 64 is called the second plane. The projection of the second plane onto the first plane is also known as the first edge line. The plane containing the first metal reflective layer 3 located on the sidewall of the first insulating layer 4 facing away from the substrate 1 and away from the through hole 64 is called the third plane. The overlapping region M is the area between the second plane and the third plane. Optionally, the horizontal width of the overlapping region M is 3µm-15µm.

[0061] Based on any of the above embodiments, preferably, the height difference ΔH between the surface of the boss 631 facing away from the substrate 1 and the surface of the second type semiconductor layer 63 facing away from the substrate 1 (e.g.) Figure 11The value range of (as shown) is 0.5um-1.5um. Since the protrusion 631 in this application example is formed by etching the second type semiconductor layer 63, the height difference ΔH is the height difference formed between the surface of the protrusion 631 away from the substrate 1 and the other light-emitting areas of the second type semiconductor layer 63 away from the surface of the substrate 1.

[0062] If the height difference ΔH is too small, the protrusion 631 will not effectively improve brightness; if the height difference ΔH is too large, the second type semiconductor layer 63 is prone to detachment. Therefore, setting the height difference ΔH to a range of 0.5µm-1.5µm effectively improves brightness while preventing the second type semiconductor layer 63 from detaching and affecting the use of the vertical structure LED chip. Figure 11 As shown, the height difference ΔH is also the thickness of the formed boss 631.

[0063] Based on any of the above embodiments, preferably, such as Figure 1 As shown, the second type semiconductor layer 63 has a roughened structure on the surface away from the substrate 1 and / or the boss 631 has a roughened structure on the surface and sidewalls away from the substrate 1.

[0064] Preferably, based on the above embodiments, the roughened structure is a protrusion structure with at least two sizes. Taking the roughened structure on the surface of the second type semiconductor layer 63 away from the substrate 1, and the roughened structure on the surface and sidewalls of the protrusion 631 away from the substrate 1 as an example, the surface of the second type semiconductor layer 63 away from the substrate 1, the surface of the protrusion 631 away from the substrate 1, and the sidewalls can be roughened for the first time using a strong alkaline KOH solution, and then the surface of the second type semiconductor layer 63 away from the substrate 1, the surface of the protrusion 631 away from the substrate 1, and the sidewalls can be roughened for the second time using a weak alkaline developer solution, so as to form a protrusion structure with at least two sizes. The morphology of the protrusion structure is pyramidal.

[0065] In this design, a roughening structure is provided on the surface of the second type semiconductor layer 63 facing away from the substrate 1 and / or on the surface and sidewalls of the protrusion 631 facing away from the substrate 1 to improve the light extraction efficiency of the LED chip. The roughening structure is configured as a protrusion structure with at least two sizes, which can better improve the light extraction efficiency of the LED chip.

[0066] In any of the above embodiments, the epitaxial stack 6 is preferably provided with a first groove 65; the first groove 65 divides the epitaxial stack 6 into a light-emitting region and a peripheral region surrounding the light-emitting region; the through hole 64 and the boss 631 are both located in the light-emitting region; the surface of the peripheral region away from the substrate 1 and the surface of the boss 631 away from the substrate 1 are at the same horizontal height.

[0067] The peripheral region facing away from the substrate 1 and the boss 631 facing away from the substrate 1 are at the same horizontal height, which allows the light emitted and reflected from the light-emitting region to be better distributed in a single core particle rather than spilling out, and can release some stress to improve the problem of epitaxial layer shedding.

[0068] In this application example, the protrusion 631 is formed by etching the second type semiconductor layer 63. Therefore, the surface of the second type semiconductor layer 63 facing away from the substrate 1 in the peripheral region is at the same horizontal height as the surface of the protrusion 631 facing away from the substrate 1. The second type semiconductor layer 63 located in the light-emitting region is the light-emitting region of the second type semiconductor layer 63; at this time, the surface of the protrusion facing away from the substrate is higher than the surface of the remaining area of ​​the second type semiconductor layer 63 facing away from the substrate 1 in the light-emitting region.

[0069] Specifically, such as Figure 1 As shown, the first groove 65 penetrates the epitaxial stack 6. The second insulating layer 51 has a second hole 511 with an opening facing the first groove 65. The second hole 511 exposes a portion of the surface of the conductive barrier layer 53 to form an electrical connection with the outside.

[0070] When the vertical structure LED chip has a first groove 65, the passivation layer 7 can be as follows: Figure 2 As shown, the passivation layer 7 covers the exposed surface of the light-emitting area, the surface of the peripheral area away from the substrate 1, the sidewall of the peripheral area facing the light-emitting area, and part of the bottom of the first groove 65.

[0071] This application also provides a method for manufacturing a vertical structure LED chip, including the following steps: S01: providing a growth substrate 8, wherein the growth substrate 8 includes, but is not limited to, a sapphire substrate.

[0072] S02: As Figure 3 As shown, an epitaxial stack 6 is fabricated on one side surface of the growth substrate 8. The epitaxial stack 6 includes a second-type semiconductor layer 63, an active layer 62, and a first-type semiconductor layer 61, which are sequentially grown in a direction away from the growth substrate 8. Preferably, a buffer layer (not shown) can be grown on the surface of the growth substrate 8 before growing the epitaxial stack 6, and then the epitaxial stack 6 is grown on the surface of the buffer layer away from the growth substrate 8. The buffer layer includes, but is not limited to, U-GaN. It should be understood that other functional layers besides the buffer layer may also be included between the growth substrate 8 and the second-type semiconductor layer 63.

[0073] S03: As Figure 4 As shown, a via 64 is fabricated on the epitaxial stack 6, penetrating at least the first type semiconductor layer 61 and the active layer 62, and exposing the second type semiconductor layer 63. In actual fabrication, the via 64 may only penetrate the first type semiconductor layer 61 and the active layer 62, or the via 64 may extend into the second type semiconductor layer 63 to a certain thickness, but not penetrate the second type semiconductor layer 63.

[0074] S04: As Figure 7 , 8 As shown, a second reflective structure 5 and a first insulating layer 4 are sequentially fabricated on the epitaxial stack 6. The second reflective structure 5 covers the surface of the epitaxial stack 6 facing away from the growth substrate 8 and is electrically connected to the first type semiconductor layer 61. The first insulating layer 4 covers the surface of the second reflective structure 5 facing away from the growth substrate 8 and extends into the via 64.

[0075] S05: The first insulating layer 4 and the substrate 1 are bonded together by the bonding metal layer 2, thus connecting the substrate 1 and the second semiconductor layer 63. In actual fabrication, the bonding metal layer 2 typically includes a first bonding sublayer and a second bonding sublayer. The first bonding sublayer covers the surface of the semi-finished product produced in step S04 away from the growth substrate 8 and extends into the via 64. The second bonding sublayer covers one side surface of the substrate 1. The first and second bonding sublayers are bonded together to form the bonding metal layer 2 to bond the first metal reflective layer 3 and the substrate 1.

[0076] S06: Remove the growth substrate 8.

[0077] S07: As Figure 11 As shown, a protrusion 631 corresponding to the via 64 is formed on the surface of the second type semiconductor layer 63 facing away from the active layer 62. Specifically, when there is a functional layer such as a buffer layer between the growth substrate 8 and the second type semiconductor layer 63, the functional layer such as the buffer layer is removed before the protrusion 631 is formed.

[0078] Optionally, in step S07, the second type semiconductor layer 63 is etched to form the protrusion 631. Alternatively, in step S07, the material used to fabricate the protrusion 631 includes one or more of titanium nitride, magnesium fluoride, silicon oxide, and undoped semiconductor materials; for example, a protrusion material can be grown on the surface of the second type semiconductor layer 63 on the side opposite to the active layer 62, and then the protrusion material in the area not covered by photoresist is removed after coating, exposure, and development to form the protrusion 631. The former is used as an example in this application.

[0079] S08: As Figure 1 As shown, the etched epitaxial stack 6 exposes a portion of the surface of the second reflective structure 5 that is away from the substrate 1.

[0080] Preferably, such as Figure 9 In step S04, after the first insulating layer 4 is fabricated, a first metal reflective layer 3 is also fabricated. The first metal reflective layer 3 covers at least a portion of the first insulating layer 4 away from the surface of the growth substrate 8 and extends into the via 64 to be electrically connected to the second type semiconductor layer 63.

[0081] Preferably, such as Figure 5-7As shown, in step S04, fabricating the second reflective structure 5 includes sequentially growing a second insulating layer 51, a second metal reflective layer 52, and a conductive barrier layer 53. The second insulating layer 51 is disposed on the surface of the epitaxial stack facing away from the growth substrate 8 and extends into the via 64. The second metal reflective layer 52 covers a portion of the second insulating layer 51 facing away from the growth substrate 8 and penetrates the second insulating layer 51 to be electrically connected to the first type semiconductor layer 61. The conductive barrier layer 53 covers the exposed surface of the second metal reflective layer 52.

[0082] The projection of the first metal reflective layer 3 onto a first plane parallel to the substrate 1 overlaps with the projection of the second metal reflective layer 52 onto the first plane. The outer contour line of the projection of the boss 631 onto the first plane lies within the overlapping area. Preferably, the edge line of the overlapping area near the through hole 64 is the first edge line of the second metal reflective layer 52; the distance L between the outer contour line of the projection of the boss 631 onto the first plane and the first edge line is 1µm-6µm, including the endpoint value.

[0083] Preferably, the height difference ΔH between the surface of the protrusion 631 facing away from the substrate 1 and the surface of the second type semiconductor layer 63 facing away from the substrate 1 ranges from 0.5um to 1.5um. Since the protrusion 631 in this application example is formed by etching the second type semiconductor layer 63, the height difference ΔH is the height difference between the surface of the protrusion 631 facing away from the substrate and the remaining light-emitting areas of the second type semiconductor layer 63 facing away from the substrate 1.

[0084] If the height difference ΔH is too small, the protrusions will not effectively improve brightness; if the height difference ΔH is too large, the second semiconductor layer is prone to detachment. Therefore, setting the height difference ΔH within the range of 0.5µm-1.5µm effectively improves brightness while preventing the second semiconductor layer from detaching and affecting the use of the vertically structured LED chip. Figure 11 As shown, the height difference ΔH is also the thickness of the formed boss.

[0085] Preferably, after fabricating the boss 631, a first trench 65 is formed on the epitaxial stack 6. The first trench 65 divides the epitaxial stack 6 into a light-emitting region and a peripheral region surrounding the light-emitting region; both the via 64 and the boss 631 are located in the light-emitting region; the surface of the peripheral region facing away from the substrate 1 and the surface of the boss 631 facing away from the substrate 1 are at the same horizontal height. In this application example, the boss 631 is formed by etching the second type semiconductor layer 63, so the surface of the second type semiconductor layer 63 facing away from the substrate 1 and the surface of the boss 631 facing away from the substrate 1 in the peripheral region are at the same horizontal height. Specifically, during step S08, the first trench 65 is formed on the epitaxial stack and a second hole is formed on the second insulating layer 51 with its opening facing the first trench 65. The second hole exposes a portion of the surface of the conductive barrier layer to form an electrical connection with the outside.

[0086] Preferably, roughening structures are formed on the surface of the second type semiconductor layer 63 away from the substrate 1 and / or on the surface and sidewalls of the boss 631 away from the substrate 1. This application will describe an example where the second type semiconductor layer 63 has a roughening structure on its surface away from the substrate 1, and the boss 631 has a roughening structure on its surface and sidewalls away from the substrate 1. Specifically, after step S08, roughening structures are formed on the surface of the second type semiconductor layer 63 away from the substrate 1, and on the surface and sidewalls of the boss 631 away from the substrate 1, that is, on... Figure 11 After fabricating the first groove and second hole based on the structure shown, a roughened structure is then created to form... Figure 1 The structure shown.

[0087] More preferably, the roughened structure is a protrusion structure with at least two sizes. Specifically, a first roughening is performed using a strong alkaline KOH solution on the surface of the second type semiconductor layer 63 facing away from the substrate 1, the surface of the protrusion 631 facing away from the substrate 1, and the sidewalls thereon. Then, a second roughening is performed using a weak alkaline developer solution on the surface of the second type semiconductor layer 63 facing away from the substrate 1 and the sidewalls of the protrusion 631, to form a protrusion structure with at least two sizes. The protrusion structure has a pyramidal morphology.

[0088] Preferably, such as Figure 2 As shown, after the roughened structure is fabricated, a passivation layer 7 can be fabricated on the side of the epitaxial stack 6 facing away from the substrate 1. The passivation layer 7 covers the exposed surface of the light-emitting area, the surface of the peripheral area facing away from the substrate 1, the sidewall of the peripheral area facing the light-emitting area, and part of the bottom of the first groove 65.

[0089] For any content not mentioned in the method for manufacturing a vertical structure LED chip in this application, please refer to the various embodiments of the vertical structure LED chip described above, and will not be repeated here.

[0090] The method for manufacturing a vertical structure LED chip provided in this application can be used to manufacture the aforementioned vertical structure LED chip, and therefore has all the beneficial effects of the aforementioned vertical structure LED chip.

[0091] This application also provides a light-emitting device, which includes a vertically structured LED chip as described in any of the above claims.

[0092] Those skilled in the art should understand that in the disclosure of this utility model, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as a limitation of this utility model.

[0093] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0094] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A vertical structure LED chip, characterized in that, The application relates to a vertical structure LED chip. The vertical structure LED chip comprises a substrate, a bonding metal layer, a first insulating layer, a second reflective structure and an epitaxial layer successively arranged on one side surface of the substrate. The epitaxial layer comprises a first semiconductor layer, an active layer and a second semiconductor layer successively arranged in a direction away from the substrate. The epitaxial layer is provided with a through hole penetrating through the first semiconductor layer and the active layer and exposing part of the second semiconductor layer. A bump corresponding to the through hole is arranged on a side surface of the second semiconductor layer away from the active layer. The second reflective structure covers a surface of the epitaxial layer facing the substrate and is electrically connected with the first semiconductor layer. The second reflective structure exposes part of the surface away from the substrate to form an electrical connection with the outside. The first insulating layer covers a surface of the second reflective structure facing the substrate and extends into the through hole.

2. A vertical structure LED chip as claimed in claim 1, wherein, The bonding metal layer bonds the first insulating layer and the substrate and connects the substrate and the second semiconductor layer. The vertical structure LED chip further comprises a first metal reflective layer.

3. The vertical structure LED chip of claim 1, wherein, The first metal reflective layer covers at least part of the surface of the first insulating layer facing the substrate and extends into the through hole to be electrically connected with the second semiconductor layer. The bump is formed by etching the second semiconductor layer.

4. A vertical structure LED chip as claimed in claim 2, wherein, Alternatively, the material of the bump comprises one or more of titanium nitride, magnesium fluoride, silicon oxide and undoped semiconductor material. The second reflective structure comprises a second insulating layer, a second metal reflective layer and a conductive barrier layer. The second metal reflective layer covers part of the surface of the second insulating layer facing the substrate and is electrically connected with the first semiconductor layer through the second insulating layer.

5. A vertical structure LED chip as claimed in claim 4, wherein, The conductive barrier layer covers the exposed surface of the second metal reflective layer and exposes part of the surface away from the substrate to form an electrical connection with the outside. The projection of the first metal reflective layer on a first plane parallel to the substrate overlaps with the projection of the second metal reflective layer on the first plane. The outer contour line of the projection of the bump on the first plane is located in the overlapping area.

6. The vertical structure LED chip according to claim 5, wherein The first edge line of the second metal reflective layer is close to the edge line of the through hole.

7. A vertical structure LED chip as claimed in claim 1, wherein, The distance L between the outer contour line of the projection of the bump on the first plane and the first edge line is 1-6 microns, including the end point value.

8. A vertical structure LED chip as set forth in claim 1, wherein, The height difference AH between the surface of the bump away from the substrate and the surface of the second semiconductor layer away from the substrate is 0.5-1.5 microns, including the end point value.

9. A vertical structure LED chip as claimed in claim 8, wherein, The surface of the second semiconductor layer away from the substrate is provided with a roughening structure and / or the surface and sidewall of the bump away from the substrate are provided with a roughening structure. The roughening structure is a convex structure with at least two sizes.

10. The vertical structure LED chip of claim 1, wherein, The epitaxial stack is also provided with a first groove; the first groove divides the epitaxial stack into a light-emitting region and a peripheral region surrounding the light-emitting region; the through hole and the boss are both located in the light-emitting region; the surface of the peripheral region away from the substrate is at the same level as the surface of the boss away from the substrate.

11. A vertical structure LED chip as claimed in claim 10, wherein, The first groove penetrates through the epitaxial stack.

12. A light-emitting device, characterized in that, A vertical structure LED chip comprising any one of the above claims 1-11.

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