LED chip

Abstract

The utility model provides an LED chip. The LED chip comprises a substrate, a first electrode layer in bonding connection with the substrate, an epitaxial laminated layer located on the surface of the side, away from the substrate, of the first electrode layer, a first insulating layer, a first extension electrode, a second insulating layer and a second extension electrode. The epitaxial laminated layer comprises a plurality of light-emitting structures, three-dimensional stacking and interconnection among layers are realized, and the light-emitting structures are connected in parallel through the first expansion electrode and the second expansion electrode, so that under the condition that the voltage of the LED chip is not increased, larger current can pass through the LED chip, and the wavebands of emergent light of the light-emitting structures can be flexibly selected to realize light mixing. Moreover, the epitaxial laminated layer is provided with a plurality of first grooves, and the first expansion electrode and the second expansion electrode share the first grooves to perform current expansion injection without respective grooving to realize current expansion injection, so that uniform transmission of current can be ensured, too much light-emitting area does not need to be compressed, and the light-emitting area is maximized.

Description

Technical Field

[0001] This utility model relates to the field of light-emitting diode technology, and more specifically, to an LED chip. Background Technology

[0002] LED chips are PN junction electroluminescent light-emitting devices. As a new generation of solid-state cold light sources, they have advantages such as high electro-optical conversion efficiency, low energy consumption, long lifespan, energy saving and environmental protection, and high reliability. They are widely used in various fields such as indoor lighting, outdoor lighting, display technology, automotive lights, and plant growth.

[0003] In practical applications, multiple LED chips often need to be connected in series and parallel to match the output of higher current and voltage sources, resulting in a relatively large LED module, which is not conducive to the subsequent integration and packaging of LED chips.

[0004] In order to achieve multi-color mixed light emission or increase light intensity during the use of LED chips, some existing LED chip manufacturing processes involve vertically or side-by-side bonding of multiple epitaxial structures of the same color (or different colors) together. This not only makes the manufacturing process complex and leads to higher costs, but also requires alignment during the bonding process. The alignment accuracy requirements are higher, and alignment errors are easily generated, resulting in a decrease in yield.

[0005] Therefore, this application is intended to solve the problems existing in the prior art. Utility Model Content

[0006] In view of this, the present invention provides an LED chip that can carry a larger current, is smaller in size, and has a simpler manufacturing process.

[0007] To achieve the above objectives, the technical solution adopted by this utility model is as follows:

[0008] An LED chip comprising:

[0009] Substrate:

[0010] A first electrode layer bonded to the substrate, wherein the first electrode layer is a reflective electrode;

[0011] An epitaxial stack is located on the surface of the first electrode layer facing away from the substrate; the epitaxial stack has n semiconductor layers stacked sequentially along the direction facing away from the substrate, n≥3, and n is a positive integer; an active layer is provided between two semiconductor layers, and the semiconductor layers on both sides of each active layer are respectively type I doped and type II doped; the first semiconductor layer is type I doped; the epitaxial stack has a plurality of first trenches, the first trenches exposing the first electrode layer and the i-th semiconductor layer on the surface facing away from the substrate, 2≤i<n, and i is a positive integer;

[0012] A first insulating layer is disposed at least on the sidewall of each of the first trenches and has a connection hole; the connection hole is disposed corresponding to the exposed surface of each of the second type doped semiconductor layers;

[0013] The first extended electrode is stacked on the first insulating layer and electrically connected to each type-1 doped semiconductor and the first electrode layer;

[0014] A second insulating layer, which at least covers the exposed surface of the first extended electrode;

[0015] The second extended electrode is disposed on the first insulating layer and passes through the connecting hole to electrically connect each of the second type doped semiconductor layers;

[0016] The projection of the connecting hole onto a first plane parallel to the substrate does not intersect with the projection of the first extended electrode onto the first plane.

[0017] Furthermore, each of the active layers emits the same light, or at least two active layers emit different light.

[0018] Furthermore, the first insulating layer also covers a portion of the surface of the epitaxial stack that faces away from the substrate;

[0019] The second insulating layer also covers the exposed surface of the first insulating layer and the exposed surface of the epitaxial stack away from the substrate.

[0020] Furthermore, the number of the first extended electrodes corresponds to the number of the first slots, and each is independently disposed in each of the first slots.

[0021] Furthermore, the second extended electrode is integrally formed and extends to the side of the epitaxial stack opposite to the substrate.

[0022] Furthermore, n is 3; the first type of doping is P-type doping, and the second type of doping is N-type doping.

[0023] Furthermore, each of the first trenches is formed by two etching stages; the first etching stage penetrates at least through the third semiconductor layer, the active layer between the third semiconductor layer and the second semiconductor layer, to expose a portion of the surface of the second semiconductor layer; the second etching stage penetrates at least through the second semiconductor layer, the active layer between the second semiconductor layer and the first semiconductor layer, and the first semiconductor layer, to expose a portion of the surface of the first electrode layer.

[0024] Furthermore, it also includes a first ohmic contact layer; the first ohmic contact layer covers a portion of the surface of the third semiconductor layer facing away from the substrate; the first extended electrode extends from the exposed surface of the first electrode layer to the surface of the first ohmic contact layer facing away from the substrate.

[0025] Furthermore, it also includes a second ohmic contact layer; the second ohmic contact layer covers a portion of the exposed surface of the second semiconductor layer away from the substrate; the second extended electrode is electrically connected to the second ohmic contact layer through the connection hole.

[0026] Furthermore, the first electrode layer is one or more of nickel, titanium, gold, silver, magnesium, rhodium, aluminum, and platinum.

[0027] Compared with the prior art, the technical solution provided by this utility model has at least the following advantages:

[0028] This application provides an LED chip comprising: a substrate; a first electrode layer bonded to the substrate, the first electrode layer being a reflective electrode; an epitaxial stack located on the surface of the first electrode layer facing away from the substrate; the epitaxial stack having n semiconductor layers sequentially stacked along the direction facing away from the substrate, n≥3, and n being a positive integer; an active layer being disposed between two semiconductor layers, and the semiconductor layers on both sides of each active layer being type-1 doped and type-2 doped, respectively; the first semiconductor layer being type-1 doped; the epitaxial stack having a plurality of first trenches, the first trenches exposing a portion of the surface of the first electrode layer and the i-th semiconductor layer facing away from the substrate, 2≤i <n, where i is a positive integer; a first insulating layer, which is at least disposed on the sidewall of each first trench, and is provided with a connection hole; the connection hole is disposed corresponding to the exposed surface of each second type doped semiconductor layer; a first extended electrode, which is stacked on the first insulating layer and electrically connects each first type doped semiconductor and the first electrode layer; a second insulating layer, which at least covers the exposed surface of the first extended electrode; a second extended electrode, which is disposed on the first insulating layer and passes through the connection hole and electrically connects each second type doped semiconductor layer; the projection of the connection hole on the first plane parallel to the substrate does not intersect with the projection of the first extended electrode on the first plane. Due to the above structural configuration, the first type doped semiconductor layer, the active layer and the second type doped semiconductor layer in the epitaxial stack form a light-emitting structure. The epitaxial stack contains multiple light-emitting structures, realizing three-dimensional stacking and interconnection between layers. By connecting the light-emitting structures in parallel, the LED chip can not only pass a larger current without increasing the operating voltage, thereby improving the light output power of the LED chip; but also flexibly select the wavelength of the light emitted by the light-emitting structure to achieve light mixing and obtain a richer light output effect. Furthermore, the light-emitting structures in the LED chip are directly epitaxially grown, arranged together without bonding processes, reducing the size of the LED chip, simplifying the manufacturing process, saving manufacturing costs, and facilitating mass production. Moreover, by exposing a portion of the i-th semiconductor layer away from the substrate through the first trench, the projection of the first extended electrode onto a first plane parallel to the substrate does not intersect with the projection of the connecting hole onto the first plane. This allows the first and second extended electrodes to share the first trench for current expansion injection, eliminating the need for separate trenches. This ensures uniform current transmission without compressing too much of the light-emitting area, maximizing the light-emitting area. The vertical structure of the LED chip in this application is also more conducive to heat dissipation.

[0029] The luminous intensity of an LED chip can be multiplied by having each active layer emit the same light; the light emitted by at least two active layers can be mixed by the LED chip.

[0030] The number of first extended electrodes corresponds to the number of first slots, and each is independently set in each first slot, which can reduce the light-emitting area occupied by the first extended electrodes.

[0031] The second extended electrode is integrally formed and extends to the side of the epitaxial stack away from the substrate, facilitating connection to an external power source.

[0032] The epitaxial stack has three semiconductor layers, and the first and third semiconductor layers are both P-type doped. In this structure, the P-type semiconductor layer is grown first, then the active region is grown, and then the N-type semiconductor layer is grown. This structure can be simply called the P-down structure. LED chips with the P-down structure are beneficial for reducing the electrostatic barrier and promoting the injection of electrons and holes.

[0033] The first electrode layer is one or more of the high-reflectivity metals nickel, titanium, gold, silver, magnesium, rhodium, aluminum, and platinum, which increases the light output of the LED chip. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0035] Figure 1 This is a top view of the LED chip in this application;

[0036] Figure 2 This is a cross-sectional view of region AA (M) in the LED chip of this application;

[0037] Figure 3 A top view showing the location of the first slot in this application;

[0038] Figure 4 This is a top view showing the location of the first extended electrode and the connection hole of the LED chip in this application;

[0039] Figure 5 This is a top view schematic diagram showing the location of the second extended electrode in this application;

[0040] Figure 6 This is a top view of the first ohmic contact layer in this application;

[0041] Figure 7 This is a top view of the second ohmic contact layer in this application.

[0042] Figure label:

[0043] Substrate 1; Metal bonding layer 2; First electrode layer 3; Epitaxial stack 4; First semiconductor layer 41; Active layer 42; Second semiconductor layer 43; Third semiconductor layer 44; First trench 45; First insulating layer 5; Connecting hole 51; First extended electrode 6; Second insulating layer 7; Second extended electrode 8; First ohmic contact layer 9; Second ohmic contact layer 10. Detailed Implementation

[0044] To make the content of this utility model clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0045] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0046] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0047] Figure 1 This is a top view of the LED chip. Figure 2 yes Figure 1 A cross-sectional view of region M along AA; the figures in this application are all illustrative when n is 3.

[0048] This application provides an LED chip, which includes a substrate 1, a first electrode layer 3, an epitaxial stack 4, a first insulating layer 5, a first extended electrode 6, a second insulating layer 7, and a second extended electrode 8.

[0049] The first electrode layer 3 is bonded to the substrate 1, and the first electrode layer 3 is a reflective electrode. Specifically, the first electrode layer 3 is bonded to the substrate 1 through a metal bonding layer 2. The metal bonding layer 2 includes, but is not limited to, one or more of gold-indium alloy, gold-tin alloy, nickel-tin alloy, and tin-silver-copper alloy.

[0050] The epitaxial stack 4 is located on the side of the first electrode layer 3 facing away from the substrate 1. The epitaxial stack 4 has n semiconductor layers stacked sequentially along the direction facing away from the substrate 1, where n ≥ 3 and n is a positive integer; an active layer 42 is provided between two semiconductor layers, and the semiconductor layers on both sides of each active layer 42 are respectively type I doped and type II doped; the first semiconductor layer 41 is type I doped; the epitaxial stack 4 has a plurality of first trenches 45, the first trenches 45 exposing the first electrode layer 3 and the i-th semiconductor layer on the surface facing away from the substrate 1, where 2 ≤ i < n and i is a positive integer.

[0051] In this process, one of the first type doping and the second type doping is a P-type doping, and the other is an N-type doping. Optionally, the P-type doped semiconductor layer includes, but is not limited to, one or both of P-type GaN and P-type Al GaN, and the N-type doped semiconductor layer includes, but is not limited to, one or both of N-type GaN and N-type Al GaN.

[0052] A first insulating layer 5 is disposed at least on the sidewall of each first trench 45 and has a connection hole 51; the connection hole 51 is disposed corresponding to the exposed surface of each second-type doped semiconductor layer. A first extended electrode 6 is stacked on the first insulating layer 5 and electrically connects each first-type doped semiconductor layer and the first electrode layer 3. A second insulating layer 7 covers at least the exposed surface of the first extended electrode 6. A second extended electrode 8 is disposed on the first insulating layer 5 and passes through the connection hole 51 to electrically connect each second-type doped semiconductor layer. The projection of the connection hole 51 onto a first plane parallel to the substrate 1 does not intersect with the projection of the first extended electrode 6 onto the first plane.

[0053] Where n can be 3, 4, 5, etc. When n is 3, the LED chip has three semiconductor layers and two active layers 42, containing two light-emitting structures; the value of i is 2, and each first groove 45 exposes the portion of the surface of the first electrode layer 3 and the second semiconductor layer 43 that faces away from the substrate 1. When n is 4, the LED chip has four semiconductor layers and three active layers, containing three light-emitting structures; the value of i is 2 or 3, and each first groove exposes the portion of the surface of the first electrode layer, the second semiconductor layer, and the third semiconductor layer that faces away from the substrate. When n is 5, the LED chip has five semiconductor layers and four active layers, containing four light-emitting structures; the value of i is 2, 3, or 4, and each first groove exposes the portion of the surface of the first electrode layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer that faces away from the substrate 1.

[0054] Due to the aforementioned structural configuration, the LED chip of this application comprises a light-emitting structure consisting of a first-type doped semiconductor layer, an active layer 42, and a second-type doped semiconductor layer in the epitaxial stack 4. The epitaxial stack 4 contains multiple light-emitting structures, achieving three-dimensional stacking and interconnection between layers. By connecting these light-emitting structures in parallel, the LED chip can not only carry a larger current without increasing the operating voltage, thereby improving its light output power, but also flexibly select the wavelength of the emitted light from each structure to achieve light mixing, resulting in richer light output effects. Furthermore, since the light-emitting structures in the LED chip are directly epitaxially grown and arranged without bonding processes, the size of the LED chip is reduced, the manufacturing process is simplified, manufacturing costs are saved, and mass production is facilitated. Furthermore, by exposing the portion of the i-th semiconductor layer facing away from the substrate 1 through the first groove 45, the projection of the first extended electrode 6 onto the first plane parallel to the substrate 1 does not intersect with the projection of the connecting hole 51 onto the first plane. This allows the first extended electrode 6 and the second extended electrode 8 to share the first groove 45 for current extension injection, eliminating the need for separate grooves. This ensures uniform current transmission without compressing too much of the light-emitting area, maximizing the light-emitting area. The vertical structure of the LED chip in this application is also more conducive to heat dissipation.

[0055] Preferably, the substrate 1 is any one of Si, SiC, AlSi, Cu, CuWo, or CuW alloy, which has good electrical and thermal conductivity. The thickness of the substrate 1 is preferably 120μm to 550μm.

[0056] The materials of the first insulating layer 5 and the second insulating layer 7 include, but are not limited to, one or more of silicon dioxide, aluminum oxide, silicon nitride, hydrogen fluoride, and zirconium dioxide.

[0057] The materials of the first extended electrode 6 and the second extended electrode 8 include, but are not limited to, one or more of nickel, titanium, gold, platinum, and gold-tin alloy.

[0058] The first electrode layer 3 is one or more of nickel, titanium, gold, silver, magnesium, rhodium, aluminum, and platinum. Using one or more of these high-reflectivity metals as the first electrode increases the light output of the LED chip.

[0059] Preferably, such as Figure 3 As shown, the array arrangement of each first slot 45 includes, but is not limited to, a rectangular array distribution, a polygonal array distribution, a circular array distribution, etc. In this application, a rectangular array distribution is used as an example. The number of first slots 45 is not limited in this application; it is only used as an example with 9 first slots 45.

[0060] Preferably, based on the above embodiments, each active layer 42 emits the same light, or at least two active layers 42 emit different light. Emitting the same light from each active layer 42 can multiply the luminous intensity of the LED chip; at least two active layers 42 emitting different light can achieve mixed light emission from the LED chip. This application does not limit the material of the active layers 42; the material of each active layer 42 can be selected according to the required emission wavelength of the LED chip. For example, when the emission wavelength of the LED chip is blue or green light, the active layer 42 can be InGaN / GaN multiple quantum wells; when the emission wavelength of the LED chip is ultraviolet light, the active layer 42 can be AlGaN / AlGaN multiple quantum wells.

[0061] Based on any of the above embodiments, preferably, such as Figure 2 As shown, the first insulating layer 5 also covers a portion of the surface of the epitaxial stack 4 facing away from the substrate 1. The second insulating layer 7 also covers the exposed surface of the first insulating layer 5 and the exposed surface of the epitaxial stack 4 facing away from the substrate 1. The second insulating layer 7 has a corresponding opening at the location where the first insulating layer 5 has the connection hole 51, and the second extended electrode 8 is stacked on the second insulating layer 7.

[0062] Preferably, in any of the above embodiments, the number of first extended electrodes 6 corresponds to the number of first slots 45, and each is independently disposed in each first slot 45. That is, a first extended electrode 6 is independently disposed in each first slot 45, and each first extended electrode 6 conducts the first electrode layer 3 and each first type doped semiconductor layer; when the first electrode layer 3 is energized, current is injected into each first type doped semiconductor layer through each first extended electrode 6, realizing current extension injection; this arrangement can reduce the light-emitting area occupied by the first extended electrodes 6. Figure 4 A top view of the first extended electrode 6 is shown. Each gray area in the figure represents the first extended electrode 6. It can be seen from the figure that each first extended electrode 6 occupies only a part of the position of each first slot 45. Each first slot 45 reserves a part of the area for opening the connection hole 51.

[0063] Preferably, in any of the above embodiments, the second extended electrode 8 is integrally formed and extends to the side of the epitaxial stack 4 away from the substrate 1, which facilitates connection to an external power source. That is, the positions of the connection holes 51 correspond to the points where current is injected into the second type doped semiconductor layers. The second extended electrode 8 extends to each connection hole 51 and electrically connects to each second type doped semiconductor layer. When the second extended electrode 8 is energized, current is injected into each second type doped semiconductor layer through each point to achieve current extension injection. Figure 5A top view of the second extended electrode 8 is shown. The location of the connection hole 51 is not limited in this application. In actual use, the location of the connection hole 51 within the first slot 45 can be reasonably selected according to the specific array configuration of the first slot 45, minimizing the light-emitting area occupied by the second extended electrode 8. The number of connection holes 51 corresponding to each first slot 45 is also not limited in this application; for example... Figure 4 As shown, for example, in the first slots 45 distributed in a rectangular row, one connection hole 51 can be set at each of the four vertices of the first slot 45, and two connection holes 51 can be set at each of the other first slots 45. In actual use, the number of connection holes 51 can be reasonably set according to the requirements to achieve a better current expansion effect.

[0064] Preferably, in any of the above embodiments, n is 3, the first type of doping is P-type doping, and the second type of doping is N-type doping. That is, the epitaxial stack 4 has three semiconductor layers, and the first semiconductor layer 41 and the third semiconductor layer 44 are both P-type doped. In this structure, the P-type doped semiconductor layer is grown first, then the active region is grown, and then the N-type doped semiconductor layer is grown. This structure can be simply referred to as a P-down structure. LED chips with a P-down structure are beneficial for reducing the electrostatic barrier and promoting the injection of electrons and holes. It should be understood that when n is greater than 3, the epitaxial stack can also be configured as a P-down structure where the P-type doped semiconductor layer is grown first.

[0065] Specifically, the epitaxial stack 4 includes a P-type doped first semiconductor layer 41, an active layer 42, an N-type doped second semiconductor layer 43, an active layer 42, and a P-type doped third semiconductor layer 44; the epitaxial stack 4 is provided with a plurality of first trenches 45, the first trenches 45 exposing the first electrode layer 3 and the second semiconductor layer 43 on the part of the surface away from the substrate 1.

[0066] Preferably, the first trench 45 is formed by two etching stages; the first etching stage penetrates at least through the active layer 42 between the third semiconductor layer 44 and the second semiconductor layer 43 to expose a portion of the surface of the second semiconductor layer 43; the second etching stage penetrates at least through the active layer 42 between the second semiconductor layer 43 and the first semiconductor layer 41 to expose a portion of the surface of the first electrode layer 3. The horizontal width of the region formed by the first etching stage of the first trench 45 is greater than the horizontal width of the region formed by the second etching stage of the first trench 45.

[0067] Preferably, such as Figure 2As shown, the LED chip also includes a first ohmic contact layer 9; the first ohmic contact layer 9 covers a portion of the surface of the third semiconductor layer 44 facing away from the substrate 1, thereby enabling current extension; the first extension electrode 6 extends from the exposed surface of the first electrode layer 3 to the surface of the first ohmic contact layer 9 facing away from the substrate 1. The first ohmic contact layer 9 includes, but is not limited to, one or more of indium tin oxide, zinc tin oxide, indium zinc tin oxide, indium aluminum tin oxide, indium gallium tin oxide, aluminum zinc oxide, antimony tin oxide, and gallium zinc oxide. Figure 6 This is a top view of the first ohmic contact layer 9, which has an opening at the location where the first groove 45 is formed. For example... Figure 2 As shown, the first insulating layer 5 also covers a portion of the surface of the first ohmic contact layer 9. Specifically, after the first insulating layer 5 is fabricated, a portion of the surface of the first ohmic contact layer 9 around the opening of each first groove 45 is exposed for electrical connection of each first extended electrode 6. The second insulating layer 7 covers the exposed surface of the first ohmic contact layer 9 that is not covered by the first extended electrode 6.

[0068] Preferably, such as Figure 2 As shown, the LED chip also includes a second ohmic contact layer 10; the second ohmic contact layer 10 covers a portion of the exposed surface of the second semiconductor layer 43 facing away from the substrate 1; the second extended electrode 8 is electrically connected to the second ohmic contact layer 10 through a connection hole 51. The second ohmic contact layer 10 includes, but is not limited to, one or more of nickel, titanium, gold, silver, magnesium, rhodium, aluminum, and platinum. Specifically, the first insulating layer 5 encloses the second ohmic contact layer 10, and only a portion of the second ohmic contact layer 10 is exposed through the connection hole 51 for electrical connection with the second extended electrode 8.

[0069] To facilitate understanding, taking an example where n equals 3, the first type of doping is P-type doping, and the second type of doping is N-type doping, the manufacturing process of an LED chip will be described in detail:

[0070] S01: Provide a growth substrate, including but not limited to a sapphire substrate.

[0071] S02: A laser lift-off layer is grown on one side surface of the growth substrate. Optionally, the laser lift-off layer is an unintentionally doped semiconductor layer, such as U-GaN.

[0072] S03: An epitaxial stack 4 and a first electrode layer 3 are sequentially grown on the laser lift-off layer. Specifically, growing the epitaxial stack 4 includes sequentially growing a third semiconductor layer 44, an active layer 42, a second semiconductor layer 43, an active layer 42, and a first semiconductor layer 41. The first electrode layer 3 is grown on the first semiconductor layer 41.

[0073] S04: A substrate 1 is provided, and a metal bonding layer 2 is formed on one side surface of the substrate 1. The metal bonding layer 2 is bonded to the first electrode layer 3, and the sapphire substrate is removed. Then, the laser lift-off layer is removed to expose the third semiconductor layer 44. Specifically, the sapphire substrate can be removed by laser lift-off.

[0074] S05: A first ohmic contact layer 9 is formed on the surface of the third semiconductor layer 44 facing away from the substrate 1 to achieve current spreading of the third semiconductor layer 44. The first ohmic contact layer 9 covers a portion of the surface of the third semiconductor layer 44 facing away from the substrate 1. Figure 6 A top view of the first ohmic contact layer 9 is shown, in which an opening is provided at the location where the first groove 45 is set.

[0075] S06: Perform a first stage of etching on the first trench 45. The first stage of etching penetrates at least through the third semiconductor layer 44 and the active layer 42 between the third semiconductor layer 44 and the second semiconductor layer 43 to expose a portion of the surface of the second semiconductor layer 43. This application describes an example where the first stage of etching also partially etches the second semiconductor layer 43. Perform a second stage of etching on the first trench 45. The second stage of etching penetrates at least through the second semiconductor layer 43, the active layer 42 between the second semiconductor layer 43 and the first semiconductor layer 41, and the first semiconductor layer 41 to expose a portion of the surface of the first electrode layer 3.

[0076] S07: The second ohmic contact layer 10 is fabricated using photolithography and stripping methods, covering a portion of the exposed surface of the second semiconductor layer 43 away from the substrate 1. Figure 7 A top view of the second ohmic contact layer 10 is shown, which is distributed in a ring on the exposed surface of the second semiconductor layer 43 within each first trench 45.

[0077] S08: Fabricate the first insulating layer 5. Specifically, the connection hole 51 on the first insulating layer 5 can be opened before the subsequent fabrication of the second extended electrode 8.

[0078] S9: Fabricate the first extended electrode 6.

[0079] S10: Fabricate the second insulating layer 7. Specifically, the opening on the first insulating layer 5 corresponding to the connection hole 51 will be made before the second extended electrode 8 is fabricated.

[0080] S11: Create a connection hole 51 on the first insulating layer 5 and an opening corresponding to the connection hole 51 on the second insulating layer 7 to form a current injection channel for the second extended electrode 8.

[0081] S12: Fabricate the second extended electrode 8. The second extended electrode 8 is integrally formed and electrically connected to the second semiconductor layer 43 through each current injection channel.

[0082] Those skilled in the art should understand that in the disclosure of this utility model, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as a limitation of this utility model.

[0083] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0084] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An LED chip, characterized by, The application relates to a substrate, a first electrode layer bonded to the substrate, the first electrode layer being a reflective electrode, an epitaxial stack on a side surface of the first electrode layer away from the substrate, the epitaxial stack being provided with n layers of semiconductor layers stacked in sequence in a direction away from the substrate, n being a positive integer greater than or equal to 3, and an active layer between two of the semiconductor layers, the semiconductor layers on both sides of each active layer being doped with a first type and a second type respectively, the first layer of semiconductor being doped with the first type, the epitaxial stack being provided with a plurality of first grooves, the first grooves exposing part of the surface of the first electrode layer and the i-th layer of semiconductor away from the substrate, 2 <= i < n, i being a positive integer, a first insulating layer provided at least on the sidewall of each first groove and provided with a connecting hole corresponding to the exposed surface of each semiconductor layer doped with the second type, a first extension electrode stacked on the first insulating layer and electrically connected to each semiconductor layer doped with the first type and the first electrode layer, a second insulating layer covering at least the exposed surface of the first extension electrode, a second extension electrode provided on the first insulating layer and electrically connected to each semiconductor layer doped with the second type through the connecting hole, and the projection of the connecting hole on a first plane parallel to the substrate having no intersection with the projection of the first extension electrode on the first plane. Each active layer emits the same light or at least two active layers emit different light. The first insulating layer also covers part of the surface of the epitaxial stack away from the substrate. The second insulating layer also covers the exposed surface of the first insulating layer and the exposed surface of the epitaxial stack away from the substrate. The number of first extension electrodes corresponds to the number of first grooves, and each first extension electrode is independently provided in each first groove. The second extension electrode is integrally formed and extends to one side of the epitaxial stack away from the substrate. n is 3, the first type of doping is P-type doping, and the second type of doping is N-type doping. Each first groove is formed by two etching processes, a first etching process at least penetrating the third layer of semiconductor, the active layer between the third layer of semiconductor and the second layer of semiconductor, to expose part of the surface of the second layer of semiconductor, and a second etching process at least penetrating the second layer of semiconductor, the active layer between the second layer of semiconductor and the first layer of semiconductor, and the first layer of semiconductor, to expose part of the surface of the first electrode layer. The first ohmic contact layer covers part of the surface of the third layer of semiconductor away from the substrate. The first extension electrode extends from the exposed surface of the first electrode layer to the surface of the first ohmic contact layer away from the substrate. The second ohmic contact layer covers part of the exposed surface of the second layer of semiconductor away from the substrate.

2. An LED chip as claimed in claim 1, wherein, The second extension electrode is electrically connected to the second ohmic contact layer through the connecting hole.

3. The LED chip of claim 1, wherein, The first electrode layer is one or more of nickel, titanium, gold, silver, magnesium, rhodium, aluminum, and platinum. ​ 4. The LED chip of claim 1, wherein, ​ 5. The LED chip of claim 1, wherein, ​ 6. An LED chip as claimed in claim 1, wherein, ​ 7. An LED chip as claimed in claim 6, wherein the first and second layers of semiconductor material are of the same type. ​ ​ 8. An LED chip as claimed in claim 6, wherein, ​ ​ ​ 9. The LED chip of claim 6, wherein, ​ ​ ​ 10. The LED chip of claim 1, wherein, ​

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