POP packaging structure based on three-dimensional stacking of switching substrates and manufacturing method of POP packaging structure

Abstract

The invention provides a POP packaging structure based on adapter substrate three-dimensional stacking and a manufacturing method. The POP packaging structure comprises an upper layer packaging body and a lower layer packaging body. The lower-layer packaging body comprises a substrate, a lower-layer chip, a switching substrate, a plastic packaging body and a metal column. According to the invention, the adapter substrate fixed above the lower layer chip is introduced into the lower layer packaging body, so that the three-dimensional stacking of the lower layer packaging body in the vertical direction is realized. According to the structure, the limitation that a traditional POP packaging structure can only carry out two-dimensional plane integration is broken through, and the vertical space of the lower layer packaging body is effectively utilized. On the basis, the metal columns directly penetrate through the plastic package body to connect the switching substrate and the upper-layer package body, so that a vertical interconnection channel from the upper-layer package body to the lower-layer chip through the metal columns and the switching substrate is formed. According to the design, the signal transmission path between the lower layer chip and the upper layer chip in the upper layer packaging body is fundamentally shortened, and the signal transmission efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more specifically, to a POP packaging structure and manufacturing method based on three-dimensional stacking of adapter substrates. Background Technology

[0002] The content in this section only provides background information related to this invention and may not constitute prior art.

[0003] With the increasing demand for miniaturization, multifunctionality, and high performance in consumer electronics, mobile communications, and other fields, System-in-Package (SIP) technology has become a key technology for improving the integration and performance of electronic products because it can integrate chips and passive components with multiple functions into a single package to achieve complete system functions.

[0004] In the field of 3D integrated packaging, Package on Package (POP) structures have become the mainstream solution for integrating heterogeneous functions such as logic chips and memory chips due to their design flexibility and ease of supply chain management. However, with the continuous improvement of chip performance and the increase in system complexity, the traditional POP architecture faces the following irreconcilable technical contradictions and universal limitations in the pursuit of higher density and better performance: Traditional standard POP (Point-of-Pack) packaging structures face bottlenecks in terms of integration density and signal integrity. Specifically, these structures rely on peripheral solder ball arrays for interconnection between upper and lower layers, resulting in lengthy signal transmission paths between chips located in different packages, introducing significant signal delay and attenuation. Simultaneously, the chip layout within the lower package is constrained by the two-dimensional plane of its supporting substrate, with vertical space not being effectively utilized, thus limiting the reduction of package planar dimensions and the improvement of three-dimensional integration density. Summary of the Invention

[0005] In view of this, the first objective of the present invention is to provide a POP packaging structure based on the three-dimensional stacking of the adapter substrate, so as to overcome the above-mentioned technical problems existing in the conventional POP packaging structure.

[0006] The second objective of this invention is to provide a method for manufacturing the POP packaging structure based on the three-dimensional stacking of the adapter substrate described above.

[0007] The objective of this invention is achieved through the following technical solution: In a first aspect, the present invention provides a POP packaging structure based on a three-dimensional stack of adapter substrates, comprising an upper package and a lower package; the lower package includes: substrate; At least one lower-level chip is mounted on the substrate; An adapter substrate is stacked and fixed to the side of the at least one lower-layer chip away from the substrate; A molding compound that encapsulates the lower-layer chip on the substrate and the adapter substrate; A metal pillar penetrates the plastic encapsulation; the first end of the metal pillar is electrically connected to the adapter substrate, and the second end of the metal pillar is electrically connected to the upper encapsulation.

[0008] Optionally, the adapter substrate is electrically connected to the substrate via leads.

[0009] Optionally, solder balls are pre-embedded at the connection between the adapter substrate and the first end of the metal pillar.

[0010] Optionally, the lower-layer chip is a WLCSP chip, and it is soldered to the substrate via flip-chip bumps.

[0011] Optionally, the number of lower-layer chips is two or more, and the adapter substrate is bridged and stacked on top of all the lower-layer chips.

[0012] Secondly, the present invention provides a method for fabricating a POP packaging structure based on a three-dimensional stack of adapter substrates as described above, comprising the following steps: A substrate is provided, and at least one lower-layer chip is mounted on the substrate; An adapter substrate is stacked and fixed to the side of the at least one lower-layer chip away from the substrate; The substrate is encapsulated to form a plastic package that encapsulates the lower-layer chip and the adapter substrate; Drill holes in the molding compound corresponding to the preset connection positions of the adapter substrate to form through holes that expose the adapter substrate; A metal pillar is formed in the through hole, and the first end of the metal pillar is electrically connected to the adapter substrate. An upper package is mounted on the second end of the metal pillar, and the second end of the metal pillar is electrically connected to the upper package.

[0013] Optionally, after the adapter substrates are stacked and fixed, the adapter substrates are electrically connected to the substrates by wire bonding.

[0014] Optionally, before encapsulating the substrate, the method further includes: pre-planting solder balls at a preset connection position on the adapter substrate; wherein the solder balls are exposed during drilling, and the first end of the metal post is electrically connected to the solder balls.

[0015] Optionally, the lower-layer chip is a WLCSP chip, which is bonded to the substrate via flip-chip bonding.

[0016] Optionally, the number of lower-layer chips is two or more, and the adapter substrate is bridged and stacked on top of all the lower-layer chips.

[0017] The technical solutions of the embodiments of the present invention have at least the following advantages and beneficial effects: This invention achieves three-dimensional stacking of the lower package in the vertical direction by introducing an adapter substrate fixed above the lower chip within the lower package. This structure breaks the limitation of traditional POP packaging structures, which can only perform two-dimensional planar integration, allowing for effective utilization of the vertical space of the lower package. Furthermore, metal pillars directly penetrate the molding compound to connect the adapter substrate and the upper package, forming a vertical interconnect channel from the upper package through the metal pillars and adapter substrate to the lower chip. This design fundamentally shortens the signal transmission path between the lower chip and the upper chip within the upper package, improving signal transmission efficiency and providing a feasible structural basis for achieving high-density three-dimensional system-in-package with smaller planar dimensions. Attached Figure Description

[0018] Figure 1 A schematic diagram of a POP packaging structure based on a three-dimensional stack of an adapter substrate provided for an embodiment of the present invention; Figure 2 A schematic diagram of the lower package structure provided for an embodiment of the present invention; Figure 3 for Figure 2 The diagram shows the structure of the lower encapsulation after the metal pillars have been removed. Figure 4 for Figure 3 The diagram shown is a schematic of the lower encapsulation structure after the molding compound has been removed. Figure 5 for Figure 4 The attempt to explode the local structure.

[0019] Icons: 10-Upper package, 20-Lower package, 21-Substrate, 22-Lower chip, 23-Adapter substrate, 24-Molded package, 25-Metal pillar, 26-Resistor / capacitor, 27-Lead, 28-Solder ball, 29-Through hole. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments. The same reference numerals in the accompanying drawings represent the same components. It should be noted that the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the described embodiments of this invention without creative effort are within the scope of protection of this invention.

[0021] Compared to the embodiments shown in the accompanying drawings, feasible embodiments within the scope of protection of this invention may have fewer components, other components not shown in the drawings, different components, components with different arrangements, or components with different connections, etc. Furthermore, two or more components in the drawings may be implemented in a single component, or a single component shown in the drawings may be implemented as multiple separate components.

[0022] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0023] Example 1 Please refer to Figures 1 to 5 As shown, Embodiment 1 of the present invention provides a POP packaging structure, and more particularly a POP packaging structure based on the three-dimensional stacking of the adapter substrate 23.

[0024] According to Embodiment 1 of the present invention, as Figure 1 As shown, the POP packaging structure includes an upper package 10 and a lower package 20 located below the upper package 10.

[0025] In Embodiment 1 of the present invention, the upper package 10 is a packaged chip, which is used to electrically connect with the lower package 20 to jointly form a POP package structure.

[0026] like Figure 2 , Figure 4 and Figure 5 As shown, the lower package 20 includes a substrate 21, a lower chip 22, an adapter substrate 23, a molding compound 24, and a metal pillar 25.

[0027] At least one lower-layer chip 22 is mounted on the upper surface of the substrate 21. In addition, other devices, such as resistors and capacitors 26, may also be mounted on the upper surface of the substrate 21, depending on actual needs.

[0028] The adapter substrate 23 is stacked and fixed to the side of at least one lower-layer chip 22 away from the substrate 21, i.e., the upper surface of the lower-layer chip 22. A molding compound 24 encapsulates the lower-layer chip 22 and the adapter substrate 23 on the substrate 21. Metal pillars 25 are implanted using TMV (molding material through-hole) technology, allowing the metal pillars 25 to penetrate the upper surface of the molding compound 24. Specifically, using TMV technology, through-holes 29 for the metal pillars 25 to pass through can be formed on the upper surface of the molding compound 24 (see...). Figure 3Thus, the first end (bottom end) of each metal pillar 25 is electrically connected to the adapter substrate 23, and the second end (top end) of each metal pillar 25 is electrically connected to the upper package 10.

[0029] According to Embodiment 1 of the present invention, by introducing a transition substrate 23 fixed above the lower-layer chip 22 within the lower-layer package 20, a three-dimensional stacking of the lower-layer package 20 in the vertical direction is achieved. This structure breaks the limitation of traditional POP packaging structures, which can only perform two-dimensional planar integration, allowing the lower-layer package 20 to make effective use of vertical space. Furthermore, a metal pillar 25 directly penetrates the molding compound 24 to connect the transition substrate 23 and the upper-layer package 10, forming a vertical interconnection channel from the upper-layer package 10 through the metal pillar 25 and the transition substrate 23 to the lower-layer chip 22. This design fundamentally shortens the signal transmission path between the lower-layer chip 22 and the upper-layer chip within the upper-layer package 10, improves signal transmission efficiency, and provides a feasible structural basis for achieving high-density three-dimensional system-in-package with smaller planar dimensions.

[0030] In a preferred embodiment of this example 1, referring to Figure 4 As shown, the adapter substrate 23 is electrically connected to the substrate 21 via leads 27. Connecting the adapter substrate 23 to the substrate 21 below via leads 27 provides a mature, low-cost, and highly flexible interconnection method, and achieves electrical connectivity between the adapter substrate 23 and the lower-layer chip 22. The bonding process of leads 27 can accommodate potential height differences and planar position deviations between the adapter substrate 23 and the substrate 21, ensuring the reliability of the electrical connection. Simultaneously, this connection method integrates the adapter substrate 23 into the internal circuit network of the lower-layer package 20, making it not only a vertical interconnection relay station between upper and lower layers but also potentially undertaking functions such as signal redistribution, further enhancing the flexibility and functionality of system integration.

[0031] In a preferred embodiment of this example 1, reference continues... Figure 4 As shown, solder balls 28 are pre-embedded at the connection between the adapter substrate 23 and the first end of the metal pillar 25. The first end of the metal pillar 25 is electrically connected to the corresponding solder balls 28 on the adapter substrate 23.

[0032] By pre-planting solder balls 28 on the adapter substrate 23, especially at predetermined connection positions, a precise alignment reference and excellent soldering interface are provided for the implantation of metal pillars 25 via TMV technology. Specifically, during the implantation of metal pillars 25 via TMV technology, the pre-planted solder balls 28 are exposed after drilling holes in the upper surface of the molding compound 24, thus allowing the solder balls 28 to serve as reliable metallization pads. Based on this, the metal pillars 25 achieve a robust mechanical connection and low-resistance electrical connection with the adapter substrate 23 through electrical connection with the solder balls 28. This design avoids the difficulties of directly metallizing the surface of the molding compound 24 or the adapter substrate 23, improves process reliability and yield, and ensures the electrical performance stability of the vertical interconnect channel.

[0033] In a preferred embodiment of this example 1, the lower-layer chip 22 is a WLCSP (Wafer-Level Chip Scale Package) chip, and is soldered to the substrate 21 via flip-chip bonding bumps. That is, the WLCSP chip and the substrate 21 are soldered together using a flip-chip bonding process.

[0034] This preferred design has multiple beneficial effects: First, the WLCSP chip itself is ultra-thin and has a small package size, making it very suitable for high-density three-dimensional stacking; second, flip-chip bonding technology can provide an extremely short interconnection distance between the lower-level chip 22 and the substrate 21. On this basis, combined with the three-dimensional stacking of the adapter substrate 23, the chip-level interconnection achieved by flip-chip bonding technology and the package-level interconnection achieved by the metal pillars 25 are efficiently combined, which improves performance and creates conditions for heterogeneous integration (such as the integration of logic chips with passive components on the adapter substrate 23).

[0035] In a preferred embodiment of this example 1, the number of lower-layer chips 22 is two or more. Exemplarily, the accompanying drawings of the present invention show a case where two opposing lower-layer chips 22 are disposed on the upper surface of the substrate 21. When the number of lower-layer chips 22 is two or more, the adapter substrate 23 bridges and stacks on top of all the lower-layer chips 22.

[0036] By placing two or more lower-level chips 22 and bridging and stacking them on top of all the lower-level chips 22 with a single adapter substrate 23, high-density three-dimensional integration of multiple lower-level chips 22 within a single lower-level package 20 is achieved. The adapter substrate 23 acts as an "on-chip bus" or "local interconnect network," efficiently managing signal exchange and power distribution between multiple lower-level chips 22. This layout significantly reduces the area required for multi-chip systems in the plane (XY direction), while shortening the die-to-die interconnect distance through the adapter substrate 23. It is particularly suitable for scenarios requiring tightly coupled processors and caches, or the integration of multiple sensor chips, significantly improving system integration and overall performance.

[0037] Example 2 Based on Example 1, Example 2 of the present invention provides a method for fabricating a POP packaging structure based on the three-dimensional stacking of the adapter substrate 23 as described in Example 1.

[0038] According to Embodiment 2 of the present invention, the manufacturing method may include the following steps: Step S1. Provide a substrate 21 and mount at least one lower layer chip 22 on the upper surface of the substrate 21.

[0039] Preferably, the lower-layer chip 22 is a WLCSP chip and is bonded to the substrate 21 via flip-chip bonding. This design allows the mounting of the lower-layer chip 22 to be completed under low-temperature, high-precision conditions, reducing thermal damage to both the lower-layer chip 22 and the substrate 21. The bump array formed by flip-chip bonding not only provides electrical connectivity but also serves as mechanical support and heat dissipation. This method seamlessly integrates with subsequent steps such as stacking the adapter substrate 23 and molding, together forming a complete advanced packaging process for high-performance chips.

[0040] Step S2. Stack and fix an adapter substrate 23 to at least one lower chip 22 on the side away from the substrate 21.

[0041] In conjunction with the aforementioned Embodiment 1, preferably, after the adapter substrate 23 is stacked and fixed, it is electrically connected to the substrate 21 by bonding with wires 27. After the adapter substrate 23 is stacked and fixed, it is connected to the substrate 21 by bonding with wires 27, placing the electrical interconnection step before the molding process. This allows for visual inspection and repair of the quality of the wire bonding before molding, ensuring the reliability of the interconnection. At the same time, the wires 27 are encapsulated and fixed by the subsequent molding body 24, avoiding the risk of wire breakage due to vibration or stress in subsequent processes or use, thus improving the long-term reliability of the package.

[0042] Furthermore, there are two or more lower-layer chips 22, and the interconnect substrate 23 bridges and stacks on top of all the lower-layer chips 22. In the fabrication method, for the layout of multiple lower-layer chips 22, the interconnect substrate 23 is used to bridge and stack them, achieving simultaneous three-dimensional integration and interconnection of multiple lower-layer chips 22 in a single process flow. This method avoids the complexity and cost of fabricating vertical interconnects separately for each lower-layer chip 22, and unifies and simplifies the interconnect structure through a shared interconnect substrate 23, significantly improving the fabrication efficiency of multi-chip packages, reducing manufacturing costs, and ensuring the consistency of interconnect performance in multi-chip systems.

[0043] Step S3. The substrate 21 is encapsulated to form a plastic encapsulation 24 that encapsulates the lower chip 22 and the adapter substrate 23.

[0044] Step S4. Implant the metal column 25 using TMV technology.

[0045] Specifically, holes are drilled in the molding compound 24 corresponding to the preset connection positions of the adapter substrate 23 to form through holes 29 that expose the adapter substrate 23. Next, metal pillars 25 are formed in each through hole 29, and the first end of the metal pillar 25 is electrically connected to the adapter substrate 23.

[0046] Step S5. Install an upper package 10 onto the second end of the metal pillar 25, and electrically connect the second end of the metal pillar 25 to the upper package 10 to obtain the POP package structure provided in Embodiment 1 of the present invention.

[0047] According to Embodiment 2 of the present invention, a unique process sequence of "first stacking the adapter substrate 23 three-dimensionally, then encapsulating the entire structure, and finally forming vertical interconnects based on TMV technology" is a dedicated and optimized method for manufacturing the innovative POP package structure provided in Embodiment 1. This manufacturing method ensures that the lower-layer chip 22 and the adapter substrate 23 are precisely aligned and fixed before encapsulation, and the encapsulation body 24 provides robust mechanical protection for the entire stacked structure. Subsequent drilling and metal pillar 25 formation steps can accurately locate the preset connection positions on the adapter substrate 23, thereby reliably constructing a vertical electrical channel penetrating the encapsulation body 24. The entire process has a clear logic, high compatibility with traditional packaging processes, and can stably and efficiently mass-produce the high-performance, high-density POP package structure described in Embodiment 1.

[0048] In a preferred embodiment of this second embodiment, before encapsulating the substrate 21, solder balls 28 are pre-planted at predetermined connection positions on the adapter substrate 23. During the subsequent implantation of the metal pillar 25 using TMV technology, the solder balls 28 are exposed during drilling, and the first end of the metal pillar 25 is electrically connected to the solder balls 28.

[0049] As can be seen from the description in Embodiment 1 above, pre-planting solder balls 28 on the adapter substrate 23 before molding is a key preparatory step for forming high-quality vertical interconnects. The pre-planted solder balls 28 act as raised metal markers, making them easily identifiable and exposed during subsequent drilling processes, even with some alignment errors. This significantly reduces the stringent requirements for drilling accuracy and improves process tolerance and yield. Simultaneously, the solder balls 28 provide a readily available, wettable metal surface for the metal pillars 25, simplifying the implantation or formation process of the metal pillars 25 and ensuring the connection quality of the interface.

[0050] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A POP packaging structure based on a three-dimensional stacked adapter substrate, comprising an upper packaging layer and a lower packaging layer; characterized in that, The lower-layer package includes: substrate; At least one lower-level chip is mounted on the substrate; An adapter substrate is stacked and fixed to the side of the at least one lower-layer chip away from the substrate; A molding compound that encapsulates the lower-layer chip on the substrate and the adapter substrate; A metal pillar penetrates the plastic encapsulation; the first end of the metal pillar is electrically connected to the adapter substrate, and the second end of the metal pillar is electrically connected to the upper encapsulation.

2. The POP packaging structure based on three-dimensional stacking of adapter substrates according to claim 1, characterized in that, The adapter substrate is electrically connected to the substrate via leads.

3. The POP packaging structure based on three-dimensional stacking of adapter substrates according to claim 1, characterized in that, Solder balls are pre-embedded at the connection between the adapter substrate and the first end of the metal pillar.

4. The POP packaging structure based on three-dimensional stacking of adapter substrates according to claim 1, characterized in that, The lower-layer chip is a WLCSP chip, which is soldered to the substrate via flip-chip bumps.

5. The POP packaging structure based on three-dimensional stacking of adapter substrates according to claim 1, characterized in that, The number of the lower-layer chips is two or more, and the adapter substrate is bridged and stacked on top of all the lower-layer chips.

6. A method for fabricating a POP packaging structure based on a three-dimensional stack of adapter substrates as described in any one of claims 1 to 5, characterized in that, Includes the following steps: A substrate is provided, and at least one lower-layer chip is mounted on the substrate; An adapter substrate is stacked and fixed to the side of the at least one lower-layer chip away from the substrate; The substrate is encapsulated to form a plastic package that encapsulates the lower-layer chip and the adapter substrate; Drill holes in the molding compound corresponding to the preset connection positions of the adapter substrate to form through holes that expose the adapter substrate; A metal pillar is formed in the through hole, and the first end of the metal pillar is electrically connected to the adapter substrate. An upper package is mounted on the second end of the metal pillar, and the second end of the metal pillar is electrically connected to the upper package.

7. The method for fabricating a POP packaging structure based on a three-dimensional stack of adapter substrates according to claim 6, characterized in that, After the adapter substrates are stacked and fixed, the adapter substrates are electrically connected to the substrates by wire bonding.

8. The method for fabricating a POP packaging structure based on a three-dimensional stack of adapter substrates according to claim 6, characterized in that, Before encapsulating the substrate, the method further includes: pre-planting solder balls at a preset connection position on the adapter substrate; wherein the solder balls are exposed during drilling, and the first end of the metal pillar is electrically connected to the solder balls.

9. The method for fabricating a POP packaging structure based on a three-dimensional stack of adapter substrates according to claim 6, characterized in that, The lower-layer chip is a WLCSP chip, which is bonded to the substrate using a flip-chip bonding process.

10. The method for fabricating a POP packaging structure based on a three-dimensional stack of adapter substrates according to claim 6, characterized in that, The number of the lower-layer chips is two or more, and the adapter substrate is bridged and stacked on top of all the lower-layer chips.

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