Low-harmonic rectification control circuit

Abstract

The utility model belongs to the technical field of electronics, and particularly relates to a low-harmonic rectification control circuit which remarkably counteracts low-order harmonics such as five-order harmonics and seven-order harmonics through multi-phase superposition of a phase-shifting transformer, the total harmonic distortion (THD) is lower than 5%, the environmental protection requirement of high-power industrial equipment for a power grid is met, and a control cable has the advantages of low harmonic pollution, low cost and the like. The DSP main control chip is combined with the digital timer, and the serial-to-parallel circuit only needs one PWM pin and three GPIO pins, so that the DSP resource occupation is reduced; the gating circuit adopts a general multiplexer (74HC4051D), so that the hardware complexity is reduced; the drive circuit realizes strong and weak current isolation through the isolation transformer, prevents high-voltage interference from damaging a control chip, improves the system safety, and reduces the maintenance cost of the circuit.

Description

Technical Field

[0001] This utility model belongs to the field of electronic technology, specifically relating to a low harmonic rectification control circuit. Background Technology

[0002] Traditional 6-pulse thyristor rectifier circuits generate significant harmonic currents in high-power applications, polluting the power grid and affecting power quality. While 12-pulse rectifier circuits can reduce some harmonics, they still cannot meet the stringent harmonic suppression requirements for high-power industrial UPS systems above 300kVA. 18-pulse rectification technology, through the coordinated control of phase-shifting transformers and multiple sets of thyristors, can significantly reduce harmonic content. However, existing 18-pulse rectification control schemes suffer from problems such as complex triggering timing, high hardware costs, and weak anti-interference capabilities. Utility Model Content

[0003] The purpose of this invention is to provide a low-harmonic rectification control circuit to solve the problems mentioned in the background art.

[0004] To achieve the above-mentioned technical objectives, the technical solution adopted by this utility model is as follows:

[0005] A low harmonic rectification control circuit includes a phase-shifting transformer for receiving three-phase mains power and generating three sets of output voltages with a phase difference of 20 degrees.

[0006] The 18-pulse thyristor rectifier circuit consists of 18 thyristors, divided into 9 upper arm thyristors and 9 lower arm thyristors. The cathodes of the upper arm thyristors are connected together to form a DC positive output, and the anodes of the lower arm thyristors are connected together to form a DC negative output.

[0007] The DSP main control chip outputs a trigger signal through the PWM pin and distributes the trigger signal to the thyristors through a serial-to-parallel conversion circuit.

[0008] A serial-to-parallel converter, including a Schmitt inverter and a shift register, is used to convert serial data output by the DSP into parallel gating signals.

[0009] The gating circuit, composed of a multiplexer, is used to distribute the PWM signal to a specified thyristor according to the parallel gating signal.

[0010] The drive circuit, which includes a Darlington transistor and an isolation transformer, is used to convert weak electrical control signals into strong electrical drive signals to trigger the thyristors.

[0011] The phase-shifting transformer outputs three sets of voltage phases of +20°, 0° and -20°, respectively, and each set of voltage is connected to the midpoint of the three sets of thyristor bridge arms.

[0012] The serial-to-parallel conversion circuit includes a 74HC14D Schmitt inverter and a 74HC595D shift register, which receive serial data, serial clock and latch pulse signals output by the DSP, and output parallel strobe signals through the QA to QH pins of the shift register.

[0013] The selection circuit uses a 74HC4051D multiplexer, whose address pin and enable pin are connected to parallel selection signals, and distributes the PWM signal to the drive terminals of 18 thyristors through address encoding logic.

[0014] The driving circuit includes a ULN2003A Darlington transistor array, whose input terminal receives a gating signal and whose output terminal is connected to the gate of a thyristor via an isolation transformer, amplifying the 3.3V weak current signal into a 12V / 500mA driving signal.

[0015] The DSP main control chip has a built-in timer module that calculates the trigger timing based on the mains commutation point and control angle. It then triggers different thyristor combinations sequentially through a gating circuit, completing 18 control cycles per mains cycle.

[0016] The low-harmonic rectification control circuit structure significantly cancels low-order harmonics such as the 5th and 7th harmonics through multi-phase superposition of phase-shifting transformers, achieving a total harmonic distortion (THD) of less than 5%, meeting the environmental protection requirements of high-power industrial equipment for the power grid, and resulting in low harmonic pollution in the control cable. The DSP main control chip, combined with a digital timer, achieves μs-level trigger timing control, dynamically adjusting the control angle to respond to load fluctuations and ensuring stable DC voltage output (error <1%), thus giving the control circuit high control accuracy. The serial-to-parallel conversion circuit requires only one PWM pin and three GPIO pins, reducing DSP resource consumption. The gating circuit uses a general-purpose multiplexer (74HC4051). D) Reduces hardware complexity; the drive circuit achieves strong and weak current isolation through an isolation transformer, avoiding high-voltage interference from damaging the control chip and improving system safety; compared with traditional analog control schemes, digital control circuits (DSP + general logic chip) are lower in cost and easier to upgrade and maintain, thereby reducing circuit maintenance costs; expandable to high-power UPS systems above 300kVA, supporting long-term continuous operation in industrial applications, suitable for scenarios with stringent power quality requirements such as data centers and medical equipment; the thyristor only turns off when the current crosses zero after triggering, reducing switching losses; multi-pulse rectification improves energy conversion efficiency (>95%), making the circuit highly efficient and reducing operating costs. Attached Figure Description

[0017] This utility model can be further illustrated by the non-limiting embodiments given in the accompanying drawings.

[0018] Figure 1 This is a system block diagram of the circuit of this utility model.

[0019] Figure 2 This is a detailed circuit diagram of the present invention.

[0020] Figure 3 This is a circuit diagram for serial-to-parallel conversion in this utility model.

[0021] Figure 4 This is the timing diagram of the serial-to-parallel conversion circuit in this utility model.

[0022] Figure 5 This is a detailed circuit diagram of the selection circuit in this utility model.

[0023] Figure 6 This is the truth table for the gating circuit in this utility model.

[0024] Figure 7 This is a detailed circuit diagram of the driving circuit in this utility model.

[0025] Figure 8 This is a specific control timing diagram of this utility model. Detailed Implementation

[0026] To enable those skilled in the art to better understand this utility model, the technical solution of this utility model will be further described below in conjunction with the accompanying drawings and embodiments.

[0027] like Figure 1-8 As shown, the phase-shifting transformer and rectifier circuit are configured as follows:

[0028] The three-phase AC mains input (A, B, C) is connected to a phase-shifting transformer, which generates three sets of output voltages:

[0029] Group 1: Phase shift +20° (A1, B1, C1);

[0030] Group 2: Phase offset 0° (A2, B2, C2);

[0031] Group 3: Phase offset -20° (A3, B3, C3).

[0032] The three voltages are connected to the midpoint of a 9-arm rectifier circuit consisting of 18 thyristors. The cathodes of the nine upper arm thyristors (T1-T9) are connected to the DC positive terminal, and the anodes of the nine lower arm thyristors (B1-B9) are connected to the DC negative terminal. A filter electrolytic capacitor is connected in parallel between the positive and negative terminals to smooth the DC output.

[0033] DSP Main Control Chip and Signal Generation: Since thyristor triggering requires precise control timing, the ordinary GPIO pins of the DSP main control chip may be affected by interrupts, making precise timing difficult. Therefore, it is necessary to utilize the DSP's PWM pins for precise timing. However, DSPs typically do not have 18 PWM pins. Therefore, this solution uses one PWM pin to output the trigger signal and three GPIO pins to output the data signal. A serial-to-parallel conversion circuit and a gating circuit are used to distribute the trigger signal to the 18 thyristors. The DSP outputs three signals: serial data, serial clock, and latch pulse. The serial data consists of a series of bytes, each byte being eight bits. The serial clock is used to divide each bit. The latch pulse is used to divide each byte. The three signals—serial data, serial clock, and latch pulse—are first filtered for interference by a 74HC14D Schmitt trigger inverter, and then sent to a 74HC595D shift register. The 74HC595D's QA to QH outputs eight bits per byte, thus completing the serial-to-parallel output.

[0034] At time t0, the DSP's serial data pin outputs bit 1. At time t1, the DSP's serial clock generates a rising edge, causing bit 1 to be stored in the 74HC595D. At time t2, the DSP's serial data pin outputs bit 2. This process is repeated from time t3 to t16, until all eight bits are stored in the 74HC595D, completing one byte transfer. At time t17, the DSP's latch pulse pin generates a rising edge, causing the eight bits of data stored in the 74HC595D to be output to pins QA to QH, updating the state of the gating circuit and connecting the DSP's PWM pin to the corresponding thyristor driver circuit. At time t18, the latch pulse goes low. At time t19, the PWM pin outputs a pulse signal of a specific duration to the driver circuit to trigger the thyristor. At time t20, the PWM goes low, completing one control cycle. The next control cycle begins at time t20; one mains power cycle contains 18 control cycles.

[0035] The DSP main control chip outputs trigger pulse signals through its PWM pin and serial control signals through three GPIO pins (data, clock, latch).

[0036] The DSP has a built-in timer module that monitors the mains commutation point (such as the zero-crossing point of the line voltage C1B1) in real time and dynamically adjusts the control angle based on the deviation between the current DC voltage and the target value to generate the trigger timing.

[0037] The serial-to-parallel conversion circuit outputs QA, QB, QC, and QD, which are the selection signals for the lower arm thyristors B1 to B9. The A0, A1, and A2 address pins and the EN enable pin of the lower arm thyristor's low-order 74HC4051D selector are connected to the QA, QB, QC, and QD selection signals, respectively. For the higher-order 74HC4051D selector of the lower arm thyristors, A0 is connected to QA, A1 and A2 are grounded, and QD is connected to the EN enable pin after passing through a 74HC14D Schmitt trigger inverter. Similarly, the serial-to-parallel conversion circuit outputs QE, QF, QG, and QH, which are the selection signals for the upper arm thyristors T1 to T9. The A0, A1, and A2 address pins and the EN enable pin of the upper arm thyristor's low-order 74HC4051D selector are connected to the QE, QF, QG, and QH selection signals, respectively. In the upper arm thyristor, the A0 of the high-order 74HC4051D selector is connected to QE, A1 and A2 are grounded, and QH is connected to the EN enable pin after passing through a 74HC14D Schmitt inverter. The PWM signal output by the DSP is connected to the common COM terminal of all four 74HC4051Ds. The PWM signal is distributed to the 18 thyristors by the DSP according to a specific timing sequence after passing through the above-mentioned gating circuit. When the gating signal QAQBQCQD = 0001 of the lower arm thyristor, the DSP's PWM signal is turned on at B1.

[0038] When QAQBQCQD=0010, the DSP's PWM signal is turned on at B2.

[0039] When QAQBQCQD=0011, the DSP's PWM signal is turned on at B3.

[0040] When QAQBQCQD=0100, the DSP's PWM signal is turned on at B4.

[0041] When QAQBQCQD=0101, the DSP's PWM signal is turned on at B5.

[0042] When QAQBQCQD=0110, the DSP's PWM signal is turned on at B6.

[0043] When QAQBQCQD=0111, the DSP's PWM signal is turned on at B7.

[0044] When QAQBQCQD = 1000, the DSP's PWM signal is turned on at B8.

[0045] When QAQBQCQD = 1001, the DSP's PWM signal is turned on at B9. 0 represents 0V low level, and 1 represents 3.3V high level. The gating logic for the upper arm is the same as that for the lower arm.

[0046] The DSP's serial data, clock, and latch signals are filtered by a 74HC14D Schmitt inverter and then input to a 74HC595D shift register.

[0047] The shift register receives serial data bit by bit on the rising edge of the clock. On the rising edge of the latch signal, it outputs 8 bits of data in parallel to the QA-QH pins to form the selection signals for the upper and lower arm thyristors (QA-QD controls the lower arm B1-B9, and QE-QH controls the upper arm T1-T9).

[0048] The gating circuit assigns trigger signals:

[0049] The selection circuit uses four 74HC4051D multiplexers (two on each of the upper and lower arms), with their address pins (A0-A2) and enable pin (EN) connected to the parallel output signals of the shift register.

[0050] By using address encoding logic (such as selecting B2 when QA-QD=0010), the DSP's PWM signal is distributed to the drive terminal of the target thyristor, ensuring that the 18 thyristors are triggered sequentially in each mains power cycle.

[0051] Drive Circuit and Isolation Design: Since the nine upper arm thyristor control signals T1 to T9 and the nine lower arm thyristor control signals B1 to B9 output by the selection circuit are weak 3.3V signals, they cannot directly drive the thyristors. The voltage and current need to be increased through the drive circuit, and then the weak and strong currents need to be isolated through an isolation transformer before the thyristors can be driven. The above 18 weak 3.3V control signals are connected to the bases B2 to B7 of three ULN2003A Darlington transistors. Each ULN2003A has seven Darlington transistors, with the first one unused. The common emitter E of the three ULN2003A transistors is grounded, and the common terminal COM of the three ULN2003A transistors is connected to a 12V power supply. The 18 signals are amplified to 12V 500mA driving capability by Darlington tubes and then output from the collectors C2 to C7 of the three ULN2003A transistors. They are then connected to 18 isolation transformers through CN1, CN2, and CN3 interfaces to drive 18 thyristors.

[0052] The commutation point of line voltage C1B1 from negative to positive is set as time t0. At this time, the DSP calculates the control angle based on the mains voltage, the current DC voltage, and the target DC voltage, and the DSP's timer starts counting from zero. At time t1, the timer counts to the duration corresponding to the control angle, then the timer is reset and restarted. The DSP control gating circuit connects the PWM pin to the thyristor drive circuits of the upper arm T1 and lower arm B2, and simultaneously outputs a trigger pulse from the DSP's PWM pin, turning on the thyristors of the upper arm T1 and lower arm B2 until the current in the thyristors of the upper arm T1 and lower arm B2 reaches zero and they automatically turn off. At time t2, the timer counts to the duration corresponding to 20 degrees, then the timer is reset and restarted. The DSP control gating circuit connects the PWM pin to the thyristor drive circuits of the upper arm T4 and lower arm B5, and simultaneously outputs a trigger pulse from the PWM pin, turning on the thyristors of the upper arm T4 and lower arm B5 until the current in the thyristors of the upper arm T4 and lower arm B5 reaches zero and they automatically turn off. From time t3 to t18, the thyristors of the upper arm T7 and lower arm B8, upper arm T1 and lower arm B3, upper arm T4 and lower arm B6, upper arm T7 and lower arm B9, upper arm T2 and lower arm B3, upper arm T5 and lower arm B6, upper arm T8 and lower arm B9, upper arm T2 and lower arm B1, upper arm T5 and lower arm B4, upper arm T8 and lower arm B7, upper arm T3 and lower arm B1, upper arm T6 and lower arm B4, upper arm T9 and lower arm B7, upper arm T3 and lower arm B2, upper arm T6 and lower arm B5, and upper arm T9 and lower arm B8 are triggered respectively. The control method is the same as at time t2, and will not be repeated. The operation at time t0 restarts when the line voltage C1B1 returns to the commutation point from negative to positive, thus achieving a stable DC voltage output.

[0053] The selected 3.3V weak current signal is connected to the ULN2003A Darlington transistor array, and the signal is amplified to 12V / 500mA through the internal Darlington pair, and the driving capability meets the gate requirements of the thyristor.

[0054] The amplified signal is transmitted to the thyristor gate through an isolation transformer (CN1-CN3 interface) to achieve strong and weak current isolation and avoid interference and high voltage breakdown risks.

[0055] Control timing and loops:

[0056] Each mains power cycle is divided into 18 control stages (corresponding to 18 pulses). The DSP triggers different thyristor combinations in sequence according to the commutation point (e.g., triggering T1 and B2 at time t1, triggering T4 and B5 at time t2, etc.).

[0057] The trigger pulse width is dynamically adjusted by the control angle to ensure that the thyristor automatically turns off when the current crosses zero, reducing switching losses and harmonics.

[0058] Technological advantages and benefits

[0059] The low-harmonic rectification control circuit significantly cancels out the 5th and 7th harmonics through multi-phase superposition of the phase-shifting transformer, achieving a total harmonic distortion (THD) of less than 5%, meeting the environmental protection requirements of high-power industrial equipment for the power grid and resulting in low harmonic pollution in the control cable. The DSP main control chip, combined with a digital timer, achieves μs-level trigger timing control, dynamically adjusting the control angle to respond to load fluctuations and ensuring stable DC voltage output (error <1%), thus giving the control circuit high control accuracy. The serial-to-parallel conversion circuit requires only one PWM pin and three GPIO pins, reducing DSP resource consumption. The gating circuit uses a general-purpose multiplexer (74HC4051D). This reduces hardware complexity; the drive circuit achieves strong and weak current isolation through an isolation transformer, avoiding high-voltage interference from damaging the control chip and improving system safety; compared with traditional analog control schemes, digital control circuits (DSP + general-purpose logic chip) are lower in cost and easier to upgrade and maintain, thereby reducing circuit maintenance costs; it can be expanded to high-power UPS systems of 300kVA and above, supporting long-term continuous operation in industrial applications, suitable for scenarios with stringent power quality requirements such as data centers and medical equipment; the thyristor only turns off when the current crosses zero after triggering, reducing switching losses; multi-pulse rectification improves energy conversion efficiency (>95%), making the circuit highly efficient and reducing operating costs.

[0060] The above embodiments are merely illustrative of the principles and effects of this utility model and are not intended to limit this utility model. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this utility model. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this utility model should still be covered by the claims of this utility model.

Claims

1. A low-harmonic rectification control circuit, characterized in that: This includes a phase-shifting transformer, used to receive three-phase mains power and generate three sets of output voltages with a phase difference of 20 degrees; The 18-pulse thyristor rectifier circuit consists of 18 thyristors, divided into 9 upper arm thyristors and 9 lower arm thyristors. The cathodes of the upper arm thyristors are connected together to form a DC positive output, and the anodes of the lower arm thyristors are connected together to form a DC negative output. The DSP main control chip outputs a trigger signal through the PWM pin and distributes the trigger signal to the thyristors through a serial-to-parallel conversion circuit. A serial-to-parallel converter, including a Schmitt inverter and a shift register, is used to convert serial data output by the DSP into parallel gating signals. The gating circuit, composed of a multiplexer, is used to distribute the PWM signal to a specified thyristor according to the parallel gating signal. The drive circuit, which includes a Darlington transistor and an isolation transformer, is used to convert weak electrical control signals into strong electrical drive signals to trigger the thyristors.

2. The low harmonic rectification control circuit according to claim 1, characterized in that: The phase-shifting transformer outputs three sets of voltage phases of +20°, 0° and -20°, respectively, and each set of voltage is connected to the midpoint of the three sets of thyristor bridge arms.

3. The low harmonic rectification control circuit according to claim 2, characterized in that: The serial-to-parallel conversion circuit includes a 74HC14D Schmitt inverter and a 74HC595D shift register, which receive serial data, serial clock and latch pulse signals output by the DSP, and output parallel strobe signals through the QA to QH pins of the shift register.

4. The low harmonic rectification control circuit according to claim 3, characterized in that: The selection circuit uses a 74HC4051D multiplexer, whose address pin and enable pin are connected to parallel selection signals, and distributes the PWM signal to the drive terminals of 18 thyristors through address encoding logic.

5. The low harmonic rectification control circuit according to claim 4, characterized in that: The driving circuit includes a ULN2003A Darlington transistor array, whose input terminal receives a gating signal and whose output terminal is connected to the gate of a thyristor via an isolation transformer, amplifying the 3.3V weak current signal into a 12V / 500mA driving signal.

6. The low harmonic rectification control circuit according to claim 5, characterized in that: The DSP main control chip has a built-in timer module that calculates the trigger timing based on the mains commutation point and control angle. It then triggers different thyristor combinations sequentially through a gating circuit, completing 18 control cycles per mains cycle.

Images