Pulse generation circuit, driving chip and electronic equipment

Abstract

The utility model discloses a pulse generation circuit, a driving chip and electronic equipment, and belongs to the technical field of electronic equipment. The pulse generation circuit comprises a square wave input end, a first pulse unit and a second pulse unit. The first pulse unit comprises a first delay module and a first logic processing module; the first delay module is used for performing delay processing on the falling edge of the square wave signal to generate a first delay signal; the first logic processing module is used for outputting a first pulse signal according to the first delay signal; the second pulse unit comprises a second delay module and a second logic processing module; the second delay module is used for performing delay processing on the rising edge of the square wave signal to generate a second delay signal; the second logic processing module is used for outputting a second pulse signal according to the second delay signal. The pulse width of the first pulse signal and the pulse width of the second pulse signal are narrower than the pulse width of the square wave signal, and conversion from the square wave signal to the pulse signal with the narrower pulse width is achieved.

Description

Technical Field

[0001] This application belongs to the field of electronic equipment technology, specifically relating to a pulse generation circuit, a driver chip, and an electronic device. Background Technology

[0002] With the widespread application of Insulated Gate Bipolar Transistors (IGBTs) in various industries, their corresponding driver chips, also known as integrated circuits (ICs), have also received widespread attention.

[0003] In this process, the driver IC needs to convert a lower-voltage square wave signal into a higher-voltage square wave signal to generate the drive current for the IGBT. However, current driver ICs typically use level-shifting circuits to directly convert the lower-voltage square wave signal into a higher-voltage square wave signal. This results in the driver IC operating under high current for an extended period, leading to higher device losses and reduced reliability. Clearly, reducing the pulse width during the level-shifting process would reduce device losses and improve the reliability of the driver IC. Therefore, there is an urgent need for a circuit that can convert a square wave signal into a narrower pulse signal to achieve the square wave signal conversion. Summary of the Invention

[0004] The pulse generation circuit, driver chip, and electronic device provided in this application embodiment can realize the conversion from square wave signal to pulse signal with narrow pulse width.

[0005] In a first aspect, a pulse generation circuit is provided, the pulse generation circuit comprising: a square wave input terminal, a first pulse unit and a second pulse unit, wherein the square wave input terminal is used to receive a square wave signal;

[0006] The first pulse unit includes a first delay module and a first logic processing module, wherein the first delay module is connected to the square wave input terminal and the first logic processing module;

[0007] The first delay module is used to delay the falling edge of the square wave signal, generate and transmit a first delayed signal to the first logic processing module;

[0008] The first logic processing module is used to output a first pulse signal according to the first delay signal, wherein the duration of the high level of the first pulse signal is the duration of the falling edge of the first delay signal;

[0009] The second pulse unit includes a second delay module and a second logic processing module, wherein the second delay module is connected to the square wave input terminal and the second logic processing module;

[0010] The second delay module is used to delay the rising edge of the square wave signal, generate and transmit a second delayed signal to the second logic processing module;

[0011] The second logic processing module is used to output a second pulse signal according to the second delay signal, wherein the high level duration of the second pulse signal is the rising edge duration of the first delay signal.

[0012] Optionally, the first delay module includes: a first inverter and a first capacitor; the first inverter is connected to the square wave input terminal, the first terminal of the first capacitor and the first logic processing module, and the second terminal of the first capacitor is grounded;

[0013] The first inverter and the first capacitor are used to perform delay processing on the rising and falling edges of the square wave signal, generate and transmit the first delayed signal to the first logic processing module.

[0014] Optionally, the first logic processing module is configured to output a high-level signal during the rising edge duration of the first delay signal and output a low-level signal during the remaining time period of the first delay signal to obtain the first pulse signal, wherein the remaining time period is the time period of the first delay signal excluding the rising edge duration.

[0015] Optionally, the first logic processing module includes: a second inverter, a third inverter, and a first AND gate; the second inverter is connected to the square wave input terminal and the first AND gate, and the third inverter is connected to the first inverter and the first AND gate.

[0016] Optionally, the second delay module is used to delay the falling edge of the inverted signal of the square wave signal to generate and transmit a second delayed signal to the second logic processing module.

[0017] Optionally, the second delay module includes: a fourth inverter, a fifth inverter, and a second capacitor; the fourth inverter is connected to the square wave input terminal and the fifth inverter, the fifth inverter is also connected to the first terminal of the second capacitor and the second logic processing module, and the second terminal of the second capacitor is grounded;

[0018] The fifth inverter and the second capacitor are used to perform delay processing on the rising and falling edges of the inverted signal, generate and transmit a second delayed signal to the second logic processing module.

[0019] Optionally, the first logic processing module includes a second inverter, a third inverter, and a first AND gate; the second inverter is connected to the square wave input terminal and the first AND gate, and the third inverter is connected to the first inverter and the first AND gate; the second delay module includes a sixth inverter and a third capacitor; the sixth inverter is connected to the second inverter, the first terminal of the third capacitor, and the second logic processing module, and the second terminal of the third capacitor is grounded;

[0020] The sixth inverter and the third capacitor are used to delay the rising and falling edges of the inverted signal, generate a second delayed signal, and transmit it to the second logic processing module.

[0021] Optionally, the second logic processing module is configured to output a high-level signal during the rising edge duration of the second delay signal and output a low-level signal during the remaining time period of the second delay signal to obtain the second pulse signal, wherein the remaining time period of the second delay signal is the time period of the second delay signal excluding the rising edge duration.

[0022] Optionally, the second logic processing module includes: an eighth inverter, a seventh inverter, and a second AND gate; the eighth inverter is connected to the second AND gate and is used to receive the inverted signal of the square wave signal, and the seventh inverter is connected to the second delay module and the second AND gate.

[0023] Optionally, the second delay module includes a fourth inverter, a fifth inverter, and a second capacitor, and the eighth inverter is connected to the fourth inverter;

[0024] Alternatively, the second delay module includes a sixth inverter and a third capacitor, the first logic processing module includes a second inverter, a third inverter and a first AND gate, and the eighth inverter is connected to the second inverter.

[0025] In a second aspect, a driving chip is provided, the driving chip including any of the pulse generation circuits described in the first aspect.

[0026] Thirdly, an electronic device is provided, the electronic device comprising any of the pulse generating circuits described in the first aspect, or the electronic device comprising the driving chip described in the second aspect.

[0027] The pulse generation circuit, driver chip, and electronic device provided in this application embodiment include a first delay module in the first pulse unit of the pulse generation circuit that can delay the falling edge of a square wave signal to generate and transmit a first delay signal to a first logic processing module, so that the first logic processing module can output a first pulse signal according to the first delay signal. The high-level duration of the first pulse signal is the same as the falling edge duration of the first delay signal. Similarly, a second delay module in the second pulse unit can delay the rising edge of a square wave signal to generate and transmit a second delay signal to a second logic processing module, so that the second logic processing module can output a second pulse signal according to the second delay signal. The high-level duration of the second pulse signal is the same as the rising edge duration of the first delay signal. In this technical solution, the pulse generation circuit can delay the rising and falling edges of the input square wave signal to output a first pulse signal with a high level duration equal to the falling edge duration, and a second pulse signal with a high level duration equal to the rising edge duration. The pulse widths of the first and second pulse signals are narrower than the pulse width of the square wave signal, thus realizing the conversion from the square wave signal to a pulse signal with a narrower pulse width. Attached Figure Description

[0028] Figure 1 This is one of the schematic diagrams of the pulse generation circuit provided in the embodiments of this application;

[0029] Figure 2 This is a second schematic diagram of the pulse generation circuit provided in the embodiments of this application;

[0030] Figure 3 This is one of the timing diagrams of the pulse generation circuit provided in the embodiments of this application;

[0031] Figure 4 This is the third schematic diagram of the pulse generation circuit provided in the embodiments of this application;

[0032] Figure 5 This is the second timing diagram of the pulse generation circuit provided in the embodiments of this application;

[0033] Figure 6 This is the fourth schematic diagram of the pulse generation circuit provided in the embodiments of this application;

[0034] Figure 7 This is the third timing diagram of the pulse generation circuit provided in the embodiments of this application;

[0035] Figure 8 This is the fifth schematic diagram of the pulse generation circuit provided in the embodiments of this application;

[0036] Figure 9 This is the fourth timing diagram of the pulse generation circuit provided in the embodiments of this application;

[0037] Figure 10 This is the sixth schematic diagram of the pulse generation circuit provided in the embodiments of this application;

[0038] Figure 11 This is the fifth timing diagram of the pulse generation circuit provided in the embodiments of this application;

[0039] Figure 12 This is the seventh schematic diagram of the pulse generation circuit provided in the embodiments of this application;

[0040] Figure 13 This is the sixth timing diagram of the pulse generation circuit provided in the embodiments of this application;

[0041] Figure 14 This is the seventh timing diagram of the pulse generation circuit provided in the embodiments of this application;

[0042] Figure 15 This is one of the structural schematic diagrams of the driver chip provided in the embodiments of this application;

[0043] Figure 16 This is one of the schematic diagrams of the operating principle of the driver chip provided in the embodiments of this application. Detailed Implementation

[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0045] With the widespread application of IGBTs in various industries, their corresponding driver ICs have also received widespread attention. The driver IC can receive a 3.3V pulse-width modulation (PWM) square wave drive signal from external signal generation units such as microcontroller units (MCUs) and controllers. It then converts the 3.3V square wave drive signal to a 15V square wave drive signal via a level conversion circuit, and further converts the 15V square wave drive signal to a 615V square wave drive signal via another level conversion circuit, which is used to generate the IGBT drive current.

[0046] However, current driver ICs typically use level-shifting circuits to directly convert lower-voltage square wave signals to higher-voltage square wave signals. This results in the driver IC operating under high current for extended periods, leading to higher device losses and reduced reliability. Clearly, reducing the pulse width during level shifting would decrease device losses and improve driver IC reliability. Therefore, there is an urgent need for a circuit that can convert square wave signals into narrower pulse signals to achieve this conversion.

[0047] Please refer to Figure 1 The diagram illustrates a pulse generation circuit according to an embodiment of this application. This pulse generation circuit converts a square wave signal into a pulse signal with a narrow pulse width. Figure 1 As shown, the pulse generation circuit 1 includes: a square wave input terminal IN, a first pulse unit 11, and a second pulse unit 12. The square wave input terminal IN is used to receive square wave signals.

[0048] The first pulse unit 11 includes a first delay module 111 and a first logic processing module 112. The first delay module 111 is connected to the square wave input terminal IN and the first logic processing module 112. The first delay module 111 is used to delay the falling edge of the square wave signal to generate and transmit a first delayed signal to the first logic processing module 112. The first logic processing module 112 is used to output a first pulse signal Out1 according to the first delayed signal. The high level duration of the first pulse signal Out1 is the same as the falling edge duration of the first delayed signal.

[0049] The second pulse unit 12 includes a second delay module 121 and a second logic processing module 122. The second delay module 121 is connected to the square wave input terminal IN and the second logic processing module 122. The second delay module 121 is used to delay the rising edge of the square wave signal to generate and transmit a second delayed signal to the second logic processing module 122. The second logic processing module 122 is used to output a second pulse signal Out2 according to the second delayed signal. The high-level duration of the second pulse signal Out2 is the same as the rising edge duration of the first delayed signal.

[0050] In this embodiment, both the first delay module 111 and the second delay module 121 can receive the square wave signal output from the square wave input terminal IN. The first delay module 111 can delay the falling edge of the received square wave signal to slow down the change time of the square wave signal from high level to low level, and output the first pulse signal obtained by the delay processing to the first logic processing module 112. The first logic processing module 112 can output the first pulse signal according to the received first delayed signal. The high level duration of the first pulse signal is the duration of the falling edge of the first delayed signal, and the pulse width of the first pulse signal is narrower than the pulse width of the square wave signal received by the pulse generation circuit 1. The first pulse signal can be called a narrow pulse width signal.

[0051] Similarly, the second delay module 121 can delay the rising edge of the received square wave signal to slow down the transition time from low to high level, and output the delayed second pulse signal to the second logic processing module 122. The second logic processing module 122 can output the second pulse signal based on the received second delayed signal. The high-level duration of the second pulse signal is the same as the rising edge duration of the second delayed signal, and the pulse width of the second pulse signal is narrower than the pulse width of the square wave signal received by the pulse generation circuit 1. It is easy to understand that the smaller the delay of the falling edge of the square wave signal by the first delay module 111, the narrower the pulse width of the first pulse signal output by the first logic processing module 112. The smaller the delay of the rising edge of the square wave signal by the second delay module 121, the narrower the pulse width of the second pulse signal output by the second logic processing module 122. The second pulse signal can be called a narrow pulse width signal.

[0052] In summary, in the pulse generation circuit provided in this application embodiment, the first delay module in the first pulse unit can delay the falling edge of the square wave signal to generate and transmit a first delay signal to the first logic processing module, so that the first logic processing module can output a first pulse signal according to the first delay signal. The high-level duration of the first pulse signal is the same as the falling edge duration of the first delay signal. The second delay module in the second pulse unit can delay the rising edge of the square wave signal to generate and transmit a second delay signal to the second logic processing module, so that the second logic processing module can output a second pulse signal according to the second delay signal. The high-level duration of the second pulse signal is the same as the rising edge duration of the first delay signal. In this technical solution, the pulse generation circuit can delay the rising and falling edges of the input square wave signal to output a first pulse signal with a high-level duration equal to the falling edge duration, and a second pulse signal with a high-level duration equal to the rising edge duration. The pulse widths of the first and second pulse signals are narrower than the pulse width of the square wave signal, realizing the conversion from a square wave signal to a pulse signal with a narrower pulse width.

[0053] Optionally, such as Figure 2 As shown, the first delay module 111 includes a first inverter G1 and a first capacitor C1. The first inverter G1 is connected to the square wave input terminal IN, the first terminal of the first capacitor C1, and the first logic processing module 112. The second terminal of the first capacitor C1 is grounded.

[0054] The first inverter G1 and the first capacitor C1 are used to perform delay processing on the rising and falling edges of the square wave signal, generating and transmitting a first delayed signal to the first logic processing module 112. Specifically, the first inverter G1 is used to invert the square wave signal. The first capacitor C1 and the first inverter G1 work together to perform delay processing on the rising and falling edges of the inverted square wave signal, generating and transmitting a first delayed signal to the first logic processing module 112.

[0055] It should be noted that the first capacitor C1 can form a resistor-capacitor circuit (i.e., an RC circuit) with the internal resistor of the first inverter G1 to delay the rising and falling edges of the square wave signal. It should also be noted that the delay duration of the rising and falling edges of the square wave signal is positively correlated with the resistance value of the internal resistor of the first inverter G1 and the capacitance value of the first capacitor C1. In some embodiments, the first delay module 111 can also be a delay chain unit, which is used to delay the rising and falling edges of the square wave signal.

[0056] Optionally, the first logic processing module 112 is configured to output a high-level signal during the duration of the rising edge of the first delayed signal and a low-level signal during the remaining time period of the first delayed signal to obtain a first pulse signal. The remaining time period refers to the time period of the first delayed signal excluding the duration of the rising edge. For example, please refer to... Figure 3 It illustrates the embodiments provided in this application. Figure 2 The diagram shows a partial timing diagram of the pulse generation circuit. Figure 3 In this diagram, In represents the square wave signal received at the square wave input terminal. A represents the output signal of the first inverter G1. B represents the output signal of the first delay module 111, i.e., the signal at the path node between the first capacitor C1 and the first logic processing module 112, i.e., the first delay signal. Out1 represents the output signal of the first logic processing module 112, i.e., the first pulse signal. Figure 3 It can be seen that the first pulse signal Out1 output by the first logic processing module 112 is at a high level during the rising edge duration of signal B (i.e., the first delay signal) and at a low level during the rest of the signal B period.

[0057] In further optional cases, such as Figure 4As shown, the first logic processing module 112 may include: a second inverter G2, a third inverter G3, and a first AND gate L1. The second inverter G2 is connected to the square wave input terminal IN and the first AND gate L1. The third inverter G3 is connected to the first inverter G1 and the first AND gate L1.

[0058] The second inverter G2 inverts the square wave signal output from the square wave input IN, outputting the inverted square wave signal to the first AND gate L1. The third inverter G3 receives the first delayed signal output from the first inverter G1, inverts it, and outputs the inverted first delayed signal to the first AND gate L1. The first AND gate L1 performs a logical AND operation between the inverted square wave signal and the inverted first delayed signal to obtain the first pulse signal Out1, which is then output. Figure 4 In the case shown, the first AND gate L1 performs a logical AND operation on the inverted signal of the square wave signal and the inverted signal of the first delayed signal to output a high-level signal during the duration of the falling edge of the inverted signal of the first delayed signal and a low-level signal during the remaining duration of the inverted signal of the first delayed signal, so as to output the first pulse signal Out1.

[0059] For example, please refer to Figure 5 It illustrates the embodiments provided in this application. Figure 4 The diagram shows a partial timing diagram of the pulse generation circuit. Figure 4 In this diagram, In represents the square wave signal received at the square wave input terminal. A represents the output signal of the first inverter G1. B represents the output signal of the first delay module 111, i.e., the signal at the path node between the first capacitor C1 and the first logic processing module 112, i.e., the first delay signal. C represents the output signal of the third inverter G3. D represents the output signal of the second inverter G2. Out1 represents the output signal of the first AND gate L1, i.e., the first pulse signal. Figure 5 It can be seen that the first pulse signal Out1 output by the first AND gate L1 is high during the duration of the falling edge of signal C (i.e., the inverted signal of the first delayed signal), and low during the rest of the duration of signal C.

[0060] In some embodiments of this application, the second delay module 121 can be used to delay the falling edge of the inverted signal of the square wave signal to generate and transmit a second delayed signal to the second logic processing module 122.

[0061] In one alternative implementation, such as Figure 6As shown, the second delay module 121 may include: a fourth inverter G4, a fifth inverter G5, and a second capacitor C2. The fourth inverter G4 is connected to the square wave input terminal IN and the fifth inverter G5. The fifth inverter G5 is also connected to the first terminal of the second capacitor C2 and the second logic processing module 122. The second terminal of the second capacitor C2 is grounded.

[0062] The fifth inverter G5 and the second capacitor C2 are used to delay the rising and falling edges of the inverted square wave signal, generating and transmitting a second delayed signal to the second logic processing module 122. Specifically, the fourth inverter G4 inverts the square wave signal and outputs the inverted square wave signal to the fifth inverter G5. The fifth inverter G5 inverts the inverted square wave signal and outputs a square wave signal. The second capacitor C2 and the fifth inverter G5 work together to delay the rising and falling edges of the inverted square wave signal (i.e., the input signal of the fifth inverter G5), generating and transmitting a second delayed signal to the second logic processing module 122.

[0063] It should be noted that the second capacitor C2 can form a resistor-capacitor circuit (i.e., an RC circuit) with the internal resistor of the fifth inverter G5 to delay the rising and falling edges of the inverted square wave signal. It should also be noted that the delay duration of the rising and falling edges of the inverted square wave signal is positively correlated with the resistance value of the internal resistor of the fifth inverter G5 and the capacitance value of the second capacitor C2. In some embodiments, the second delay module 121 may further include a fourth inverter G4 and a delay chain unit. The fourth inverter G4 is connected to the square wave input terminal IN and the delay chain unit. The fourth inverter G4 is used to invert the square wave signal and output the inverted square wave signal to the delay chain unit. This delay chain unit is used to delay the rising and falling edges of the inverted square wave signal.

[0064] Optionally, the second logic processing module 122 is configured to output a high-level signal during the rising edge duration of the second delayed signal and a low-level signal during the remaining duration of the second delayed signal to obtain a second pulse signal. The remaining duration of the second delayed signal refers to the time period of the second delayed signal excluding the rising edge duration. For example, please refer to... Figure 7 It illustrates the embodiments provided in this application. Figure 6 The diagram shows a partial timing diagram of the pulse generation circuit. Figure 7In the diagram, In represents the square wave signal received at the square wave input terminal. E represents the output signal of the fourth inverter G4. F represents the output signal of the fifth inverter G5. H represents the output signal of the second delay module 121, i.e., the signal at the path node between the second capacitor C2 and the second logic processing module 122, i.e., the second delay signal. Out2 represents the output signal of the second logic processing module 122, i.e., the second pulse signal. Figure 7 It can be seen that the second pulse signal Out2 output by the second logic processing module 122 is at a high level during the rising edge duration of signal H (i.e., the second delay signal), and at a low level during the remaining duration of signal H.

[0065] Further optional, such as Figure 8 As shown, the second logic processing module 122 includes: an eighth inverter G8, a seventh inverter G7, and a second AND gate L2. The eighth inverter G8 is connected to the second AND gate L2 and is used to receive the inverted signal of the square wave signal. The seventh inverter G7 is connected to the fifth inverter G5 and the second AND gate L2.

[0066] In the second delay module 121, which includes a fourth inverter G4, a fifth inverter G5, and a second capacitor C, an eighth inverter G8 is connected to the fourth inverter G4. The eighth inverter G8 receives the inverted square wave signal output from the fourth inverter G4. The eighth inverter G8 inverts the inverted square wave signal and outputs the square wave signal to the second AND gate L2. The seventh inverter G7 receives the second delayed signal output from the fifth inverter G5, inverts the second delayed signal, and outputs the inverted second delayed signal to the second AND gate L2. The second AND gate L2 performs a logical AND operation on the inverted second delayed signal and the square wave signal to obtain the second pulse signal Out2, and outputs the second pulse signal Out2. Figure 8 In the case shown, the second AND gate L2 performs a logical AND operation on the inverted signals of the square wave signal and the second delayed signal to output a high-level signal during the rising edge duration of the inverted signal of the second delayed signal and a low-level signal during the remaining duration of the inverted signal of the second delayed signal, thereby outputting the second pulse signal Out2.

[0067] For example, please refer to Figure 9 It illustrates the embodiments provided in this application. Figure 8 The diagram shows a partial timing diagram of the pulse generation circuit. Figure 8In the diagram, In represents the square wave signal received at the square wave input terminal. E represents the output signal of the fourth inverter G4. F represents the output signal of the fifth inverter G5. H represents the output signal of the second delay module 121, i.e., the signal at the path node between the second capacitor C2 and the second logic processing module 122, i.e., the second delay signal. I represents the output signal of the seventh inverter G7. J represents the output signal of the eighth inverter G8. Out2 represents the output signal of the second AND gate L2, i.e., the second pulse signal. Figure 9 It can be seen that the second pulse signal Out2 output by the second AND gate L2 is high during the duration of the falling edge of signal I (i.e., the inverted signal of the second delay signal), and low during the rest of the signal I.

[0068] In another alternative implementation, the first logic processing module 112 is Figure 4 In the case of the first logic processing module 112 shown, that is, if the first logic processing module 112 includes a second inverter G2, a third inverter G3, and a first AND gate L1. The second inverter G2 is connected to the square wave input terminal IN and the first AND gate L1. The third inverter G3 is connected to the first inverter G1 and the first AND gate L1. Figure 10 As shown, the second delay module 121 includes: a sixth inverter G6 and a third capacitor C3.

[0069] The sixth inverter G6 is connected to the second inverter G2, the first terminal of the third capacitor C3, and the second logic processing module 122. The second terminal of the third capacitor C3 is grounded. The sixth inverter G6 and the third capacitor C3 are used to perform delay processing on the rising and falling edges of the inverted square wave signal, generating and transmitting a second delayed signal to the second logic processing module 122. Specifically, the sixth inverter G6 receives the inverted square wave signal output from the second inverter G2 and inverts it. The third capacitor C3 and the sixth inverter G6, in conjunction with the rising and falling edges of the inverted square wave signal, perform delay processing on the second logic processing module 122, generating and transmitting a second delayed signal to the second logic processing module 122.

[0070] It should be noted that the third capacitor C3 can form a resistor-capacitor circuit (i.e., an RC circuit) with the internal resistor of the sixth inverter G6 to delay the rising and falling edges of the inverted square wave signal. It should also be noted that the delay duration of the rising and falling edges of the inverted square wave signal is positively correlated with the resistance value of the internal resistor of the sixth inverter G6 and the capacitance value of the third capacitor C3. In some embodiments, the second delay module 121 can also be a delay chain unit, which is used to delay the rising and falling edges of the inverted square wave signal.

[0071] Optionally, the second logic processing module 122 is configured to output a high-level signal during the rising edge duration of the second delayed signal and a low-level signal during the remaining duration of the second delayed signal to obtain a second pulse signal. The remaining duration of the second delayed signal refers to the time period of the second delayed signal excluding the rising edge duration. For example, please refer to... Figure 11 It illustrates the embodiments provided in this application. Figure 10 The diagram shows a partial timing diagram of the pulse generation circuit. Figure 11 In the diagram, In represents the square wave signal received at the square wave input terminal. D represents the output signal of the second inverter G2. F represents the output signal of the fifth inverter G5. H represents the output signal of the second delay module 121, i.e., the signal at the path node between the second capacitor C2 and the second logic processing module 122, i.e., the second delay signal. Out2 represents the output signal of the second logic processing module 122, i.e., the second pulse signal. Figure 11 It can be seen that the second pulse signal Out2 output by the second logic processing module 122 is at a high level during the rising edge duration of signal H (i.e., the second delay signal), and at a low level during the remaining duration of signal H.

[0072] Further optional, such as Figure 12 As shown, the second logic processing module 122 includes: an eighth inverter G8, a seventh inverter G7, and a second AND gate L2. The eighth inverter G8 is connected to the second AND gate L2 and is used to receive the inverted signal of the square wave signal. The seventh inverter G7 is connected to the sixth inverter G6 and the second AND gate L2.

[0073] In the second delay module 121, which includes a sixth inverter G6 and a third capacitor C3, an eighth inverter G8 is connected to the second inverter G2. The eighth inverter G8 receives the inverted square wave signal output from the second inverter G2. The eighth inverter G8 inverts the inverted square wave signal and outputs the square wave signal to the second AND gate L2. The seventh inverter G7 receives the second delayed signal output from the sixth inverter G6, inverts the second delayed signal, and outputs the inverted second delayed signal to the second AND gate L2. The second AND gate L2 performs a logical AND operation on the inverted second delayed signal and the square wave signal to obtain the second pulse signal Out2, and outputs the second pulse signal Out2. Figure 12 In the case shown, the second AND gate L2 performs a logical AND operation on the inverted signals of the square wave signal and the second delayed signal to output a high-level signal during the rising edge duration of the inverted signal of the second delayed signal and a low-level signal during the remaining duration of the inverted signal of the second delayed signal, thereby outputting the second pulse signal Out2.

[0074] For example, please refer to Figure 13 It illustrates the embodiments provided in this application. Figure 12 The diagram shows a partial timing diagram of the pulse generation circuit. Figure 13 In the diagram, In represents the square wave signal received at the square wave input terminal. D represents the output signal of the second inverter G2. F represents the output signal of the sixth inverter G6. H represents the output signal of the second delay module 121, i.e., the signal at the path node between the second capacitor C2 and the second logic processing module 122, i.e., the second delay signal. I represents the output signal of the seventh inverter G7. J represents the output signal of the eighth inverter G8. Out2 represents the output signal of the second AND gate L2, i.e., the second pulse signal. Figure 13 It can be seen that the second pulse signal Out2 output by the second AND gate L2 is high during the duration of the falling edge of signal I (i.e., the inverted signal of the second delay signal), and low during the rest of the signal I.

[0075] To facilitate understanding of the pulse generation circuit 1 provided in this application, the pulse generation circuit 1 of the technical solution of this application will be schematically described below with reference to examples. For example, as... Figure 12 As shown, the pulse generation circuit 1 includes: a square wave input terminal IN, a first pulse unit 11, and a second pulse unit 12. The square wave input terminal IN is used to receive square wave signals.

[0076] The first pulse unit 11 includes a first delay module 111 and a first logic processing module 112. The first delay module 111 includes a first inverter G1 and a first capacitor C1. The first inverter G1 is connected to the square wave input terminal IN, the first terminal of the first capacitor C1, and the first logic processing module 112. The second terminal of the first capacitor C1 is grounded. The first logic processing module 112 may include a second inverter G2, a third inverter G3, and a first AND gate L1. The second inverter G2 is connected to the square wave input terminal IN and the first AND gate L1. The third inverter G3 is connected to the first inverter G1 and the first AND gate L1.

[0077] The second pulse unit 12 includes a second delay module 121 and a second logic processing module 122. The second delay module 121 includes a sixth inverter G6 and a third capacitor C3. The sixth inverter G6 is connected to the second inverter G2, the first terminal of the third capacitor C3, and the second logic processing module 122. The second terminal of the third capacitor C3 is grounded. The second logic processing module 122 includes an eighth inverter G8, a seventh inverter G7, and a second AND gate L2. The eighth inverter G8 is connected to the second AND gate L2. The eighth inverter G8 is connected to the second inverter G2. The seventh inverter G7 is connected to the sixth inverter G6 and the second AND gate L2.

[0078] Please refer to Figure 14 It illustrates the embodiments provided in this application. Figure 12 The diagram shows a partial timing diagram of the pulse generation circuit. Figure 14 In this diagram, In represents the square wave signal received at the square wave input terminal. A represents the output signal of the first inverter G1. B represents the output signal of the first delay module 111, i.e., the signal at the path node between the first capacitor C1 and the first logic processing module 112, i.e., the first delay signal. C represents the output signal of the third inverter G3. D represents the output signal of the second inverter G2. F represents the output signal of the sixth inverter G6. H represents the output signal of the second delay module 121, i.e., the signal at the path node between the second capacitor C2 and the second logic processing module 122, i.e., the second delay signal. I represents the output signal of the seventh inverter G7. J represents the output signal of the eighth inverter G8. Out1 represents the output signal of the first AND gate L1, i.e., the first pulse signal. Out2 represents the output signal of the second AND gate L2, i.e., the second pulse signal. Figure 14 It can be seen that the first pulse signal Out1 output by the first AND gate L1 is high during the duration of the falling edge of signal C (i.e., the inverted signal of the first delayed signal), and low during the remaining duration of signal C. The second pulse signal Out2 output by the second AND gate L2 is high during the duration of the falling edge of signal I (i.e., the inverted signal of the second delayed signal), and low during the remaining duration of signal I.

[0079] In the embodiments of this application Figure 12 In the pulse generation circuit shown, the received square wave signal is first inverted using a first inverter G1 to obtain signal A. Then, the square wave signal is delayed using a first capacitor C1 and the internal resistor of the first inverter G1 to obtain signal B. Next, signal B is inverted using a third inverter G3 to obtain signal C. Furthermore, the square wave signal is inverted using a second inverter G2 to obtain signal D. Signals C and D are then logically ANDed using a first AND gate L1 to obtain the first pulse signal Out1. In this pulse generation circuit, signal D can also be inverted using a sixth inverter G6 to obtain signal F.

[0080] Signal F is delayed by the second capacitor C2 and the internal resistor of the sixth inverter G6 to obtain signal H. Then, signal H is inverted by the seventh inverter G7 to obtain signal I. Furthermore, signal D is inverted by the eighth inverter G8 to obtain signal J. Signals I and J are then logically ANDed by the second AND gate L2 to obtain the second pulse signal Out2.

[0081] In this embodiment, the pulse generation circuit 1 can be composed of six inverters, two capacitors, and two AND gates. Related pulse generation circuits typically include: a square wave receiver, twelve inverters INV1-INV12, two P-type metal-oxide-semiconductor (PMOS) transistors P1-P2, two N-type metal-oxide-semiconductor (NMOS) transistors N1-N2, two resistors R1-R2, two capacitors CR1-CR2, and two NOR gates NOR1-NOR2. The square wave receiver is used to receive square wave signals.

[0082] The gate of PMOS P1 is connected to the square wave receiver, and the source of PMOS P1 is connected to the power supply. The drain of PMOS P1 is connected to one end of resistor R1, one end of inverter INV1, and one end of capacitor CR1. The gate of NMOS N1 is connected to the square wave receiver, the drain of NMOS N1 is connected to the other end of resistor R1, and the source of NMOS N1 is connected to the common terminal. The other end of capacitor CR1 is also connected to the common terminal. Inverter INV1 is also connected to the input of NOR gate NOR1 in sequence through inverters INV2 and INV3. Inverter INV4 is connected to the square wave receiver and the input of NOR gate NOR1. The output of NOR gate NOR1 is also connected to inverters INV5 and INV6 in sequence and the first pulse signal output.

[0083] The gate of PMOS P2 is connected to inverter INV4, the source of PMOS P2 is connected to the power supply terminal, and the drain of PMOS P2 is connected to one end of resistor R2, one end of inverter INV7, and one end of capacitor CR2. The gate of NMOS N2 is connected to inverter INV4, the drain of NMOS N2 is connected to the other end of resistor R2, and the source of NMOS N2 is connected to the common terminal. The other end of capacitor CR2 is also connected to the common terminal. Inverter INV7 is also connected to the input of NOR gate NOR2 in sequence through inverters INV8 and INV9. Inverter INV10 is connected to the input of inverter INV4 and NOR gate NOR2. The output of NOR gate NOR2 is also connected to inverters INV11 and INV12 in sequence and the second pulse signal output terminal. This pulse generation circuit 1 converts the square wave signal provided by the square wave input terminal into two narrow pulse width pulse signals, which are output through the first pulse signal output terminal and the second pulse signal output terminal, respectively. Obviously, the pulse generation circuit 1 in this embodiment has the characteristics of low circuit complexity, simple structure, few components, and high reliability.

[0084] In summary, in the pulse generation circuit provided in this application embodiment, the first delay module in the first pulse unit can delay the falling edge of the square wave signal to generate and transmit a first delay signal to the first logic processing module, so that the first logic processing module can output a first pulse signal according to the first delay signal. The high-level duration of the first pulse signal is the same as the falling edge duration of the first delay signal. The second delay module in the second pulse unit can delay the rising edge of the square wave signal to generate and transmit a second delay signal to the second logic processing module, so that the second logic processing module can output a second pulse signal according to the second delay signal. The high-level duration of the second pulse signal is the same as the rising edge duration of the first delay signal. In this technical solution, the pulse generation circuit can delay the rising and falling edges of the input square wave signal to output a first pulse signal with a high-level duration equal to the falling edge duration, and a second pulse signal with a high-level duration equal to the rising edge duration. The pulse widths of the first and second pulse signals are narrower than the pulse width of the square wave signal, realizing the conversion from a square wave signal to a pulse signal with a narrower pulse width.

[0085] This application also provides a driver chip. The driver chip may include the pulse generation circuit provided in this application embodiment. Optionally, the driver chip may include the components described in this application embodiment. Figure 1 , Figure 2 , Figure 4 , Figure 6 , Figure 8 , Figure 10 or Figure 12 The pulse generation circuit shown.

[0086] In some embodiments of this application, such as Figure 15 As shown, the driver chip further includes: an interface logic circuit 2, a first level conversion circuit 3, a pulse generation circuit 1, a second level conversion circuit 4, a pulse recovery circuit 5, and an output driver circuit 6. The interface logic circuit 2 is sequentially connected to the first level conversion circuit 3, the pulse generation circuit 1, the second level conversion circuit 4, the pulse recovery circuit 5, and the output driver circuit 6. The pulse generation circuit 1 is the pulse generation circuit provided in the embodiment of this application.

[0087] The interface logic circuit 2 can receive a square wave signal of a first voltage provided by an external signal generation unit, filter noise in the square wave signal to improve its compatibility. The interface logic circuit 2 can also output the noise-filtered square wave signal to the first level conversion circuit 3. The first level conversion circuit 3 converts the square wave signal of the first voltage into a square wave signal of a second voltage and outputs the square wave signal of the second voltage to the pulse generation circuit 1. This second voltage is greater than the first voltage. The pulse generation circuit 1 converts the received square wave signal of the second voltage into a first pulse signal and a second pulse signal, and outputs the first pulse signal and the second pulse signal to the second level conversion circuit 4. The first pulse signal and the second pulse signal are pulse signals of the second voltage, and their pulse widths are less than those of the square wave signal of the second voltage.

[0088] The second level conversion circuit 4 converts the first pulse signal of the second voltage into the first pulse signal of the third voltage, and the second pulse signal of the second voltage into the second pulse signal of the third voltage, outputting the first pulse signal and the second pulse signal of the third voltage to the pulse recovery circuit 5. The third voltage is much larger than the second voltage. The pulse recovery circuit 5 recovers the square wave signal of the third voltage based on the first and second pulse signals of the third voltage, and outputs the square wave signal of the third voltage to the output drive circuit 6. The output drive circuit 6 generates the drive current of the IGBT based on the square wave drive signal of the third voltage, which is used to power the IGBT to emit light.

[0089] In this embodiment, when the driver chip needs to convert a square wave signal of a second voltage into a square wave signal of a third voltage that is much larger than the second voltage, the pulse generation circuit 1 first converts the square wave signal of the second voltage into a narrow pulse signal of the second voltage (i.e., a first pulse signal and a second pulse signal), thereby converting the narrow pulse signal of the second voltage into a narrow pulse signal of the third voltage. Then, the narrow pulse signal of the third voltage is restored to a square wave signal of the third voltage, thus achieving the square wave signal conversion. In this way, the signal pulse width during the level conversion process is reduced. Therefore, the device losses during the level conversion process are reduced, thereby effectively improving the reliability of the driver chip and effectively optimizing the driver chip circuit.

[0090] In some embodiments of this application, the interface logic circuit 2 can be used to output a noise-filtered square wave signal to the pulse generation circuit 1. The pulse generation circuit 1 is also used to convert the square wave signal of the first voltage into a third pulse signal and a fourth pulse signal, and output the third pulse signal and the fourth pulse signal to the first level conversion circuit 3. The third pulse signal and the fourth pulse signal are pulse signals of the first voltage, and the pulse width of the third pulse signal and the fourth pulse signal is smaller than that of the square wave signal of the first voltage.

[0091] The first level conversion circuit 3 converts the third pulse signal of the first voltage into the third pulse signal of the second voltage, and converts the fourth pulse signal of the first voltage into the fourth pulse signal of the second voltage, and outputs the third pulse signal and the fourth pulse signal of the second voltage to the pulse recovery circuit 5. The pulse recovery circuit 5 is also used to recover the square wave signal of the second voltage based on the third pulse signal and the fourth pulse signal of the second voltage.

[0092] In this embodiment, the driver chip can further convert the square wave signal of the first voltage to a square wave signal of the second voltage (which is greater than the first voltage) into a narrow pulse signal of the first voltage using the pulse generation circuit 1. This narrow pulse signal is then converted into a narrow pulse signal of the second voltage. The narrow pulse signal of the second voltage is then restored to a square wave signal of the second voltage, thus achieving the square wave signal conversion. This further reduces the signal pulse width during the level conversion process, thereby reducing device losses and effectively improving the reliability of the driver chip, further optimizing the driver chip circuitry.

[0093] For example, assume the first voltage is 3.3V, the second voltage is 15V, and the third voltage is 615V. The external signal generation unit can be an MCU, controller, etc., which provides the PWM square wave drive signal (a square wave signal). For example... Figure 16 As shown, the MCU provides a 3.3V PWM square wave drive signal, referred to as the 3.3V square wave signal. The control methods of the driver chip include:

[0094] The control interface logic circuit 2 receives a 3.3V square wave signal from the MCU, filters out noise in the 3.3V square wave signal, and improves pulse signal compatibility. It controls the first level conversion circuit 3 (3.3V~15V level conversion circuit), which receives the 3.3V square wave signal output from the interface logic circuit 2 and converts it into a 15V square wave signal. The pulse generation circuit 1 receives the 15V square wave signal and converts it into an extremely narrow pulse signal, also known as a 15V narrow pulse signal. The second level conversion circuit 4 (15V~615V level conversion circuit) converts the 15V narrow pulse signal into a 615V narrow pulse signal. Finally, the pulse recovery circuit 5 receives the 615V narrow pulse signal and converts it into a 615V square wave signal. The control output drive circuit 6 receives a 615V square wave signal and generates the drive current for the IGBT to emit light.

[0095] In summary, in the driver chip provided in this application embodiment, the first delay module in the first pulse unit of the pulse generation circuit can delay the falling edge of the square wave signal to generate and transmit a first delay signal to the first logic processing module, so that the first logic processing module can output a first pulse signal according to the first delay signal. The high-level duration of the first pulse signal is the same as the falling edge duration of the first delay signal. Similarly, the second delay module in the second pulse unit can delay the rising edge of the square wave signal to generate and transmit a second delay signal to the second logic processing module, so that the second logic processing module can output a second pulse signal according to the second delay signal. The high-level duration of the second pulse signal is the same as the rising edge duration of the first delay signal. In this technical solution, the pulse generation circuit can delay the rising and falling edges of the input square wave signal to output a first pulse signal with a high level duration equal to the falling edge duration, and a second pulse signal with a high level duration equal to the rising edge duration. The pulse widths of the first and second pulse signals are narrower than the pulse width of the square wave signal, thus realizing the conversion from the square wave signal to a pulse signal with a narrower pulse width.

[0096] This application also provides an electronic device, which may include the pulse generation circuit provided in this application embodiment. Alternatively, the electronic device may include the driver chip provided in this application embodiment. In this way, in the electronic device provided in this application embodiment, the first delay module in the first pulse unit of the pulse generation circuit can delay the falling edge of the square wave signal to generate and transmit a first delay signal to the first logic processing module, so that the first logic processing module can output a first pulse signal according to the first delay signal, the high-level duration of the first pulse signal being equal to the falling edge duration of the first delay signal. The second delay module in the second pulse unit can delay the rising edge of the square wave signal to generate and transmit a second delay signal to the second logic processing module, so that the second logic processing module can output a second pulse signal according to the second delay signal, the high-level duration of the second pulse signal being equal to the rising edge duration of the first delay signal. In this technical solution, the pulse generation circuit can delay the rising and falling edges of the input square wave signal to output a first pulse signal with a high level duration equal to the falling edge duration, and a second pulse signal with a high level duration equal to the rising edge duration. The pulse widths of the first and second pulse signals are narrower than the pulse width of the square wave signal, thus realizing the conversion from the square wave signal to a pulse signal with a narrower pulse width.

[0097] Optionally, the electronic device may further include a processor and a memory. The memory is used to store computer programs. The processor, when executing the program stored in the memory, implements the control method of the driver chip in the method embodiments of this application.

[0098] This application embodiment also provides a readable storage medium storing a program or instructions, which, when executed by a processor, implements the control method of the aforementioned driver chip. The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0099] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A pulse generating circuit, characterized by, The pulse generation circuit comprises a square wave input end, a first pulse unit and a second pulse unit, the square wave input end is used for receiving a square wave signal; The first pulse unit comprises a first delay module and a first logic processing module, the first delay module is connected with the square wave input end and the first logic processing module; The first delay module is used for performing delay processing on a falling edge of the square wave signal, generating and transmitting a first delay signal to the first logic processing module; The first logic processing module is used for outputting a first pulse signal according to the first delay signal, a high level duration of the first pulse signal is a falling edge duration of the first delay signal; The second pulse unit comprises a second delay module and a second logic processing module, the second delay module is connected with the square wave input end and the second logic processing module respectively; The second delay module is used for performing delay processing on a rising edge of the square wave signal, generating and transmitting a second delay signal to the second logic processing module; The second logic processing module is used for outputting a second pulse signal according to the second delay signal, a high level duration of the second pulse signal is a rising edge duration of the first delay signal.

2. The pulse generating circuit of claim 1, wherein, The first delay module comprises a first inverter and a first capacitor; The first inverter is connected with the square wave input end, a first end of the first capacitor and the first logic processing module respectively, and a second end of the first capacitor is grounded; The first inverter and the first capacitor are used for cooperating to perform delay processing on the rising edge and the falling edge of the square wave signal, generating and transmitting the first delay signal to the first logic processing module.

3. The pulse generating circuit of claim 2, wherein, The first logic processing module is used for outputting a high level signal in a rising edge duration of the first delay signal, and outputting a low level signal in a remaining period of the first delay signal, so as to obtain the first pulse signal, the remaining period is a period of the first delay signal except the rising edge duration.

4. The pulse generating circuit of claim 3, wherein, The first logic processing module comprises a second inverter, a third inverter and a first AND gate; The second inverter is connected with the square wave input end and the first AND gate respectively, and the third inverter is connected with the first inverter and the first AND gate.

5. The pulse generating circuit of claim 4, wherein, The second delay module is used for performing delay processing on a falling edge of an inverse signal of the square wave signal, generating and transmitting a second delay signal to the second logic processing module.

6. The pulse generating circuit of claim 5, wherein, The second delay module comprises a fourth inverter, a fifth inverter and a second capacitor; The fourth inverter is connected with the square wave input end and the fifth inverter respectively, the fifth inverter is also connected with a first end of the second capacitor and the second logic processing module respectively, and a second end of the second capacitor is grounded; The fifth inverter and the second capacitor are used for cooperating to perform delay processing on the rising edge and the falling edge of the inverse signal, generating and transmitting the second delay signal to the second logic processing module.

7. The pulse generating circuit of claim 6, wherein, The first logic processing module comprises a second inverter, a third inverter and a first AND gate; the second inverter is connected with the square wave input end and the first AND gate respectively, and the third inverter is connected with the first inverter and the first AND gate respectively. The second delay module comprises a sixth inverter and a third capacitor; the sixth inverter is connected with the second inverter, the first end of the third capacitor and the second logic processing module respectively, and the second end of the third capacitor is grounded. The sixth inverter and the third capacitor are used for delaying the rising edge and the falling edge of the inverted signal, generating and transmitting a second delay signal to the second logic processing module.

8. The pulse generating circuit of any one of claims 5 to 7, wherein, The second logic processing module is used for outputting a high-level signal in a rising edge duration of the second delay signal and outputting a low-level signal in the rest duration of the second delay signal to obtain the second pulse signal, wherein the rest duration of the second delay signal is a duration of the second delay signal except the rising edge duration.

9. The pulse generating circuit of claim 8, wherein, The second logic processing module comprises an eighth inverter, a seventh inverter and a second AND gate. The eighth inverter is connected with the second AND gate respectively to receive the inverted signal of the square wave signal, and the seventh inverter is connected with the second delay module and the second AND gate respectively.

10. The pulse generating circuit of claim 9, wherein, The second delay module comprises a fourth inverter, a fifth inverter and a second capacitor, and the eighth inverter is connected with the fourth inverter. Alternatively, the second delay module comprises a sixth inverter and a third capacitor, the first logic processing module comprises a second inverter, a third inverter and a first AND gate, and the eighth inverter is connected with the second inverter.

11. A driver chip, characterized by comprising: The driving chip comprises the pulse generation circuit according to any one of claims 1 to 10.

12. An electronic device, comprising: The electronic device comprises the driving chip according to claim 11.

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