Anti-oscillation circuit for power supply output voltage power-off process

Abstract

The utility model relates to the technical field of power-off logic control, in particular to an anti-oscillation circuit for a power supply output voltage power-off process, which is characterized in that a voltage comparison unit is arranged to sample an output voltage, different reference voltages are arranged to realize different functions, and power supply is controlled by generating a first detection signal. The power-off detection function is not triggered by mistake, the output voltage is detected through the second detection signal to judge whether the output is powered off or not, if the power-off output signal is detected to the delay unit, a set fixed-time square wave is output to turn off the power supply enable, and the power supply enable is reset after the output voltage is detected to be reduced through the third detection signal, so that the power supply enable becomes effective again. The time delay from the output power-off to the turn-off of the power supply is only 1-2 microseconds, and the oscillation in the power-off process of the output voltage can be controlled in time.

Description

Technical Field

[0001] This utility model relates to the field of power-down logic control technology, specifically, to an anti-oscillation circuit for the power supply output voltage power-down process. Background Technology

[0002] For electronic devices with high power supply quality requirements, large fluctuations in the power supply voltage, especially oscillations near the operating threshold, can cause abnormal system states, shutdowns, and malfunctions. Therefore, some systems require that the power supply not oscillate during power-down to prevent frequent switching of downstream circuits and subsequent damage. Furthermore, each power-down must discharge the output voltage to a low level to ensure sufficient reset of downstream circuits and prevent high voltage stored in the output or downstream circuit energy storage devices from flowing back into the power supply and damaging components upon power-up.

[0003] There are normal power-off and abnormal power-off. Normal power-off is when the power enable signal is turned off by an external control circuit. Abnormal power-off is caused by a power supply failure or unstable input voltage, which causes the output to lose power. Regardless of whether it is normal or abnormal, the output must not oscillate and must be turned off for a period of time and discharged to a lower voltage before it can be powered on again. Utility Model Content

[0004] This invention addresses the problem that the output voltage needs to decrease monotonically without oscillation during power-down, and that restarting should only be allowed after the output voltage has been discharged to a low level. It proposes an anti-oscillation circuit for the power supply output voltage during power-down. By setting a voltage comparison unit to sample the output voltage and using different reference voltages to achieve different functions, a first detection signal is generated to control the power supply, preventing false triggering of the power-down detection function. A second detection signal detects the output voltage to determine if the output is powered down. If a power-down signal is detected, a delay unit outputs a pre-set fixed-time square wave to turn off the power supply enable. A third detection signal detects a decrease in the output voltage and resets the circuit, making the power supply enable active again. The delay from output power-down to power-off is only in the range of 1-2 microseconds, effectively controlling oscillations during the power-down process.

[0005] The specific implementation details of this utility model are as follows:

[0006] An anti-oscillation circuit for power supply output voltage during the power-down process includes a voltage comparison unit and a delay unit;

[0007] The voltage comparison unit receives and outputs voltage at its input terminal, and its output terminal is connected to the input terminal of the delay unit.

[0008] The output terminal of the delay unit is connected to the power enable terminal;

[0009] The voltage comparison unit first samples the output voltage and generates a first detection signal based on the set first reference voltage and the output voltage. Then, based on the first detection signal, it controls the power-on process to prevent triggering a power-down detection. Next, based on the output voltage and the set second reference voltage, it generates a second detection signal to detect whether the output voltage has been powered down and generates a power-down output signal. Finally, based on the output voltage and the set third reference voltage, it generates a third detection signal to detect whether the output voltage has been de-energized; if the output voltage has been de-energized, it resets.

[0010] The delay unit is used to generate a fixed-time square wave to turn off the power enable based on the acquired power-down output signal.

[0011] To better realize the present invention, the voltage comparison unit further includes a first voltage comparison unit, a second voltage comparison unit, a third voltage comparison unit, a first reference voltage source, a second reference voltage source, and a third reference voltage source;

[0012] The non-inverting input of the first voltage comparator is connected to the inverting input of the third voltage comparator. The inverting input of the first voltage comparator is connected to ground through the first reference voltage source. The output of the first voltage comparator is connected to the positive power supply interface of the second voltage comparator. The positive power supply interface of the first voltage comparator is connected to the positive terminal of the output voltage. The negative power supply interface of the first voltage comparator is connected to ground.

[0013] The inverting terminal of the second voltage comparator is connected to the positive terminal of the output voltage, the non-inverting terminal of the second voltage comparator is connected to the negative terminal of the output voltage through a second reference voltage source, the positive power supply interface of the second voltage comparator is connected to the output terminal of the first voltage comparator, and the output terminal of the second voltage comparator is connected to the input terminal of the delay unit.

[0014] The non-inverting terminal of the third voltage comparator is connected to ground via a third reference voltage source. The output terminal of the third voltage comparator is connected between the negative power supply interface of the second voltage comparator and the output terminal of the first voltage comparator. The positive power supply interface of the third voltage comparator is connected to an auxiliary power supply device, and the negative power supply interface of the third voltage comparator is connected to ground.

[0015] To better realize the present invention, the first voltage comparison unit further includes an operational amplifier U1, a diode D1, a resistor R3, and a capacitor C1;

[0016] One end of the diode D1 is connected to the output terminal of the operational amplifier U1, and the other end is connected to the input terminal of the resistor R3;

[0017] One end of the capacitor C1 is connected to the negative terminal of the first reference voltage source, and the other end is connected between the output terminal of the resistor R3 and the negative power supply interface of the second voltage comparison unit.

[0018] The positive power supply interface of the operational amplifier U1 is connected to the positive terminal of the output voltage, the non-inverting terminal of the operational amplifier U1 is connected between the negative terminal and the positive terminal of the output voltage, and the inverting terminal of the operational amplifier is connected to the positive output terminal of the first reference voltage source.

[0019] To better realize the present invention, the second voltage comparison unit further includes an operational amplifier U2 and a transistor Q2;

[0020] The inverting terminal of the operational amplifier U2 is connected between the positive and negative terminals of the output voltage. The non-inverting terminal of the operational amplifier U2 is connected to the positive output terminal of the second reference voltage source. The negative power supply interface of the operational amplifier U2 is connected between the negative terminal of the output voltage and the emitter of the transistor Q2. The positive power supply interface of the operational amplifier U2 is connected between the output terminal of the resistor R3 and the capacitor C1.

[0021] The base of transistor Q2 is connected to the output terminal of operational amplifier U2, and the collector of transistor Q2 is connected to the input terminal of delay circuit.

[0022] To better realize the present invention, the third voltage comparison unit further includes an operational amplifier U3 and a transistor Q1;

[0023] The inverting terminal of the operational amplifier U3 is connected to the non-inverting terminal of the operational amplifier U1, the non-inverting terminal of the operational amplifier U3 is connected to the positive output terminal of the third reference voltage source, the positive power supply interface of the operational amplifier U3 is connected to the auxiliary power supply equipment, and the negative power supply interface of the operational amplifier U3 is connected to the ground terminal.

[0024] The base of transistor Q1 is connected to the output terminal of operational amplifier U3, the emitter of transistor Q1 is connected to the negative output terminal of the third voltage reference source, and the collector of transistor Q1 is connected between the negative power supply interface of operational amplifier U2 and the output terminal of resistor R3.

[0025] To better realize the present invention, the delay unit further includes a timer U4 and a transistor Q3;

[0026] The TRIG pin of the timer U4 is connected to the collector of the transistor Q2, the VCC pin of the timer U4 is connected to the auxiliary power supply, the GND pin of the timer U4 is connected to ground, and the OUTPUT pin of the timer U4 is connected to the base of the transistor Q3.

[0027] The collector of transistor Q3 is connected to the power enable terminal, and the emitter of transistor Q3 is connected to the negative terminal of the output voltage.

[0028] To better realize the present invention, the anti-oscillation circuit for the power supply output voltage down-process further includes resistors R1 and R2;

[0029] One end of the resistor R1 is connected between the positive terminal of the output voltage and the positive power supply interface of the operational amplifier U1, and the other end of the resistor R1 is connected to the inverting input of the operational amplifier U2.

[0030] One end of the resistor R2 is connected between the resistor R1 and the inverting input of the operational amplifier U2, and the other end is connected between the negative terminal of the output voltage and the emitter of the transistor Q3.

[0031] To better realize the present invention, the anti-oscillation circuit for the power supply output voltage under power-down process further includes a low dropout chip U5;

[0032] One end of the low-dropout chip U5 is connected between the positive terminal of the output voltage and the resistor R1, and the other end is connected to the positive power supply interface of the operational amplifier U1.

[0033] To better realize the present invention, the timer U4 is further described as an SE555 chip.

[0034] To better realize the present invention, the low dropout chip U5 is further described as an LDO chip.

[0035] This utility model has the following beneficial effects:

[0036] (1) When the output voltage of this utility model reaches the undervoltage value, the power supply is immediately turned off for a period of time to turn off the output, and the output voltage is kept off until it is lower than a certain value, at which point the power supply is turned on to restart automatically and effectively, so that the output voltage does not oscillate while the output voltage detection and control circuit responds quickly.

[0037] (2) The delay from power-down to power-off of this utility model is only 1 to 2 microseconds, which can timely control the oscillation during the power-down process of the output voltage;

[0038] (3) This utility model has the function of preventing false triggering during power-on process and has a fixed shutdown time after normal triggering and power-off. Therefore, the detection circuit does not need additional filtering delay. It has microsecond-level fast detection control, fixed shutdown time and self-recovery function, which ensures that the output voltage does not oscillate during power-off process. Attached Figure Description

[0039] Figure 1 The overall structural circuit diagram provided for this utility model.

[0040] Figure 2 This is a schematic diagram showing the voltage change when the output voltage discharges to the reset time, which is greater than the fixed shutdown time, according to an embodiment of the present invention.

[0041] Figure 3 This is a schematic diagram illustrating the voltage change when the output voltage discharges to the reset time, which is less than the fixed shutdown time, according to an embodiment of the present invention. Detailed Implementation

[0042] To more clearly illustrate the technical solutions of the embodiments of this utility model, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the described embodiments are only some embodiments of this utility model, not all embodiments, and therefore should not be regarded as a limitation on the scope of protection. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0043] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "set up," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0044] Example 1:

[0045] This embodiment proposes an anti-oscillation circuit for the power supply output voltage during the power-down process, including a voltage comparison unit and a delay unit;

[0046] The voltage comparison unit receives and outputs voltage at its input terminal, and its output terminal is connected to the input terminal of the delay unit.

[0047] The output terminal of the delay unit is connected to the power enable terminal;

[0048] The voltage comparison unit first samples the output voltage and generates a first detection signal based on the set first reference voltage and the output voltage. Then, based on the first detection signal, it controls the power-on process to prevent triggering a power-down detection. Next, based on the output voltage and the set second reference voltage, it generates a second detection signal to detect whether the output voltage has been powered down and generates a power-down output signal. Finally, based on the output voltage and the set third reference voltage, it generates a third detection signal to detect whether the output voltage has been de-energized; if the output voltage has been de-energized, it resets.

[0049] The delay unit is used to generate a fixed-time square wave to turn off the power enable based on the acquired power-down output signal.

[0050] Working Principle: This embodiment samples the output voltage using a voltage comparison unit and achieves different functions by setting different reference voltages. A first detection signal is generated to control the power supply, preventing accidental triggering of the power-down detection function. A second detection signal detects the output voltage to determine if the output is powered down. If a power-down signal is detected, a delay unit outputs a pre-set fixed-time square wave to turn off the power enable. A third detection signal detects a decrease in the output voltage and resets the power enable, making it active again. The delay from output power-down to power-down is only on the order of 1-2 microseconds, enabling timely control of oscillations during the output voltage power-down process.

[0051] Example 2:

[0052] This embodiment describes the specific structure of the voltage comparison unit based on the above embodiment 1.

[0053] The voltage comparison unit includes a first voltage comparison unit, a second voltage comparison unit, a third voltage comparison unit, a first reference voltage source, a second reference voltage source, and a third reference voltage source;

[0054] The non-inverting input of the first voltage comparator is connected to the inverting input of the third voltage comparator. The inverting input of the first voltage comparator is connected to ground through the first reference voltage source. The output of the first voltage comparator is connected to the positive power supply interface of the second voltage comparator. The positive power supply interface of the first voltage comparator is connected to the positive terminal of the output voltage. The negative power supply interface of the first voltage comparator is connected to ground.

[0055] The inverting terminal of the second voltage comparator is connected to the positive terminal of the output voltage, the non-inverting terminal of the second voltage comparator is connected to ground through the second reference voltage source, the positive power supply interface of the second voltage comparator is connected to the output terminal of the first voltage comparator, and the output terminal of the second voltage comparator is connected to the input terminal of the delay unit.

[0056] The non-inverting terminal of the third voltage comparator is connected to ground via a third reference voltage source. The output terminal of the third voltage comparator is connected between the negative power supply interface of the second voltage comparator and the output terminal of the first voltage comparator. The positive power supply interface of the third voltage comparator is connected to an auxiliary power supply device, and the negative power supply interface of the third voltage comparator is connected to ground.

[0057] Working Principle: This embodiment connects the detection terminals of the first, second, and third voltage comparison units together to sample the output voltage. Different functions are achieved by using different reference voltage values. The first voltage comparison unit controls the power supply to the second voltage comparison unit, ensuring that the second voltage comparison unit is not powered during the output voltage rise process, thus preventing false triggering of the power-down detection function. The second voltage comparison unit detects the output voltage to determine whether the output is powered down. If a power-down signal is detected, it sends a delay unit, which then outputs a pre-set fixed-time square wave to turn off the power enable. The third voltage comparison unit resets after detecting a decrease in output voltage, and the power enable becomes active again. The delay from output power-down to power-down is only on the order of 1 to 2 microseconds, enabling timely control of oscillations during the output voltage power-down process.

[0058] The other parts of this embodiment are the same as those in Embodiment 1 above, so they will not be described again.

[0059] Example 3:

[0060] This embodiment is based on any one of Embodiments 1-2 above, such as Figure 1 As shown, the specific structure of the first voltage comparison circuit is described with reference to a specific embodiment.

[0061] The first voltage comparison unit includes an operational amplifier U1, a diode D1, a resistor R3, and a capacitor C1;

[0062] One end of the diode D1 is connected to the output terminal of the operational amplifier U1, and the other end is connected to the input terminal of the resistor R3;

[0063] One end of the capacitor C1 is connected to the negative terminal of the first reference voltage source, and the other end is connected between the output terminal of the resistor R3 and the negative power supply interface of the second voltage comparison unit.

[0064] The positive power supply interface of the operational amplifier U1 is connected to the positive terminal of the output voltage, the non-inverting terminal of the operational amplifier U1 is connected between the negative terminal and the positive terminal of the output voltage, and the inverting terminal of the operational amplifier is connected to the positive output terminal of the first reference voltage source.

[0065] The anti-oscillation circuit for the power output voltage during the power-down process also includes a low-dropout chip U5. One end of the low-dropout chip U5 is connected between the positive terminal of the output voltage and the resistor R1, and the other end is connected to the positive power supply interface of the operational amplifier U1.

[0066] The anti-oscillation circuit for the power supply output voltage down-process also includes resistors R1 and R2;

[0067] One end of the resistor R1 is connected between the positive terminal of the output voltage and the positive power supply interface of the operational amplifier U1, and the other end of the resistor R1 is connected to the inverting input of the operational amplifier U2.

[0068] One end of the resistor R2 is connected between the resistor R1 and the inverting input of the operational amplifier U2, and the other end is connected between the negative terminal of the output voltage and the emitter of the transistor Q3.

[0069] Working principle: After the power enable terminal becomes high, the output voltage rises. The output voltage is regulated by the low dropout chip U5 and then supplies power to U1. At the same time, the output voltage is divided into a low voltage signal by a resistor and sent to the non-inverting input of operational amplifier U1. The first reference voltage of the inverting input of operational amplifier U1 is taken as the value of rated output voltage * 90% * R2 / (R1 + R2). When the output voltage rises to 90% of the rated voltage, the output terminal of operational amplifier U1 outputs a high level to supply power to operational amplifier U2. At this time, operational amplifier U2 starts to work. That is, operational amplifier U2 does not work before the output voltage rises to 90%. The rise process will not trigger the power failure detection function. Capacitor C1 is a filter energy storage capacitor, resistor R3 is a current limiting resistor, and diode D1 is for reverse power supply protection.

[0070] The other parts of this embodiment are the same as any one of the above embodiments 1-2, so they will not be described again.

[0071] Example 4:

[0072] This embodiment is based on any one of embodiments 1-3 above, such as Figure 1 As shown, the specific structure of the second voltage comparison unit is described with reference to a specific embodiment.

[0073] The second voltage comparison unit includes an operational amplifier U2 and a transistor Q2;

[0074] The inverting terminal of the operational amplifier U2 is connected between the positive and negative terminals of the output voltage. The non-inverting terminal of the operational amplifier U2 is connected to the positive output terminal of the second reference voltage source. The negative power supply interface of the operational amplifier U2 is connected between the negative terminal of the output voltage and the emitter of the transistor Q2. The positive power supply interface of the operational amplifier U2 is connected between the output terminal of the resistor R3 and the capacitor C1.

[0075] The base of transistor Q2 is connected to the output terminal of operational amplifier U2, and the collector of transistor Q2 is connected to the input terminal of delay circuit.

[0076] Working principle: The second reference voltage at the non-inverting input of operational amplifier U2 is determined by the value of rated output voltage * 80% * R2 / (R1 + R2). When the output voltage drops below 90% of the rated output voltage, operational amplifier U1 outputs a low level. Operational amplifier U2 is powered by energy storage capacitor C1. Diode D1 prevents capacitor C1 from discharging in reverse to the output of operational amplifier U1. When the output voltage continues to drop to 80% of the rated output voltage, the sampling voltage at the inverting input of operational amplifier U2 is lower than the voltage at the non-inverting input. The output changes from low to high level, driving transistor Q2 to work. This pulls the input of the delay circuit low to trigger the delay. The delay circuit outputs a high level for a fixed time, driving transistor Q3 to pull the power enable terminal low and turn off the power output.

[0077] The other parts of this embodiment are the same as any one of the above embodiments 1-3, so they will not be described again.

[0078] Example 5:

[0079] This embodiment is based on any one of embodiments 1-4 above, such as Figure 1 As shown, the structure of the third voltage comparison unit is illustrated with a specific embodiment.

[0080] The third voltage comparison unit includes an operational amplifier U3 and a transistor Q1;

[0081] The inverting terminal of the operational amplifier U3 is connected to the non-inverting terminal of the operational amplifier U1, the non-inverting terminal of the operational amplifier U3 is connected to the positive output terminal of the third reference voltage source, the positive power supply interface of the operational amplifier U3 is connected to the auxiliary power supply equipment, and the negative power supply interface of the operational amplifier U3 is connected to the ground terminal.

[0082] The base of transistor Q1 is connected to the output terminal of operational amplifier U3, the emitter of transistor Q1 is connected to the negative output terminal of the third voltage reference source, and the collector of transistor Q1 is connected between the positive power supply interface of operational amplifier U2 and the output terminal of resistor R3.

[0083] Working principle: The third reference voltage at the non-inverting input of operational amplifier U3 is taken as the value of rated output voltage * 10% * R2 / (R1 + R2). When the output voltage is lower than 10%, the output of operational amplifier U3 changes from low level to high level, causing transistor Q1 to start working and pull the power supply of operational amplifier U2 to low level. Power-off detection and reset.

[0084] The other parts of this embodiment are the same as any one of the embodiments 1-4 above, so they will not be described again.

[0085] Example 6:

[0086] This embodiment is based on any one of the embodiments 1-5 above, such as Figure 1 As shown, the structure of the delay unit is illustrated with a specific embodiment.

[0087] The delay unit includes a timer U4 and a transistor Q3;

[0088] The TRIG pin of the timer U4 is connected to the collector of the transistor Q2, the VCC pin of the timer U4 is connected to the auxiliary power supply, the GND pin of the timer U4 is connected to ground, and the OUTPUT pin of the timer U4 is connected to the base of the transistor Q3.

[0089] The collector of transistor Q3 is connected to the power enable terminal, and the emitter of transistor Q3 is connected to the negative terminal of the output voltage.

[0090] Working Principle: Operational amplifiers U1, U2, and U3 have their detection terminals connected together to sample the output voltage. Different reference voltage values ​​enable different functions. Operational amplifier U1 controls the power supply to operational amplifier U2, ensuring that U2 is not powered during the output voltage rise process, thus preventing false triggering of the power-down detection function. Operational amplifier U2 detects the output voltage to determine if the output is powered down. If a power-down signal is detected, it sends a signal to timer U4, which then outputs a pre-set fixed-time square wave to turn off the power enable. Operational amplifier U3 resets after detecting a decrease in output voltage, and the power enable becomes active again. The delay from output power-down to power-off is only in the range of 1-2 microseconds, enabling timely control of oscillations during the output voltage power-down process.

[0091] The other parts of this embodiment are the same as any one of the above embodiments 1-5, so they will not be described again.

[0092] Example 7:

[0093] This embodiment is based on any one of embodiments 1-6 above, such as Figure 2 , Figure 3 As shown, the output voltage energization process is illustrated using a specific embodiment.

[0094] Working principle: The discharge time varies depending on the energy storage device and load size at the output end. If the time for the output voltage to discharge from 80% to 10% (reset point) is greater than the fixed delay time designed by the delay circuit, then the total shutdown time of the power enable terminal is the time for the output voltage to discharge from 80% to 10% (reset point). If the time for the output voltage to discharge from 80% to 10% (reset point) is less than the fixed delay time designed by the delay circuit, then the total shutdown time of the output is the fixed delay time, ensuring that the output has a fixed shutdown time.

[0095] The other parts of this embodiment are the same as any one of the embodiments 1-6 above, so they will not be described again.

[0096] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Any simple modifications or equivalent changes made to the above embodiments based on the technical essence of the present utility model shall fall within the protection scope of the present utility model.

Claims

1. An anti-hunting circuit for a power supply output voltage down process, characterized by, Includes a voltage comparison unit and a delay unit; The voltage comparison unit receives and outputs voltage at its input terminal, and its output terminal is connected to the input terminal of the delay unit. The output terminal of the delay unit is connected to the power enable terminal; The voltage comparison unit first samples the output voltage and generates a first detection signal based on the set first reference voltage and output voltage; then, based on the first detection signal, it controls the power-on process to prevent triggering the power-off detection. Then, based on the output voltage and the set second reference voltage, a second detection signal is generated to detect whether the output voltage is powered down, and a power-down output signal is generated; finally, based on the output voltage and the set third reference voltage, a third detection signal is generated to detect whether the output voltage is powered down, and if the output voltage is powered down, the system is reset. The delay unit is used to generate a fixed-time square wave to turn off the power enable based on the acquired power-down output signal.

2. The anti-hunting circuit for power supply output voltage down process according to claim 1, wherein, The voltage comparison unit includes a first voltage comparison unit, a second voltage comparison unit, a third voltage comparison unit, a first reference voltage source, a second reference voltage source, and a third reference voltage source; The non-inverting input of the first voltage comparator is connected to the inverting input of the third voltage comparator. The inverting input of the first voltage comparator is connected to ground through the first reference voltage source. The output of the first voltage comparator is connected to the positive power supply interface of the second voltage comparator. The positive power supply interface of the first voltage comparator is connected to the positive terminal of the output voltage. The negative power supply interface of the first voltage comparator is connected to ground. The inverting terminal of the second voltage comparator is connected to the positive terminal of the output voltage, the non-inverting terminal of the second voltage comparator is connected to ground through the second reference voltage source, the positive power supply interface of the second voltage comparator is connected to the output terminal of the first voltage comparator, and the output terminal of the second voltage comparator is connected to the input terminal of the delay unit. The non-inverting terminal of the third voltage comparator is connected to ground via a third reference voltage source. The output terminal of the third voltage comparator is connected between the negative power supply interface of the second voltage comparator and the output terminal of the first voltage comparator. The positive power supply interface of the third voltage comparator is connected to an auxiliary power supply device, and the negative power supply interface of the third voltage comparator is connected to ground.

3. The anti-hunting circuit for power supply output voltage down process according to claim 2, wherein, The first voltage comparison unit includes an operational amplifier U1, a diode D1, a resistor R3, and a capacitor C1; One end of the diode D1 is connected to the output terminal of the operational amplifier U1, and the other end is connected to the input terminal of the resistor R3; One end of the capacitor C1 is connected to the negative terminal of the first reference voltage source, and the other end is connected between the output terminal of the resistor R3 and the negative power supply interface of the second voltage comparison unit. The positive power supply interface of the operational amplifier U1 is connected to the positive terminal of the output voltage, the non-inverting terminal of the operational amplifier U1 is connected between the negative terminal and the positive terminal of the output voltage, and the inverting terminal of the operational amplifier is connected to the positive output terminal of the first reference voltage source.

4. The anti-hunting circuit for power supply output voltage down process according to claim 3, wherein, The second voltage comparison unit includes an operational amplifier U2 and a transistor Q2; The inverting terminal of the operational amplifier U2 is connected between the positive and negative terminals of the output voltage. The non-inverting terminal of the operational amplifier U2 is connected to the positive output terminal of the second reference voltage source. The negative power supply interface of the operational amplifier U2 is connected between the negative terminal of the output voltage and the emitter of the transistor Q2. The positive power supply interface of the operational amplifier U2 is connected between the output terminal of the resistor R3 and the capacitor C1. The base of transistor Q2 is connected to the output terminal of operational amplifier U2, and the collector of transistor Q2 is connected to the input terminal of delay circuit.

5. The anti-hunting circuit for power supply output voltage down process according to claim 4, wherein, The third voltage comparison unit includes an operational amplifier U3 and a transistor Q1; The inverting terminal of the operational amplifier U3 is connected to the non-inverting terminal of the operational amplifier U1, the non-inverting terminal of the operational amplifier U3 is connected to the positive output terminal of the third reference voltage source, the positive power supply interface of the operational amplifier U3 is connected to the auxiliary power supply equipment, and the negative power supply interface of the operational amplifier U3 is connected to the ground terminal. The base of transistor Q1 is connected to the output terminal of operational amplifier U3, the emitter of transistor Q1 is connected to the negative output terminal of the third voltage reference source, and the collector of transistor Q1 is connected between the positive power supply interface of operational amplifier U2 and the output terminal of resistor R3.

6. The anti-hunting circuit for power supply output voltage down process according to claim 5, wherein, The delay unit includes a timer U4 and a transistor Q3; The TRIG pin of the timer U4 is connected to the collector of the transistor Q2, the VCC pin of the timer U4 is connected to the auxiliary power supply, the GND pin of the timer U4 is connected to ground, and the OUTPUT pin of the timer U4 is connected to the base of the transistor Q3. The collector of transistor Q3 is connected to the power enable terminal, and the emitter of transistor Q3 is connected to the negative terminal of the output voltage.

7. The anti-hunting circuit for power supply output voltage down process according to claim 6, wherein, The anti-oscillation circuit for the power supply output voltage down-process also includes resistors R1 and R2; One end of the resistor R1 is connected between the positive terminal of the output voltage and the positive power supply interface of the operational amplifier U1, and the other end of the resistor R1 is connected between the non-inverting input of the operational amplifier U1 and the inverting input of the operational amplifier U2. One end of the resistor R2 is connected between the resistor R1 and the inverting input of the operational amplifier U2, and the other end is connected between the negative terminal of the output voltage and the emitter of the transistor Q3.

8. The anti-hunting circuit for power supply output voltage down process according to claim 7, wherein, The anti-oscillation circuit for the power output voltage during the power-down process also includes a low-dropout chip U5; One end of the low-dropout chip U5 is connected between the positive terminal of the output voltage and the resistor R1, and the other end is connected to the positive power supply interface of the operational amplifier U1.

9. The anti-hunting circuit for power supply output voltage down process according to claim 6, wherein, The timer U4 is an SE555 chip.

10. An anti-oscillation circuit for the power supply output voltage during the power-down process according to claim 8, characterized in that, The low dropout chip U5 is an LDO chip.

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