Circuit board structure
By introducing an anti-plating layer and a fine drilling process into the circuit board structure, the signal problems caused by the increase in branch length were solved, achieving higher signal integrity and transmission performance, while reducing process complexity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-07
- Publication Date
- 2026-04-03
AI Technical Summary
When increasing the line density and number of layers in existing circuit board structures, the length of the branches in the connection structure increases, leading to problems such as signal reflection, short circuits, and signal delays, making it difficult to meet the high-performance requirements of electronic products.
Introducing a resist coating into the circuit board structure defines the boundary between conductive structures and branches, reduces branch length, and improves the positioning accuracy of the drilling process. An additional drilling process is used to remove unnecessary conductive material, forming via and through-hole structures.
It effectively reduces branch length, improves signal integrity and transmission, reduces process complexity, and improves the accuracy of drilling process.
Smart Images
Figure CN224083770U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to circuit board structures, and more particularly to a circuit board structure with an anti-plating coating. Background Technology
[0002] With the widespread use of electronic products, higher performance is required. For example, to achieve thinner and smaller designs, the circuit density and number of layers in electronic products must be increased. However, increasing circuit density and the number of layers poses a significant challenge to controlling electrical performance. Therefore, although existing circuit board structures have gradually met their intended uses, they are not perfect in every aspect. Thus, there is still a need to develop new circuit board structures. Utility Model Content
[0003] According to some embodiments, a circuit board structure is provided. The circuit board structure includes a first stack, a second stack, a resist layer, a via structure, and a through-hole structure. The first stack has a first dielectric layer and a first circuit layer. The second stack is disposed on the first stack, wherein the second stack has a second dielectric layer and a second circuit layer. The resist layer is disposed between the first circuit layer and the second circuit layer. The via structure is disposed in the first stack and electrically connected to the first circuit layer. The through-hole structure is disposed in the second stack and the resist layer, wherein the through-hole structure is directly connected to the via structure and electrically insulated from the via structure.
[0004] In some embodiments, the first stack has a first sidewall exposed from a via structure, the via structure including a conductive material, and the conductive material disposed on the first sidewall.
[0005] In some embodiments, the resist coating has a second sidewall exposed from the through-hole structure, and the conductive material has a side surface away from the first sidewall, and the side surface is not coplanar with the second sidewall.
[0006] In some embodiments, the first sidewall and the second sidewall are coplanar.
[0007] In some embodiments, the second stack has a third sidewall exposed from a through-hole structure, the through-hole structure including a conductive material, and the conductive material is disposed on the third sidewall adjacent to the resist layer.
[0008] In some embodiments, the resist coating has a second sidewall exposed from the through-hole structure, and the conductive material has a side surface away from the third sidewall, and the side surface is not coplanar with the second sidewall.
[0009] In some embodiments, the via structure has a first width, the through-hole structure has a second width, and the first width is smaller than the second width.
[0010] In some embodiments, the through-hole structure further has a third width, and the first width is equal to the third width.
[0011] In some embodiments, the first stack further includes a third dielectric layer, and the second stack further includes a fourth dielectric layer.
[0012] In some embodiments, the two ends of the via structure penetrate the first stack.
[0013] The circuit board structure of this invention can be applied to various types of electronic devices. To make the components and advantages of this invention more apparent and understandable, various embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Attached Figure Description
[0014] When with attachment Figure 1 This invention can be more fully understood from the following detailed description. It is worth noting that, in accordance with industry standard practice, the components are not drawn to scale. In fact, for clarity, the dimensions of each component can be arbitrarily enlarged or reduced.
[0015] Figures 1 to 6 These are cross-sectional schematic diagrams showing different stages of the manufacturing process of the circuit board structure according to some embodiments of the present invention. Detailed Implementation
[0016] The following provides a detailed description of the apparatus according to various embodiments of the present invention. It should be understood that the following description provides many different embodiments for implementing various forms of some embodiments of the present invention. The specific elements and arrangements described below are merely for simple and clear description of some embodiments of the present invention. Of course, these are only examples and not limitations on the present invention. Furthermore, similar and / or corresponding element symbols may be used in different embodiments to identify similar and / or corresponding elements for clear description of the present invention. However, the use of these similar and / or corresponding element symbols is only for simple and clear description of some embodiments of the present invention and does not represent any relationship between the different embodiments and / or structures discussed.
[0017] Furthermore, it should be understood that the ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify elements, are not intended to imply any prior ordinal number representing the (or plurality of) elements, nor to represent the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another with the same name. The claims and specification may not use the same terminology; for example, a first element in the specification may be a second element in the claims.
[0018] In some embodiments of this utility model, terms such as "connect," "interconnect," and "bond," unless specifically defined, may refer to two structures in direct contact, or to two structures not in direct contact, with other structures disposed between them. Furthermore, these terms may include situations where both structures are movable or both are fixed. Additionally, the terms "electrical connection" or "electrical coupling" include any direct or indirect electrical connection means.
[0019] In this text, the terms "approximately," "about," and "substantially" typically indicate that a given value or range is within 10%, 5%, 3%, 2%, 1%, or 0.5%. The given quantity is an approximate quantity; that is, even without specific mention of "approximately," "about," or "substantially," the meaning of "approximately," "about," or "substantially" is implied. The phrase "the range is between the first value and the second value" indicates that the range includes the first value, the second value, and other values in between. Furthermore, any two values or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies an error within approximately 10%, 5%, 3%, 2%, 1%, or 0.5% between the first and second values. If the first direction is perpendicular to the second direction, the angle between the first and second directions may be between 80 and 100 degrees. If the first direction is parallel to the second direction, then the angle between the first direction and the second direction can be between 0 degrees and 10 degrees.
[0020] It should be understood that, without departing from the spirit of this utility model, the components in the various embodiments described below can be replaced, reorganized, or combined to complete other embodiments. Components in each embodiment can be arbitrarily combined and used as long as they do not violate the spirit of the utility model or conflict with it.
[0021] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art. It is understood that such terms, for example, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in embodiments of this invention.
[0022] With the pursuit of portability and lightweight design, the size of electronic products continues to shrink. Furthermore, to meet the demands of High Performance Computing (HPC), the number of components in electronic products has increased significantly. Therefore, to achieve miniaturization and increase component count, the circuit density and number of layers in printed circuit boards (PCBs) need to be greatly increased. However, this significant increase in circuit density and layer count also creates more unnecessary branches in the interlayer connections (e.g., vias) of the PCB, and these branches do not have a specific function (e.g., signal transmission). In some cases, the presence of branches may cause signal reflection, thus affecting signal integrity and transmission performance. Even worse, branches may cause short circuits or signal delays.
[0023] Therefore, current practices typically employ back-drilling technology to reduce stub length and minimize the impact of stubs. Furthermore, this invention provides a circuit board structure that utilizes an additional anti-plating layer to significantly reduce stub length. This more effectively reduces the impact of stubs on electronic products.
[0024] Reference Figures 1 to 6 These figures are cross-sectional schematic diagrams showing different stages of the manufacturing process of the circuit board structure according to some embodiments of the present invention. It is worth noting that, for the sake of simplicity and ease of understanding, the dimensions of components and the proportions between them may be exaggerated in the figures. Furthermore, some components in the circuit board structure may be omitted in the figures, but those skilled in the art will understand that the circuit board structure may also include other common components. For example, the circuit board structure of the present invention may also include various active components, passive components, heat dissipation components, connectors, and / or protective layers, etc., not shown in the figures.
[0025] like Figure 1As shown, a plurality of stacked layers 10 are provided. In this invention, each stacked layer 10 may include a dielectric layer 100 and a circuit layer 101, and the circuit layer 101 may be disposed on one or both surfaces of the dielectric layer 100. In some embodiments, the material of the dielectric layer 100 may include polymeric materials, fibrous materials, other suitable materials, or combinations thereof, but this invention is not limited thereto. For example, polymeric materials may include epoxy resin, polyimide (PI), polypropylene (PP), other suitable polymeric materials, or combinations thereof, but this invention is not limited thereto. For example, fibrous materials may include carbon fiber, glass fiber, other suitable fibrous materials, or combinations thereof, but this invention is not limited thereto.
[0026] In some embodiments, a circuit layer 101 with a specific pattern can be formed on the dielectric layer 100 by a combination of deposition, photolithography, and etching processes. The deposition process is used to deposit conductive and masking materials on the dielectric layer 100, while the photolithography and etching processes are used to pattern the conductive and masking materials. In some embodiments, the conductive material may be aluminum (Al), copper (Cu), their alloys, or compounds, but the present invention is not limited thereto. For example, copper alloys or compounds may include brass, phosphor bronze, beryllium copper alloy, or oxygen-free copper, but the present invention is not limited thereto. In some embodiments, the masking material may include silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, photoresist, other suitable materials, or combinations thereof, but the present invention is not limited thereto.
[0027] In some embodiments, the deposition process may include electroplating, chemical plating, physical vapor deposition (PVD), chemical vapor deposition (CVD), other suitable processes, or combinations thereof, but the present invention is not limited thereto. In some embodiments, the photolithography process may include photoresist application (e.g., spin-on coating, lamination), soft baking, mask alignment, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof, but the present invention is not limited thereto. In some embodiments, the etching process may include dry etching, wet etching, other suitable etching, or combinations thereof, but the present invention is not limited thereto.
[0028] like Figure 2 As shown, following the steps described above, a resist layer 11 is provided between the two stacked layers 10. Specifically, the resist layer 11 is located between adjacent circuit layers 101 of the two stacked layers 10. In some embodiments, the resist layer 11 may include a material with properties significantly different from those of the metal (e.g., lattice constant, bonding, coefficient of thermal expansion, etc.) to prevent the metal from adhering to it in subsequent plating processes. For example, the resist material may include photoresist, plating resist ink, liquid solder mask, other suitable materials, or combinations thereof, but the present invention is not limited thereto. In some embodiments, the resist layer 11 may be formed by a coating process such as spraying or brushing, other suitable processes, or combinations thereof, but the present invention is not limited thereto. In some embodiments, the resist layer 11 may directly contact any one or both of the two adjacent circuit layers 101, but the present invention is not limited thereto. In other embodiments, the resist layer 11 may not contact the circuit layers 101 at all.
[0029] Following the steps described above, a dielectric layer 12 is formed between two adjacent stacked layers 10, and the dielectric layer 12 covers the sidewalls of the resist layer 11. In some embodiments, the material of the dielectric layer 12 may be epoxy resin, polyimide (PI), build-up material (ABF), other suitable polymer materials, or combinations thereof, but the present invention is not limited thereto. In some embodiments, the dielectric layer 12 may be formed by lamination, coating, other suitable processes, or combinations thereof, but the present invention is not limited thereto.
[0030] Following the steps described above, a circuit layer 13 is formed on the dielectric layer 12. In some embodiments, the circuit layer 13 may be or may include a conductive material. For example, the conductive material may be aluminum (Al), copper (Cu), their alloys, or compounds thereof, but the present invention is not limited thereto. In some embodiments, the material of the circuit layer 13 may be the same as or different from the material of the circuit layer 101, depending on design requirements. In some embodiments, a circuit layer 13 with a specific pattern can be formed on the dielectric layer 12 by a combination of deposition, photolithography, and etching processes. Detailed descriptions can be found above and will not be repeated here.
[0031] like Figure 3 As shown, following the above steps, a first drilling process DP1 is performed to form a first through hole 14 in the plurality of stacks 10. Specifically, the first through hole 14 formed by the first drilling process DP1 penetrates the plurality of stacks 10, the resist layer 11, and the dielectric layer 12. In some embodiments, the first drilling process DP1 may include mechanical drilling, laser drilling, other suitable processes, or combinations thereof, but the present invention is not limited thereto. In some embodiments, the first drilling process DP1 may also form a blind via (not shown) instead of forming a first through hole 14. In this case, one end of the formed blind via is embedded in the plurality of stacks 10, while the other end is exposed to the outside from the stacks 10 or the dielectric layer 12.
[0032] like Figure 4 As shown, following the steps described above, a plating process is performed to form a conductive material 15 in the first through-hole 14. Due to the nature of the resist plating layer 11, the conductive material 15 does not cover the sidewalls of the resist plating layer 11 exposed from the first through-hole 14. Specifically, the conductive material 15 covers the sidewalls of the stack 10 exposed from the first through-hole 14, and also covers the sidewalls of the dielectric layer 12 exposed from the first through-hole 14. In other words, by using the resist plating layer 11 provided in the aforementioned steps, the conductive material 15 can be selectively plated at specific locations in the first through-hole 14.
[0033] In this invention, the resist coating 11 can be used to define the portions of the through-hole that require electrical connection (i.e., those serving as conductive structures) and the portions that do not require electrical connection (i.e., branches that do not serve as conductive structures). Compared to prior art circuit board structures that do not use the resist coating 11, this invention uses the resist coating 11 to more precisely define the boundary between conductive structures and branches, thereby effectively reducing branch length (or even completely eliminating the existence of branches). In addition, because the resist coating 11 is easy to install, it can further improve the positioning accuracy of subsequent drilling processes without significantly increasing process complexity.
[0034] It is worth mentioning that, although Figure 4 The illustration shows an embodiment where the conductive material 15 partially fills the first through-hole 14 (i.e., a gap or channel remains in the center of the first through-hole 14), but the present invention is not limited thereto. In other embodiments, the conductive material 15 may completely fill the first through-hole 14, leaving no gap in the center of the first through-hole 14. Alternatively, in yet another embodiment, the conductive material 15 may partially fill the first through-hole 14, and the first through-hole 14 may be further filled by providing a dielectric material such as an advance layer material (ABF) (not shown), leaving no gap in the center of the first through-hole 14.
[0035] like Figure 5 As shown, following the above steps, a second drilling process DP2 is performed to form a second through-hole 16 at a portion of the first through-hole 14. Specifically, the second through-hole 16 formed by the second drilling process DP2 penetrates multiple stacks 10 and dielectric layers 12, and removes a portion of the first through-hole 14 and the conductive material 15 located in these first through-holes 14. In some embodiments, the second drilling process DP2 may include mechanical drilling, laser drilling, other suitable processes, or combinations thereof, but the present invention is not limited thereto. In some embodiments, the axial direction (i.e., the extension direction) of the first through-hole 14 may substantially overlap with the axial direction of the second through-hole 16. In other words, the first through-hole 14 and the second through-hole 16 penetrate multiple stacks 10 and dielectric layers 12 along the same axis. However, the present invention is not limited thereto. In some cases, the axial direction (i.e., the extension direction) of the first through-hole 14 may be spaced at a specific distance from the axial direction of the second through-hole 16. This specific distance may be due to process errors or design requirements.
[0036] It is worth mentioning that in this step, the removed conductive material 15 is a branch not used for electrical connection, while the remaining conductive material 15 is a connection structure used for electrical connection. In other words, this invention removes unnecessary conductive material 15 through the second drilling process DP2, thereby reducing the branch length or completely eliminating the existence of the branch. In some embodiments, the anti-plating layer 11 can be used as a boundary or positioning element of the second drilling process DP2, and the conductive material 15 located on one side (e.g., the upper side) of the anti-plating layer 11 is removed, leaving the conductive material 15 located on the other side (e.g., the lower side) of the anti-plating layer 11. Figure 5 In the illustrated embodiment, the second drilling process DP2 removes the conductive material 15 above the resist coating 11, leaving the conductive material 15 below the resist coating 11. However, the present invention is not limited thereto. In other embodiments, the second drilling process DP2 may also remove the conductive material 15 below the resist coating 11, leaving the conductive material 15 above the resist coating 11.
[0037] After the above-described process, this utility model yields a circuit board structure 1. For ease of understanding and differentiation of components, the following description will use the following description... Figure 6 In this context, the first through-hole 14 located below the resist coating 11 and the conductive material 15 located therein can be collectively referred to as the via structure VS, and this via structure VS is used to electrically connect different circuit layers in the vertical direction. In this case, the stack 10 and dielectric layer 12 through which the via structure VS passes can be further referred to as the first stack 10A, the dielectric layer 100 in the first stack 10A is referred to as the first dielectric layer 100A, the circuit layer 101 in the first stack 10A is referred to as the first circuit layer 101A, and the dielectric layer 12 in the first stack 10A is referred to as the third dielectric layer 12A.
[0038] In addition, the first through-hole 14 at the same horizontal height as the resist coating 11 and the second through-hole 16 located above the resist coating 11 can be collectively referred to as the through-hole structure TS, and this through-hole structure TS is not used to electrically connect different circuit layers in the vertical direction. In this case, the stack 10 and dielectric layer 12 through which the through-hole structure TS passes can be further referred to as the second stack 10B, the dielectric layer 100 in the second stack 10B is referred to as the second dielectric layer 100B, the circuit layer 101 in the second stack 10B is referred to as the second circuit layer 101B, and the dielectric layer 12 in the second stack 10B is referred to as the fourth dielectric layer 12B.
[0039] As mentioned above, Figure 6As shown, the circuit board structure 1 includes a first stack 10A, a second stack 10B, a resist layer 11, a via structure VS, and a through-hole structure TS. The first stack 10A has a first dielectric layer 100A, a third dielectric layer 12A, and a first circuit layer 101A. The second stack 10B is disposed on the first stack 10A, and includes a second dielectric layer 100B, a fourth dielectric layer 12B, and a second circuit layer 101B. The resist layer 11 is disposed between the first circuit layer 101A and the second circuit layer 101B. The via structure VS is disposed in the first stack 10A and electrically connected to the first circuit layer 101A. The through-hole structure TS is disposed in the second stack 10B and the resist layer 11, wherein the through-hole structure TS is directly connected to the via structure VS and electrically insulated from the via structure VS.
[0040] In some embodiments, when the second drilling process DP2 has completely removed the conductive material 15 above the resist coating 11, there is substantially no residual conductive material 15 in the through-hole. In this case, refer to Figure 6 The left half of the structure includes a first stack 10A having a first sidewall SW1 exposed from a via structure VS, the via structure VS including a conductive material 15 disposed on the first sidewall SW1. In some embodiments, the resist layer 11 has a second sidewall SW2 exposed from a through-hole structure TS, the conductive material 15 having a side surface SS away from the first sidewall SW1, and the side surface SS not being coplanar with the second sidewall SW2. More specifically, the side surface SS protrudes horizontally from the second sidewall SW2, and the thickness of the protrusion is equal to the thickness of the conductive material 15. In some embodiments, the first sidewall SW1 and the second sidewall SW2 are coplanar.
[0041] In some embodiments, when the second drilling process DP2 does not completely remove the conductive material 15 above the resist coating 11, there may be trace amounts of residual conductive material 15 in the through-hole. In this case, refer to Figure 6 The right half of the structure includes a second stack 10B having a third sidewall SW3 exposed from a via structure TS. The via structure TS includes a conductive material 15 disposed on the third sidewall SW3 and adjacent to the resist layer 11. In some embodiments, the resist layer 11 has a second sidewall SW2 exposed from the via structure TS, and the remaining conductive material 15 has a side surface SS away from the third sidewall SW3, and the side surface SS is not coplanar with the second sidewall SW2. More specifically, the side surface SS protrudes horizontally from the second sidewall SW2, and the thickness of the protrusion is equal to the thickness of the remaining conductive material 15.
[0042] In some embodiments, the via structure VS has a first width W1, and the through-hole structure TS has a second width W2, wherein the first width W1 is smaller than the second width W2. In some embodiments, the through-hole structure TS may have the following characteristics: Figure 6 The funnel shape is shown. In this case, the through-hole structure TS can have multiple widths, such as a second width W2 and a third width W3. The second width W2, located furthest from the guide hole structure VS, can be the maximum width of the through-hole structure TS, which is greater than the first width W1 of the guide hole structure VS. Conversely, the third width W3, located adjacent to the guide hole structure VS, can be the minimum width of the through-hole structure TS, which is equal to the first width W1 of the guide hole structure VS. It is worth noting that in this paper, the width of the guide hole structure VS refers to the distance between the first sidewalls SW1, while the width of the through-hole structure TS refers to the distance between the second sidewalls SW2 or the distance between the third sidewalls SW3.
[0043] In some embodiments, the two ends of the via structure VS respectively penetrate the first stack 10A, but the present invention is not limited thereto. As mentioned above, in some embodiments, the via structure VS can be a blind via, with one end connected to the through-hole structure TS, and the other end embedded in the first stack 10A.
[0044] In summary, this utility model provides a circuit board structure that employs an additional anti-plating layer to significantly reduce branch length. Specifically, the anti-plating layer can be used to define the portions of vias that require electrical connection (i.e., those serving as conductive structures) and those that do not (i.e., branches that do not serve as conductive structures), thereby more effectively reducing branch length (or even completely eliminating the existence of branches) during the drilling process. Furthermore, due to the simple application method of the anti-plating layer, it can further improve the positioning accuracy of the drilling process without significantly increasing process complexity.
[0045] The above outlines several embodiments to enable those skilled in the art to better understand the viewpoints of the present invention. Those skilled in the art should understand that other processes and structures can be designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.
[0046] [Symbol Explanation]
[0047] 1: Circuit board structure
[0048] 10: Stacking
[0049] 10A: First stack
[0050] 10B: Second stack
[0051] 100: Dielectric layer
[0052] 100A: First dielectric layer
[0053] 100B: Second dielectric layer
[0054] 101: Line Layer
[0055] 101A: First Line Layer
[0056] 101B: Second Line Layer
[0057] 11: Anti-coating
[0058] 12: Dielectric layer
[0059] 12A: Third dielectric layer
[0060] 12B: Fourth dielectric layer
[0061] 13: Line Layer
[0062] 14: First through hole
[0063] 15: Conductive materials
[0064] 16: Second through hole
[0065] DP1: First Drilling Process
[0066] DP2: Second drilling process
[0067] SS: Side surface
[0068] SW1: First sidewall
[0069] SW2: Second sidewall
[0070] SW3: Third sidewall
[0071] TS: Through-hole structure
[0072] VS: Guide hole structure
[0073] W1: First width
[0074] W2: Second width
[0075] W3: Third width.
Claims
1. A circuit board structure, characterized by, The first stack has a first dielectric layer and a first circuit layer. The second stack is disposed on the first stack, wherein the second stack has a second dielectric layer and a second circuit layer. A barrier layer is disposed between the first circuit layer and the second circuit layer. A via structure is disposed in the first stack and electrically connected to the first circuit layer. A through-hole structure is disposed in the second stack and the barrier layer, wherein the through-hole structure is directly connected to the via structure and electrically insulated from the via structure. The first stack has a first sidewall exposed from the via structure, the via structure includes a conductive material, and the conductive material is disposed on the first sidewall. The barrier layer has a second sidewall exposed from the through-hole structure, the conductive material has a side surface away from the first sidewall, and the side surface is not coplanar with the second sidewall.
2. The circuit board structure according to claim 1, characterized by The first sidewall is coplanar with the second sidewall.
3. The circuit board structure according to claim 2, characterized by The second stack has a third sidewall exposed from the through-hole structure, the through-hole structure includes a conductive material, and the conductive material is disposed on the third sidewall and adjacent to the barrier layer.
4. The circuit board structure according to claim 3, characterized by The barrier layer has a second sidewall exposed from the through-hole structure, the conductive material has a side surface away from the third sidewall, and the side surface is not coplanar with the second sidewall.
5. The circuit board structure of claim 1, wherein The via structure has a first width, the through-hole structure has a second width, and the first width is less than the second width.
6. The circuit board structure according to claim 5, characterized by The through-hole structure also has a third width, and the first width is equal to the third width.
7. The circuit board structure of claim 1, wherein The first stack further includes a third dielectric layer, and the second stack further includes a fourth dielectric layer.
8. The circuit board structure according to claim 7, characterized by Both ends of the via structure pass through the first stack.
9. The circuit board structure of claim 1, wherein 10. The circuit board structure of claim 1, wherein