High-voltage-withstanding groove type MOSFET (metal oxide semiconductor field effect transistor) structure

Abstract

The utility model discloses a high withstand voltage trench type MOSFET structure, which comprises an N + substrate, an N-drift region, a P type base region, source electrode metal and drain electrode metal, the P type base region is provided with a trench gate structure, and the bottom of the trench gate structure is connected with the N-drift region through an N type region; two sides, corresponding to the trench gate structure, of the upper part of the P-type base region are respectively provided with an N + source region, and one side, far away from the trench gate structure, of the N + source region is provided with a P + region; and the upper end of the trench gate structure is covered with an interlayer dielectric layer. In the utility model, the P-type base region completely wraps the trench gate structure, and the N-type region is formed at the bottom of the trench to realize the connection of the trench gate structure and the N-drift region, so that the gate leakage charge can be reduced, the switching speed can be improved, and the electric field at the bottom of the trench can be reduced, thereby effectively protecting the gate oxide layer and improving the reliability.

Description

Technical Field

[0001] This invention belongs to the field of power devices, and in particular relates to a high-voltage trench MOSFET structure. Background Technology

[0002] Trench MOSFETs are important power devices used in DC-DC converters, voltage regulators, power management modules, electromechanical control, display control, and automotive electronics. Compared to planar MOSFETs, trench MOSFETs not only eliminate the JFET effect and reduce internal impedance to bring the on-resistance closer to the ideal value, but also reduce cell size and increase cell density, thereby increasing current density and effectively saving chip area. With the increasing demands on the frequency characteristics of power devices in modern circuits, minimizing the characteristic on-resistance and gate-drain charge of trench MOSFETs under a given breakdown voltage is a primary design objective.

[0003] Please see Figure 1 In traditional trench MOSFET structures, the thickness of the P-type base region 120 is relatively small, and the trench 210 typically penetrates the P-type base region 120 and extends into the N-drift region 120. In this case, the introduction of the trench 210 leads to electric field concentration at the corners of the gate oxide layer 220, which can easily cause gate oxide layer 220 breakdown, resulting in serious reliability issues. Furthermore, traditional trench MOSFETs have a relatively long conduction channel length and a large on-resistance, leaving considerable room for improvement to reach the ideal on-resistance. Utility Model Content

[0004] In view of the shortcomings of the prior art, the technical problem to be solved by this utility model is to provide a high-voltage trench MOSFET structure.

[0005] To solve the above-mentioned technical problems, this utility model provides the following technical solution:

[0006] A high-voltage trench MOSFET structure includes an N+ substrate, an N- drift region, and a P-type base region arranged sequentially from bottom to top. The P-type base region has a trench gate structure, and the bottom of the trench gate structure is connected to the N- drift region through an N-type region. An N+ source region is respectively disposed on the upper part of the P-type base region corresponding to both sides of the trench gate structure, and a P+ region is disposed on the side of the N+ source region away from the trench gate structure. An interlayer dielectric layer covers the upper end of the trench gate structure, and source metal is disposed at the upper ends of the interlayer dielectric layer, the N+ source region, and the P+ region. A drain metal is disposed at the lower end of the N+ substrate.

[0007] Furthermore, the N+ substrate is heavily N-type doped; the N- drift region is lightly N-type doped; the P-type base region is P-type doped; the N-type region is N-type doped; the N+ source region is heavily N-type doped; and the P+ region is heavily P-type doped.

[0008] Furthermore, the thickness of the P-type base region is 2μm to 3μm.

[0009] Furthermore, the thickness of the N+ source region is greater than the thickness of the P+ region.

[0010] Furthermore, the P-type base regions on both sides of the trench grid structure form a platform region, and the two ends of the interlayer dielectric layer extend horizontally outward to above the platform region.

[0011] Furthermore, the width of the N-type region is less than the width of the interlayer dielectric layer, and greater than or equal to the width of the trench.

[0012] Furthermore, the trench gate structure includes a trench formed in the P-type body region, a gate oxide layer formed on the trench wall, and a gate filled in the trench.

[0013] Furthermore, the gate oxide layer includes a bottom gate oxide layer formed at the bottom of the trench and a sidewall gate oxide layer formed on the sidewall of the trench, wherein the thickness of the bottom gate oxide layer is greater than the thickness of the sidewall gate oxide layer.

[0014] Furthermore, the thickness of the sidewall gate oxide layer is 400 Å to 600 Å, and the thickness of the bottom gate oxide layer is 2000 Å to 5000 Å thicker than the thickness of the sidewall gate oxide layer.

[0015] Furthermore, the depth of the trench is 0.9 μm to 1.5 μm.

[0016] In this invention, by increasing the thickness of the P-type base region, the P-type base region can completely enclose the trench gate structure; simultaneously, an N-type region is formed at the bottom of the trench to connect the trench gate structure and the N-drift region. This not only reduces gate leakage charge and improves switching speed but also reduces the electric field at the bottom of the trench, thereby effectively protecting the gate oxide layer and improving reliability. Thickening the gate oxide layer at the bottom of the trench can further improve the reliability of the gate oxide layer at this point, thus making the device more reliable. In addition, by increasing the depth of the N+ source region, the length of the formed conductive channel can be shortened, thereby reducing the resistance of the conductive channel. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0018] Figure 1This is a schematic diagram of the structure of a trench MOSFET in current technology.

[0019] Figure 2 This is a schematic diagram of an embodiment of a high-voltage trench MOSFET structure according to the present invention.

[0020] The diagrams in the instruction manual are labeled as follows:

[0021] N+ substrate - 100; N- drift region - 110; P-type base region - 120; N+ source region - 130; P+ region - 140; N-type region - 150; trench - 210; gate oxide layer - 220; bottom gate oxide layer - 221; sidewall gate oxide layer - 222; gate - 230; interlayer dielectric layer - 300; source metal - 400; drain metal - 500. Detailed Implementation

[0022] The following specific examples illustrate the implementation of this utility model. The illustrations provided in the following embodiments are only schematic representations of the basic concept of this utility model. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0023] Please see Figure 2 , Figure 2 This is a schematic diagram of an embodiment of a high-voltage trench MOSFET structure according to the present invention. The high-voltage trench MOSFET structure of this embodiment includes, from bottom to top, an N+ substrate 100, an N- drift region 110, and a P-type base region 120. The N+ substrate 100 is heavily N-type doped, the N- drift region 110 is lightly N-type doped, and the P-type base region 120 is P-type doped. In this embodiment, the P-type base region 120 is formed epitaxially on the N- drift region 110, thereby significantly increasing the thickness of the P-type base region 120, which is 2μm to 3μm.

[0024] An N+ source region 130 is respectively disposed on both sides of the upper part of the P-type base region 120 corresponding to the trench gate structure. A P+ region 140 is disposed on the side of the N+ source region 130 away from the trench gate structure. The N+ source region 130 is heavily N-type doped, and the P+ region 140 is heavily P-type doped. In this embodiment, the depth of the N+ source region 130 is greater than the depth of the P+ region 140, thereby making the length of the conductive channel formed when conduction is performed shorter, and thus reducing the resistance of the conductive channel.

[0025] The trench gate structure generally includes a trench 210 formed in the P-type body region, a gate oxide layer 220 formed on the trench wall of the trench 210, and a gate 230 filled in the trench 210; the depth of the trench 210 is generally 0.9 μm to 1.5 μm. In this embodiment, the gate oxide layer 220 includes a bottom gate oxide layer 221 formed at the bottom of the trench 210 and a sidewall gate oxide layer 222 formed on the sidewall of the trench 210. The bottom gate oxide layer 221 and the sidewall gate oxide layer 222 form the gate oxide layer 220. The gate oxide layer 220 can be formed by two growth processes, so that the thickness of the bottom gate oxide layer 221 is greater than the thickness of the sidewall gate oxide layer 222.

[0026] The thickness of the sidewall gate oxide layer 222 is generally 400 Å to 600 Å, and the thickness of the bottom gate oxide layer 221 is generally 2000 Å to 5000 Å thicker than the sidewall gate oxide layer 222. In this embodiment, by epitaxially forming a thicker P-type base region 120, the trench gate structure can be encapsulated. This not only reduces gate leakage charge and improves switching speed, but also reduces the electric field at the bottom of the trench 210, thereby effectively protecting the gate oxide layer 220 and improving reliability. Furthermore, the thickening of the bottom gate oxide layer 221 can further improve the reliability of the gate oxide layer 220 at this location.

[0027] The bottom of the trench gate structure is connected to the N-drift region 110 via an N-type region 150, which is N-type doped. The upper end of the trench gate structure is covered by an interlayer dielectric layer 300, the thickness of which is 0.8 μm to 1.3 μm. The width of the interlayer dielectric layer 300 is greater than the width of the trench 210. The width of the N-type region 150 is less than the width of the interlayer dielectric layer 300, but greater than or equal to the width of the trench 210, thus ensuring the device's breakdown voltage performance.

[0028] A source metal 400 is disposed at the upper end of the interlayer dielectric layer 300, the N+ source region 130, and the P+ region 140. Of course, a passivation layer is generally disposed on the source metal 400. A drain metal 500 is disposed at the lower end of the N+ substrate 100.

[0029] In this embodiment, by increasing the thickness of the P-type base region 120, the P-type base region 120 can completely enclose the trench gate structure; simultaneously, an N-type region 150 is formed at the bottom of the trench 210 to connect the trench gate structure and the N-drift region 110. This not only reduces gate leakage charge and improves switching speed but also reduces the electric field at the bottom of the trench 210, thereby effectively protecting the gate oxide layer 220 and improving reliability. Thickening the gate oxide layer 220 at the bottom of the trench 210 can further improve the reliability of the gate oxide layer 220 at this location, thus making the device more reliable. In addition, by increasing the depth of the N+ source region 130, the length of the formed conductive channel can be shortened, thereby reducing the resistance of the conductive channel.

[0030] The above embodiments only illustrate preferred implementations of this utility model, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.

Claims

1. A high-voltage trench MOSFET structure, characterized in that: The device comprises, from bottom to top, an N+ substrate, an N- drift region, and a P-type base region. The P-type base region has a trench gate structure, and the bottom of the trench gate structure is connected to the N- drift region through an N-type region. An N+ source region is disposed on each side of the upper part of the P-type base region corresponding to the two sides of the trench gate structure. A P+ region is disposed on the side of the N+ source region away from the trench gate structure. An interlayer dielectric layer covers the upper end of the trench gate structure. Source metal is disposed at the upper end of the interlayer dielectric layer, the N+ source region, and the P+ region. Drain metal is disposed at the lower end of the N+ substrate.

2. The high-voltage trench MOSFET structure as described in claim 1, characterized in that: The N+ substrate is heavily N-type doped; the N- drift region is lightly N-type doped; the P-type base region is P-type doped; the N-type region is N-type doped; the N+ source region is heavily N-type doped; and the P+ region is heavily P-type doped.

3. The high-voltage trench MOSFET structure as described in claim 1, characterized in that: The thickness of the P-type base region is 2μm to 3μm.

4. The high-voltage trench MOSFET structure as described in claim 1, characterized in that: The thickness of the N+ source region is greater than the thickness of the P+ region.

5. The high-voltage trench MOSFET structure as described in claim 1, characterized in that: The P-type base regions on both sides of the trench grid structure form a platform region, and the two ends of the interlayer dielectric layer extend horizontally outward to the top of the platform region.

6. The high-voltage trench MOSFET structure as described in claim 5, characterized in that: The width of the N-type region is less than the width of the interlayer dielectric layer, and greater than or equal to the width of the trench.

7. A high-voltage trench MOSFET structure as described in any one of claims 1 to 6, characterized in that: The trench gate structure includes a trench formed in the P-type body region, a gate oxide layer formed on the trench wall, and a gate filled in the trench.

8. The high-voltage trench MOSFET structure as described in claim 7, characterized in that: The gate oxide layer includes a bottom gate oxide layer formed at the bottom of the trench and a sidewall gate oxide layer formed on the sidewall of the trench, wherein the thickness of the bottom gate oxide layer is greater than the thickness of the sidewall gate oxide layer.

9. The high-voltage trench MOSFET structure as described in claim 8, characterized in that: The thickness of the sidewall gate oxide layer is 400 Å to 600 Å, and the thickness of the bottom gate oxide layer is 2000 Å to 5000 Å thicker than the thickness of the sidewall gate oxide layer.

10. A high-voltage trench MOSFET structure as described in claim 7, characterized in that: The depth of the trench is 0.9 μm to 1.5 μm.

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