MOSFET layout and MOSFET device

Abstract

The utility model provides an MOSFET layout and an MOSFET device. A first resistance adjusting region is arranged at the junction of a first source electrode metal region and a source electrode metal connecting region; and a second resistance adjusting region is arranged at the junction of the second source electrode metal region and the source electrode metal connecting region. According to the invention, through layout adjustment, a resistance adjusting area is added in a fixed area, and a series loop of a source-grid resistor and a source-drain capacitor is formed to absorb Vds oscillation voltage caused by reverse recovery of an MOSFET body diode.

Description

Technical Field

[0001] This application relates to various embodiments in the field of semiconductor technology, and particularly to a MOSFET layout and MOSFET device. Background Technology

[0002] The gate material of MOSFET devices is generally heavily doped polysilicon because silicon-based MOSFETs have parasitic body diodes. In DC-DC circuits, the reverse recovery of the body diodes of the upper and lower MOSFETs can cause overcharge oscillations in the circuit. In high-frequency operation, it is necessary to suppress the occurrence of circuit oscillations. Summary of the Invention

[0003] To address or mitigate the problems in the prior art, this application adjusts the layout by adding a resistor adjustment region in a fixed area, forming a series circuit of source-gate resistor and source-drain capacitor to absorb the Vds oscillation voltage caused by the reverse recovery of the MOSFET body diode.

[0004] In a first aspect, embodiments of this application provide a MOSFET layout, including: a gate metal connection region, a gate metal region, and a source metal region;

[0005] The gate metal region includes a first gate metal region and a second gate metal region, and the two ends of the gate metal connection region are respectively connected to the first gate metal region and the second gate metal region.

[0006] The source metal region includes a first source metal region, a second source metal region, and a third source metal region; the two ends of the source metal connection region are respectively connected to the first source metal region and the second source metal region; the third source metal region is disposed in the region enclosed by the first gate metal region, the gate metal connection region, and the second gate metal region; and the third source metal region is connected to the source metal connection region.

[0007] The first gate metal region is spaced apart from the first source metal region and the third source metal region, the third source metal region is spaced apart from the gate metal connection region, and the second gate metal region is spaced apart from the second source metal region and the third source metal region.

[0008] A first source contact hole region and a second source contact hole region are respectively provided on the first source metal region and the second source metal region; a first gate contact hole region and a second gate contact hole region are respectively provided on the first gate metal region and the second gate metal region; wherein, the first source contact hole and the first gate contact hole are provided on one side of the third source metal region, and the second source contact hole and the second gate contact hole are provided on the other side of the third source metal region.

[0009] The third source metal region is provided with a third source contact hole region and a fourth source metal region at intervals. The first source contact hole region, the first gate contact hole region, the second source contact hole region, and the second gate contact hole region are alternately arranged at both ends of the fourth source metal region.

[0010] A first resistance adjustment region is provided at the junction of the first source metal region and the source metal connection region;

[0011] A second resistance adjustment region is provided at the junction of the second source metal region and the source metal connection region;

[0012] A gate lead-out region is provided at the junction between the gate metal connection region and the second gate metal region.

[0013] Compared with the prior art, in this embodiment, a first resistance adjustment region is provided at the junction of the first source metal region and the source metal connection region; a second resistance adjustment region is provided at the junction of the second source metal region and the source metal connection region. This application adds one of the aforementioned resistance adjustment regions in a fixed area through layout adjustments, forming a series circuit of source-gate resistance and source-drain capacitance to absorb the oscillating Vds voltage.

[0014] Secondly, embodiments of this application provide a MOSFET device, fabricated according to the layout described in the first aspect, specifically including a device body;

[0015] A resistance adjustment region is provided on the source metal connection region in the device body.

[0016] In a preferred embodiment of this application, the resistance adjustment region is provided with a resistive material.

[0017] In a preferred embodiment of this application, the resistive material is a resistive metal or polycrystalline silicon with resistance.

[0018] Compared with the prior art, the beneficial effects of the MOSFET provided in this application are the same as those of the technical solution provided in the first aspect, and will not be repeated here. Attached Figure Description

[0019] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the drawings:

[0020] Figure 1This is a schematic diagram of a MOSFET layout provided in this application;

[0021] Figure 2 This is a schematic diagram of the structure of a MOSFET device provided in this application; Detailed Implementation

[0022] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.

[0023] Firstly, such as Figure 1 As shown, this application provides a MOSFET layout including: a gate metal connection region 5, a gate metal region, and a source metal region;

[0024] The gate metal region includes a first gate metal region 4 and a second gate metal region 6, and the two ends of the gate metal connection region 5 are respectively connected to the first gate metal region 4 and the second gate metal region 6.

[0025] The source metal region includes a first source metal region 1, a second source metal region 3, and a third source metal region 13; the source metal connection region 2 is connected to the first source metal region 1 and the second source metal region 3 at both ends; the third source metal region 13 is disposed in the region enclosed by the first gate metal region 4, the gate metal connection region 5, and the second gate metal region 6; and the third source metal region 13 is connected to the source metal connection region 2.

[0026] The first gate metal region 4 is spaced apart from the first source metal region 1 and the third source metal region 13, the third source metal region 13 is spaced apart from the gate metal connection region 5, and the second gate metal region 6 is spaced apart from the second source metal region 3 and the third source metal region 13.

[0027] A first source contact hole region 10 and a second source contact hole region 11 are respectively provided on the first source metal region 1 and the second source metal region 3; a first gate contact hole region 9 and a second gate contact hole region 12 are respectively provided on the first gate metal region 4 and the second gate metal region 6; wherein, the first source contact hole 10 and the first gate contact hole 9 are provided on one side of the third source metal region 13, and the second source contact hole 11 and the second gate contact hole 6 are provided on the other side of the third source metal region 13;

[0028] The third source metal region 13 is provided with a third source contact hole region 7 and a fourth source metal region 8 at intervals. The first source contact hole region 10, the first gate contact hole region 9, the second source contact hole region 8, and the second gate contact hole region 12 are alternately arranged at both ends of the fourth source metal region 8.

[0029] A first resistance adjustment region is provided at the junction of the first source metal region 1 and the source metal connection region 2;

[0030] A second resistance adjustment region 14 is provided at the junction of the second source metal region 3 and the source metal connection region 2;

[0031] A gate lead-out region 15 is provided at the junction between the gate metal connection region 5 and the second gate metal region 6.

[0032] Compared with the prior art, in this embodiment, a first resistance adjustment region 14 is provided at the junction of the first source metal region 1 and the source metal connection region 2; a second resistance adjustment region 15 is provided at the junction of the second source metal region 3 and the source metal connection region 2. This application adds one of the aforementioned resistance adjustment regions in a fixed area through layout adjustments, forming a series circuit of source-gate resistance and source-drain capacitance to absorb the Vds oscillation voltage caused by the reverse recovery of the MOSFET body diode.

[0033] Secondly, such as Figure 2 As shown, this application provides a MOSFET device, fabricated according to the layout described in the first aspect, specifically including a device body;

[0034] A resistance adjustment region is provided on the source metal connection region in the device body.

[0035] In a preferred embodiment of this application, the resistance adjustment region is provided with a resistive material.

[0036] In a preferred embodiment of this application, the resistive material is a resistive metal or polycrystalline silicon with resistance.

[0037] Compared with the prior art, the beneficial effects of the MOSFET provided in this application are the same as those of the technical solution provided in the first aspect, and will not be repeated here.

[0038] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A MOSFET layout, characterized in that, include: Gate metal connection region, gate metal region, and source metal region; The gate metal region includes a first gate metal region and a second gate metal region, and the two ends of the gate metal connection region are respectively connected to the first gate metal region and the second gate metal region. The source metal region includes a first source metal region, a second source metal region, and a third source metal region; the two ends of the source metal connection region are respectively connected to the first source metal region and the second source metal region; the third source metal region is disposed in the region enclosed by the first gate metal region, the gate metal connection region, and the second gate metal region; and the third source metal region is connected to the source metal connection region. The first gate metal region is spaced apart from the first source metal region and the third source metal region, the third source metal region is spaced apart from the gate metal connection region, and the second gate metal region is spaced apart from the second source metal region and the third source metal region. A first source contact hole region and a second source contact hole region are respectively provided on the first source metal region and the second source metal region; a first gate contact hole region and a second gate contact hole region are respectively provided on the first gate metal region and the second gate metal region; wherein, the first source contact hole and the first gate contact hole are provided on one side of the third source metal region, and the second source contact hole and the second gate contact hole are provided on the other side of the third source metal region. The third source metal region is provided with a third source contact hole region and a fourth source metal region at intervals. The first source contact hole region, the first gate contact hole region, the second source contact hole region, and the second gate contact hole region are alternately arranged at both ends of the fourth source metal region. A first resistance adjustment region is provided at the junction of the first source metal region and the source metal connection region; A second resistance adjustment region is provided at the junction of the second source metal region and the source metal connection region; A gate lead-out region is provided at the junction between the gate metal connection region and the second gate metal region.

2. A MOSFET device, characterized in that, The layout fabrication according to claim 1 specifically includes a device body; A resistance adjustment region is provided on the source metal connection region in the device body.

3. A MOSFET device as described in claim 2, characterized in that, The resistance adjustment area is provided with a resistive material.

4. A MOSFET device as described in claim 3, characterized in that, The resistive material is a resistive metal or polycrystalline silicon that has resistance.

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