Long-wave uncooled infrared camera architecture with phase locking function

Abstract

The utility model discloses a long-wave uncooled infrared camera framework with a phase locking function. The infrared camera framework comprises an infrared detector and a circuit framework. The infrared detector is used for receiving long-wave infrared radiation emitted by an object and converting the long-wave infrared radiation into an electric signal. The circuit framework comprises a plurality of circuit boards which are arranged in a stacked mode, and the circuit boards comprise an L1 detector circuit board, an L2 analog conversion circuit board, an L3 calculation circuit board, an L4 power supply circuit board, an L5 communication circuit board and an L6 interface circuit board. By integrating a high-computing-power FPGA (Field Programmable Gate Array) chip at a camera end and implanting a phase-locking computing algorithm into the high-computing-power FPGA chip, complete integration of image acquisition and processing is realized, the problems of delay and frame loss in a data transmission process are avoided, and the precision and reliability of phase-locking computing are improved. Through the stacked circuit architecture design, circuit boards with different functions are organically integrated, the integration level and stability of the system are improved, and meanwhile heat dissipation and maintenance are facilitated.

Description

TECHNICAL FIELD

[0001] The utility model belongs to infrared camera technical field, concretely relates to a long wave uncooled infrared camera frame with phase -locked loop function. BACKGROUND

[0002] The working principle of long wave uncooled infrared camera is mainly based on the temperature detection and imaging of the infrared radiation emitted by the object.The core component is infrared detector, especially micro bolometer type detector, which is the most mature technology and the highest market share mainstream uncooled infrared focal plane detector.The lens of long wave uncooled infrared camera receives the long wave infrared radiation (usually in the wavelength range of 8~14 microns) emitted by the object.The temperature of the detection pixel in the infrared detector changes after absorbing the infrared radiation, and then the resistance value of the thermistor changes.This resistance change is converted into an electrical signal by the readout circuit.The processed signal is converted into image data, and finally the thermal image of the object is presented on the display screen.This type of camera is generally used in military field, industrial detection, medical field, automatic driving and security monitoring.However, the temperature sensitivity of long wave uncooled infrared camera can be detected is greater than 50mK, and the more weak temperature change cannot be detected.

[0003] Generally, people will use image phase -locked loop calculation method to greatly improve the temperature detection sensitivity.Through the introduction of periodic excitation signal, the weak temperature change image is obtained through Fourier transform.However, this method generally uses host computer or through acquisition card to connect infrared camera to acquire image, and then carries out phase -locked loop calculation.When the phase -locked loop calculation is completed by host computer software, the configuration and communication interface speed of host computer are usually required to be higher, and the continuity of picture and the synchronization of excitation source cannot be guaranteed. SUMMARY

[0004] The utility model aims at providing a long wave uncooled infrared camera frame with phase -locked loop function, which can solve at least part of the above technical problems.

[0005] The first aspect of the utility model embodiment provides a long wave uncooled infrared camera frame with phase -locked loop function, and the infrared camera frame comprises:

[0006] Infrared detector, for receiving long wave infrared radiation emitted by the object and converting it into electrical signal;

[0007] Circuit architecture, the circuit architecture includes a plurality of circuit boards arranged in layers, respectively:

[0008] The L1 detector circuit board is connected to the infrared detector and is used to power on the infrared detector and for timing communication.

[0009] The L2 analog-to-digital converter circuit board is connected to the L1 detector circuit board and is used to convert the analog image data output by the infrared detector into digital signals.

[0010] The L3 computing circuit board is connected to the L2 analog conversion circuit board. The L3 computing circuit board integrates a high-performance FPGA chip. The FPGA chip implements a phase-locked loop (PLL) algorithm through a hardware description language (HDL) to receive the digital signal and complete the PLL calculation, thereby enabling real-time processing and calculation of image data at the camera end.

[0011] The L4 power supply circuit board is connected to the L3 computing circuit board and is used to provide power to the circuit architecture.

[0012] The L5 communication circuit board is connected to the L3 computing circuit board and is used to complete external interface communication and network port communication conversion.

[0013] The L6 interface circuit board is connected to the L5 communication circuit board and is used to connect external digital signal input / output interfaces, 24V power supply interfaces, RJ45 network interfaces, BNC trigger signal output interfaces, external grounding posts, and camera operation indicator lights.

[0014] Optionally, the L2 analog-to-digital converter circuit board includes an analog-to-digital converter (ADC), the input terminal of which is connected to the L1 detector circuit board and the output terminal of which is connected to the L3 computing circuit board, for converting the analog voltage signal output by the infrared detector into a digital signal.

[0015] Optionally, the FPGA chip of the L3 computing circuit board is connected to the L2 analog conversion circuit board via a high-speed data bus to receive and process the digital signal. The phase-locked loop calculation algorithm implemented by the FPGA chip of the L3 computing circuit board through a hardware description language (HDL) can process a large amount of image data output by the infrared detector in real time and directly output the calculation results to the L5 communication circuit board.

[0016] Optionally, the L4 power supply circuit board includes a multi-channel voltage conversion module for providing power at different voltage levels to the infrared detector, L1 detector circuit board, L2 analog conversion circuit board, L3 computing circuit board, L5 communication circuit board and L6 interface circuit board.

[0017] Optionally, the L5 communication circuit board includes a network interface module for transmitting the phase-locked loop calculation results of the L3 computing circuit board to the host computer via the UDP protocol.

[0018] Optionally, the L6 interface circuit board also includes a trigger signal input interface for receiving external trigger signals to synchronize the image acquisition and phase-locked loop calculation process of the infrared detector.

[0019] Optionally, the L3 computing circuit board further includes a storage module for temporarily storing the digital signals output by the L2 analog-to-digital converter circuit board to improve the efficiency and stability of data processing.

[0020] Optionally, the infrared detector is a microbolometer detector with a working wavelength range of 8–14 micrometers.

[0021] Optionally, the FPGA chip of the L3 computing circuit board is connected to the L2 analog conversion circuit board through a dedicated high-speed interface, which supports a data transmission rate of not less than 1Gbps.

[0022] Optionally, the L3 computing circuit board further includes a heat dissipation module for dissipating heat from the FPGA chip.

[0023] The main technical effects achieved by this embodiment of the invention are as follows: By integrating a high-performance FPGA chip into the camera and embedding the phase-locked loop (PLL) algorithm into it, complete integration of image acquisition and processing is realized, avoiding latency and frame loss during data transmission and improving the accuracy and reliability of PLL calculation. Utilizing the parallel processing capabilities of the FPGA chip, large amounts of image data can be processed in extremely short time, meeting real-time requirements and improving the overall performance of the camera. Through a layered circuit architecture design, circuit boards with different functions are organically integrated, improving the system's integration and stability, while also facilitating heat dissipation and maintenance. Attached Figure Description

[0024] Figure 1 This is a circuit architecture diagram of a long-wave uncooled infrared camera with phase-locked loop function in one embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of the internal data flow of the infrared camera architecture in one embodiment of the present invention.

[0026] Explanation of reference numerals in the attached diagram: 1. L1 detector circuit board; 2. L2 analog conversion circuit board; 3. L3 calculation circuit board; 4. L4 power supply circuit board; 5. L5 communication circuit board; 6. L6 interface circuit board. Detailed Implementation

[0027] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The manner described in the following exemplary embodiments does not represent all manner consistent with this invention. Rather, they are merely examples of apparatuses consistent with some aspects of this invention as detailed in the appended claims.

[0028] The terminology used in this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. Unless otherwise defined, the technical or scientific terms used in this invention should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar words used in this specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "a" or "one," and similar words do not indicate a quantity limitation, but rather indicate the presence of at least one, which will be separately stated if referring only to "a." "A plurality" or "several" indicates two or more. Unless otherwise stated, "front," "rear," "lower," and / or "upper," and similar words are for ease of description only and are not limited to a location or spatial orientation. The terms "comprising" or "including," and similar words mean that the elements or objects preceding "comprising" or "including" encompass the elements or objects listed following "comprising" or "including" and their equivalents, but do not exclude other elements or objects. The terms “connection” or “link” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The singular forms “a,” “the,” and “the” used in this specification and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0029] like Figure 1As shown, a first aspect of this utility model embodiment provides a long-wavelength uncooled infrared camera architecture with phase-locked loop (PLL) functionality. The infrared camera architecture includes an infrared detector and a circuit architecture. The infrared detector receives long-wavelength infrared radiation emitted by an object and converts it into an electrical signal. The circuit architecture includes multiple stacked circuit boards, namely, L1 detector circuit board 1, L2 analog conversion circuit board 2, L3 calculation circuit board 3, L4 power supply circuit board 4, L5 communication circuit board 5, and L6 interface circuit board 6. The L1 detector circuit board 1 is connected to the infrared detector and is used to power on the infrared detector and for timing communication. The L2 analog-to-digital converter circuit board 2 is connected to the L1 detector circuit board 1 and is used to convert the analog image data output by the infrared detector into digital signals. The L3 computing circuit board 3 is connected to the L2 analog-to-digital converter circuit board 2. The L3 computing circuit board 3 integrates a high-performance FPGA chip. The FPGA chip implements a phase-locked loop (PLL) algorithm through a hardware description language (HDL) to receive the digital signals and complete the PLL calculation, thereby enabling real-time processing and calculation of image data at the camera end. The L4 power supply circuit board 4 is connected to the L3 computing circuit board 3 and is used to provide power to the circuit architecture. The L5 communication circuit board 5 is connected to the L3 computing circuit board 3 and is used to complete external interface communication and network port communication conversion. The L6 interface circuit board 6 is connected to the L5 communication circuit board 5 and is used to connect external digital signal input / output interfaces, 24V power supply interfaces, RJ45 network interfaces, BNC trigger signal output interfaces, external grounding posts, and camera operation indicator lights. The phase-locked loop (PLL) algorithm for infrared images is embedded into the camera's own FPGA chip, allowing the camera to perform calculations directly on the captured images and output the results directly to the host computer. However, the addition of PLL functionality to the camera results in a massive computational load of image data, increasing the camera's power consumption and making it difficult for conventional circuit architectures and structural designs to dissipate heat effectively. Therefore, this invention designs a unique circuit stack-up architecture and structural form based on the camera's performance and power consumption requirements, ensuring both the computational needs for large amounts of data and adequate heat dissipation.

[0030] As an optional implementation, the L2 analog-to-digital converter (ADC) includes an input terminal connected to the L1 detector circuit board 1 and an output terminal connected to the L3 calculation circuit board 3, used to convert the analog voltage signal output by the infrared detector into a digital signal. By integrating the ADC on the L2 analog-to-digital converter circuit board 2, the analog voltage signal output by the infrared detector can be efficiently and accurately converted into a digital signal, providing a high-quality data foundation for subsequent phase-locked loop calculations.

[0031] As an optional implementation, the FPGA chip of the L3 computing circuit board 3 is connected to the L2 analog conversion circuit board 2 via a high-speed data bus to receive and process the digital signals. The phase-locked loop (PLL) calculation algorithm implemented by the FPGA chip of the L3 computing circuit board 3 using a hardware description language (HDL) can process a large amount of image data output by the infrared detector in real time and directly output the calculation results to the L5 communication circuit board 5. By embedding the PLL calculation algorithm into the FPGA chip using a hardware description language (HDL), the algorithm is hardware-based, greatly improving the calculation efficiency and significantly reducing the calculation time compared to traditional software implementation methods. The parallel processing capability of the FPGA chip enables the PLL calculation to be completed in real time, ensuring the immediate output of calculation results even when processing large amounts of image data, meeting the needs of real-time monitoring and analysis.

[0032] As an optional implementation, the L4 power supply circuit board 4 includes a multi-channel voltage conversion module for providing power at different voltage levels to the infrared detector, L1 detector circuit board 1, L2 analog conversion circuit board 2, L3 computing circuit board 3, L5 communication circuit board 5, and L6 interface circuit board 6. Through the multi-channel voltage conversion module of the L4 power supply circuit board 4, precise voltage supply is provided to circuit boards with different functions, ensuring that each module operates under optimal conditions, thus improving the stability and reliability of the system.

[0033] As an optional implementation, the L5 communication circuit board 5 includes a network interface module for transmitting the phase-locked loop (PLL) calculation results of the L3 calculation circuit board 3 to a host computer via the UDP protocol. Through the network interface module of the L5 communication circuit board 5, the PLL calculation results are quickly transmitted to the host computer using the UDP protocol. The low latency of the UDP protocol ensures real-time data transmission.

[0034] As an optional implementation, the L6 interface circuit board 6 further includes a trigger signal input interface for receiving external trigger signals to synchronize the image acquisition and phase-locked loop (PLL) calculation processes of the infrared detector. By adding a trigger signal input interface to the L6 interface circuit board 6, external synchronization signals can be received, ensuring precise synchronization between image acquisition and the excitation source, thereby improving the accuracy and reliability of the PLL calculation.

[0035] As an optional implementation, the L3 computing circuit board 3 further includes a storage module for temporarily storing the digital signals output from the L2 analog-to-digital converter circuit board 2, thereby improving the efficiency and stability of data processing. The storage module on the L3 computing circuit board 3 can temporarily store the digital signals output from the L2 analog-to-digital converter circuit board 2, avoiding blockages during data processing and improving the efficiency and stability of data processing.

[0036] As an optional implementation, the infrared detector is a microbolometer detector with an operating wavelength range of 8–14 micrometers. Using a microbolometer detector provides high sensitivity to long-wave infrared radiation (8–14 micrometers), enabling it to effectively receive and convert infrared radiation signals emitted by objects, thus providing a foundation for high-quality imaging.

[0037] As an optional implementation, the FPGA chip of the L3 computing circuit board 3 is connected to the L2 analog conversion circuit board 2 via a dedicated high-speed interface, which supports a data transmission rate of not less than 1Gbps. Connecting the L2 analog conversion circuit board 2 and the L3 computing circuit board 3 via a dedicated high-speed interface supports a data transmission rate of not less than 1Gbps, ensuring that large amounts of image data can be transmitted to the computing circuit board quickly and without loss, meeting the requirements of real-time processing.

[0038] As an optional implementation, the L3 computing circuit board 3 further includes a heat dissipation module for cooling the FPGA chip. By adding a heat dissipation module to the L3 computing circuit board 3, the temperature of the FPGA chip under high load can be effectively reduced, ensuring that it operates within a stable operating temperature range and extending the chip's lifespan.

[0039] like Figure 2 The diagram illustrates the internal data flow of an infrared camera architecture. The infrared detector driver controls the detector's reading order and reset time. Under the control of the driving clock, the infrared detector senses external infrared radiation signals and generates an analog voltage signal. This analog voltage signal is converted into a digital signal by an ADC converter chip. The driving clock controls the ADC's reading order, assembling an infrared image according to a specific number of rows and columns. This image is directly input into the phase-locked loop (PLL) algorithm, where the PLL calculation result is obtained on the camera's internal circuitry. The data result is encoded via UDP and finally transmitted directly to the host computer via a network interface. This operational process directly eliminates the errors in PLL results caused by frame loss during high-speed image transmission in traditional cameras. Within this framework, even if one transmission result is lost, the next transmission result will still be correct, unaffected by the transmission process, because all calculations are completed at the camera end.

[0040] The above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the scope of protection of the present utility model.

Claims

1. A long-wavelength uncooled infrared camera architecture with phase-locked loop (PLL) function, characterized in that, The infrared camera architecture includes: An infrared detector is used to receive long-wave infrared radiation emitted by an object and convert it into an electrical signal. The circuit architecture includes multiple stacked circuit boards, namely: The L1 detector circuit board is connected to the infrared detector and is used to power on the infrared detector and for timing communication. The L2 analog conversion circuit board is connected to the L1 detector circuit board and is used to convert the analog image data output by the infrared detector into digital signals. The L3 computing circuit board is connected to the L2 analog conversion circuit board. The L3 computing circuit board integrates a high-performance FPGA chip. The FPGA chip implements a phase-locked loop (PLL) algorithm through a hardware description language (HDL) to receive the digital signal and complete the PLL calculation, thereby enabling real-time processing and calculation of image data at the camera end. The L4 power supply circuit board is connected to the L3 computing circuit board and is used to provide power to the circuit architecture. The L5 communication circuit board is connected to the L3 computing circuit board and is used to complete external interface communication and network port communication conversion. The L6 interface circuit board is connected to the L5 communication circuit board and is used to connect external digital signal input / output interfaces, 24V power supply interfaces, RJ45 network interfaces, BNC trigger signal output interfaces, external grounding posts, and camera operation indicator lights.

2. The long-wavelength uncooled infrared camera architecture with phase-locked loop function according to claim 1, characterized in that, The L2 analog-to-digital converter circuit board includes an analog-to-digital converter (ADC). The input terminal of the ADC is connected to the L1 detector circuit board, and the output terminal is connected to the L3 computing circuit board. It is used to convert the analog voltage signal output by the infrared detector into a digital signal.

3. The long-wavelength uncooled infrared camera architecture with phase-locked loop function according to claim 1, characterized in that, The FPGA chip of the L3 computing circuit board is connected to the L2 analog conversion circuit board via a high-speed data bus to receive and process the digital signal. The phase-locked loop calculation algorithm implemented by the FPGA chip of the L3 computing circuit board through a hardware description language (HDL) can process a large amount of image data output by the infrared detector in real time and output the calculation results directly to the L5 communication circuit board.

4. The long-wavelength uncooled infrared camera architecture with phase-locked loop function according to claim 1, characterized in that, The L4 power supply circuit board includes a multi-channel voltage conversion module for providing power at different voltage levels to the infrared detector, L1 detector circuit board, L2 analog conversion circuit board, L3 computing circuit board, L5 communication circuit board and L6 interface circuit board.

5. The long-wavelength uncooled infrared camera architecture with phase-locked loop function according to claim 1, characterized in that, The L5 communication circuit board includes a network interface module, which is used to transmit the phase-locked loop calculation results of the L3 calculation circuit board to the host computer via the UDP protocol.

6. The long-wavelength uncooled infrared camera architecture with phase-locked loop function according to claim 1, characterized in that, The L6 interface circuit board also includes a trigger signal input interface for receiving external trigger signals to synchronize the image acquisition and phase-locked loop calculation process of the infrared detector.

7. The long-wavelength uncooled infrared camera architecture with phase-locked loop function according to claim 1, characterized in that, The L3 computing circuit board also includes a storage module for temporarily storing the digital signals output by the L2 analog-to-digital converter circuit board, so as to improve the efficiency and stability of data processing.

8. The long-wavelength uncooled infrared camera architecture with phase-locked loop function according to claim 1, characterized in that, The infrared detector is a microbolometer detector with a working wavelength range of 8–14 micrometers.

9. The long-wavelength uncooled infrared camera architecture with phase-locked loop function according to claim 1, characterized in that, The FPGA chip of the L3 computing circuit board is connected to the L2 analog conversion circuit board through a dedicated high-speed interface, which supports a data transmission rate of not less than 1Gbps.

10. The long-wavelength uncooled infrared camera architecture with phase-locked loop function according to claim 1, characterized in that, The L3 computing circuit board also includes a heat dissipation module for dissipating heat from the FPGA chip.

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