Pixel circuit, display device having same, and electronic device including display device

Abstract

The utility model relates to a pixel circuit, a display device and an electronic device including the display device. The pixel circuit includes: a first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor configured to apply a data voltage to the first transistor; a third transistor connected to the first node and a third node; a fourth transistor configured to apply a first power voltage to the second node in response to the first transmission signal; a fifth transistor configured to apply a voltage of a fourth node to the third node in response to a second transmission signal different from the first transmission signal; a seventh transistor configured to apply a driving current to the light emitting element and connected to the fourth node; a ninth transistor configured to apply an initialization voltage to a fourth node; and a light emitting element configured to emit light based on the driving current.

Description

Technical Field

[0001] This disclosure relates to pixel circuits, display devices including pixel circuits, and electronic devices including display devices. Background Technology

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel includes multiple gate lines, multiple data lines, and multiple pixels. The display panel driver includes a gate driver that provides gate signals to the gate lines, a data driver that provides data voltages to the data lines, and a drive controller that controls the gate driver and the data driver.

[0003] Conventional pixel circuits driven by pulse width modulation methods and performing internal compensation of threshold voltages may include nineteen or more transistors and three or more capacitors, making them difficult to apply to ultra-high resolution display devices due to integration limitations. Utility Model Content

[0004] Embodiments of this disclosure provide a pixel circuit driven by pulse width modulation, performing internal compensation of the threshold voltage, and including a small number of transistors, thus making it suitable for ultra-high resolution display devices.

[0005] Embodiments of this disclosure also provide a display device including pixel circuitry and an electronic device including a display device.

[0006] According to one or more embodiments, the pixel circuit may include: a first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor configured to apply a data voltage to the first transistor; a third transistor connected to the first node and the third node; a fourth transistor configured to apply a first power voltage to the second node in response to a first transmit signal; a fifth transistor configured to apply a voltage of the fourth node to the third node in response to a second transmit signal different from the first transmit signal; a seventh transistor configured to apply a drive current to a light-emitting element and connected to the fourth node; a ninth transistor configured to apply an initialization voltage to the fourth node; and a light-emitting element configured to emit light based on the drive current. The initialization voltage may have a low initialization voltage level or a constant current voltage level. The first transistor may be a P-type transistor, the second transistor may be an N-type transistor, the third transistor may be an N-type transistor, and the seventh transistor may be a P-type transistor.

[0007] In one or more embodiments, the ninth transistor may include a control electrode configured to receive a second scan signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the fourth node.

[0008] In one or more embodiments, the pixel circuit may further include a first capacitor, the first capacitor including a first electrode configured to receive a sweep frequency signal and a second electrode connected to a first node.

[0009] In one or more embodiments, the pixel circuit may further include an eighth transistor, the eighth transistor including a control electrode configured to receive an initialization signal, a first electrode configured to receive an initialization voltage of the light-emitting element, and a second electrode connected to the light-emitting element.

[0010] In one or more embodiments, the pixel circuit may further include a sixth transistor, the sixth transistor including a control electrode configured to receive a first transmission signal, a first electrode configured to receive a second electrical voltage, and a second electrode connected to a seventh transistor.

[0011] In one or more embodiments, the pixel circuit may further include a second capacitor, the second capacitor including a first electrode receiving a second electrical voltage and a second electrode connected to a fourth node.

[0012] In one or more embodiments, the second transistor may include a control electrode configured to receive a first scan signal, a first electrode configured to receive a data voltage, and a second electrode connected to a second node. The third transistor may include a control electrode configured to receive the first scan signal, a first electrode connected to a first node, and a second electrode connected to a third node. The seventh transistor may include a control electrode connected to a fourth node, a first electrode connected to a fifth node, and a second electrode connected to a light-emitting element.

[0013] In one or more embodiments, the pixel circuit may further include a first capacitor, a second capacitor, a sixth transistor, and an eighth transistor. The second transistor may include a control electrode configured to receive a first scan signal, a first electrode configured to receive a data voltage, and a second electrode connected to a second node. The third transistor may include a control electrode configured to receive the first scan signal, a first electrode connected to a first node, and a second electrode connected to a third node. The fourth transistor may include a control electrode configured to receive a first transmit signal, a first electrode configured to receive a first power voltage, and a second electrode connected to a second node. The fifth transistor may include a control electrode configured to receive a second transmit signal, a first electrode connected to a third node, and a second electrode connected to a fourth node. The sixth transistor may include a control electrode configured to receive the first transmit signal, a first electrode connected to a fifth node, and a second electrode connected to a sixth node. The seventh transistor may include a control electrode connected to a fourth node, a first electrode configured to receive a second power voltage, and a second electrode connected to a fifth node. The eighth transistor may include a control electrode configured to receive an initialization signal, a first electrode configured to receive a light-emitting element initialization voltage, and a second electrode connected to a sixth node. The ninth transistor may include a control electrode configured to receive a second scan signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to a fourth node. The first capacitor may include a first electrode configured to receive a sweep frequency signal and a second electrode connected to a first node. The second capacitor may include a first electrode configured to receive a second electrical voltage and a second electrode connected to a fourth node. The light-emitting element may include a first electrode connected to a sixth node and a second electrode configured to receive a third electrical voltage.

[0014] In one or more embodiments, the pixel circuit may further include a first capacitor, a second capacitor, a sixth transistor, and an eighth transistor. The second transistor may include a control electrode configured to receive a first scan signal, a first electrode configured to receive a data voltage, and a second electrode connected to a second node. The third transistor may include a control electrode configured to receive the first scan signal, a first electrode connected to a first node, and a second electrode connected to a third node. The fourth transistor may include a control electrode configured to receive a first transmit signal, a first electrode configured to receive a first power voltage, and a second electrode connected to a second node. The fifth transistor may include a control electrode configured to receive a second transmit signal, a first electrode connected to a third node, and a second electrode connected to a fourth node. The sixth transistor may include a control electrode configured to receive the first transmit signal, a first electrode configured to receive a second power voltage, and a second electrode connected to a fifth node. The seventh transistor may include a control electrode connected to a fourth node, a first electrode connected to a fifth node, and a second electrode connected to a sixth node. The eighth transistor may include a control electrode configured to receive an initialization signal, a first electrode configured to receive a light-emitting element initialization voltage, and a second electrode connected to a sixth node. The ninth transistor may include a control electrode configured to receive a second scan signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to a fourth node. The first capacitor may include a first electrode configured to receive a sweep frequency signal and a second electrode connected to a first node. The second capacitor may include a first electrode configured to receive a second electrical voltage and a second electrode connected to a fourth node. The light-emitting element may include a first electrode connected to a sixth node and a second electrode configured to receive a third electrical voltage.

[0015] In one or more embodiments, the fourth, fifth, sixth, and eighth transistors may be P-type transistors, and the ninth transistor may be an N-type transistor.

[0016] In one or more embodiments, the fifth and eighth transistors may be P-type transistors, and the fourth, sixth, and ninth transistors may be N-type transistors.

[0017] In one or more embodiments, the initial voltage of the light-emitting element may be a third electrical voltage.

[0018] In one or more embodiments, during the first cycle, the initialization voltage may have a low initialization voltage level, the first scan signal may have an active level, the second scan signal may have an active level, the first transmit signal may have an inactive level, the second transmit signal may have an active level, and the initialization signal may have an active level. During the first cycle, the third, fifth, eighth, and ninth transistors may be turned on, and the fourth transistor may be turned off.

[0019] In one or more embodiments, in a second cycle following the first cycle, the initialization voltage may have a low initialization voltage level, the first scan signal may have an invalid level, the second scan signal may have an active level, the first transmit signal may have an invalid level, and the second transmit signal may have an invalid level. In the second cycle, the ninth transistor may be turned on, and the fifth transistor may be turned off.

[0020] In one or more embodiments, during a third cycle following the second cycle, the first scan signal may have an active level, and the second transmit signal may have an inactive level. During the third cycle, the second and third transistors may be turned on, and the fifth transistor may be turned off.

[0021] In one or more embodiments, during the fourth cycle following the third cycle, the initialization voltage may have a constant current voltage level, the second scan signal may have an active level, and the second transmit signal may have an inactive level. During the fourth cycle, the ninth transistor may be turned on, and the fifth transistor may be turned off.

[0022] In one or more embodiments, during the fifth cycle following the fourth cycle, the sweep signal can gradually decrease from a high level, and the first transmit signal can have an active level. During the fifth cycle, the sixth and seventh transistors can be turned on.

[0023] In one or more embodiments, during the sixth cycle following the fifth cycle, the sweep signal may gradually decrease, and the second transmit signal may have an effective level. During the sixth cycle, the first and fifth transistors may be turned on, and the seventh transistor may be turned off.

[0024] In one or more embodiments, during the seventh cycle following the sixth cycle, the sweep signal may be high, the first transmit signal may be inactive, the second transmit signal may be inactive, and the initialization signal may be active. During the seventh cycle, the eighth transistor may be turned on.

[0025] According to one or more embodiments, a display device may include: a display panel including pixel circuitry; a gate driver configured to apply a gate signal to the pixel circuitry; an emitter driver configured to apply an emitter signal to the pixel circuitry; and a data driver configured to apply a data voltage to the pixel circuitry. The pixel circuitry may include: a first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor configured to apply a data voltage to the first transistor; a third transistor connected to the first node and the third node; a fourth transistor configured to apply a first power voltage to the second node in response to a first emitter signal; a fifth transistor configured to apply a voltage of the fourth node to the third node in response to a second emitter signal different from the first emitter signal; a seventh transistor configured to apply a drive current to a light-emitting element and connected to the fourth node; a ninth transistor configured to apply an initialization voltage to the fourth node; and a light-emitting element configured to emit light based on the drive current. The initialization voltage may have a low initialization voltage level or a constant current voltage level. The first transistor may be a P-type transistor, the second transistor may be an N-type transistor, the third transistor may be an N-type transistor, and the seventh transistor may be a P-type transistor.

[0026] In one or more embodiments, the electronic device includes a display device, the display device comprising: a display panel including pixel circuitry; and a display driver configured to drive the display panel, wherein the pixel circuitry includes: a first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor configured to apply a data voltage to the first transistor; a third transistor connected to the first node and the third node; a fourth transistor configured to apply a first power voltage to the second node in response to a first transmission signal; a fifth transistor configured to apply a voltage of the fourth node to the third node in response to a second transmission signal different from the first transmission signal; a seventh transistor configured to apply a drive current to a light-emitting element and connected to the fourth node; a ninth transistor configured to apply an initialization voltage to the fourth node; and a light-emitting element configured to emit light based on the drive current, wherein the initialization voltage has a low initialization voltage level or a constant current voltage level, and wherein the first transistor is a P-type transistor, the second transistor is an N-type transistor, the third transistor is an N-type transistor, and the seventh transistor is a P-type transistor.

[0027] In one or more embodiments, the electronic device may include a cellular phone, video phone, smart panel, television (TV), smartwatch, car navigation system, computer display, laptop computer, or head-mounted display (HMD) device.

[0028] As described above, the pixel circuit may include nine transistors and two capacitors. The pixel circuit can be driven by pulse width modulation (PWM), performing internal compensation of the threshold voltage, and includes fewer transistors compared to conventional pixel circuits, allowing for high integration. Therefore, the pixel circuit can be applied to ultra-high resolution display devices. Furthermore, at least one transistor in the PWM circuit and at least one transistor in the constant current generation circuit can be N-type transistors, reducing power consumption. Additionally, the first transistor in the PWM circuit and the seventh transistor in the constant current generation circuit can be P-type transistors, improving mobility. Furthermore, the initial voltage applied to the second electrode of the eighth transistor can be lower than the third power voltage applied to the cathode of the light-emitting element, improving the black characteristics of the pixel circuit. Furthermore, the low initial voltage level applied to the control electrode of the first transistor and the constant current voltage level applied to the control electrode of the seventh transistor can be output from the same voltage terminal, reducing the number of transistors and signal lines. Additionally, the ninth transistor can apply the low initial voltage level to the first node via the second transmit signal and the fifth transistor. Therefore, the ninth transistor can be both a transistor for initializing the first node and a transistor for applying the constant current voltage level to the fourth node. Therefore, the integration density of pixel circuits can be improved. Attached Figure Description

[0029] The illustrative, non-limiting embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings.

[0030] Figure 1 This is a block diagram illustrating a display device according to one or more embodiments of the present disclosure.

[0031] Figure 2 It is shown Figure 1 A circuit diagram of an example pixel circuit for a display panel.

[0032] Figure 3 It shows that it is applied to Figure 2 A timing diagram of an example of the signal of a pixel.

[0033] Figure 4 This shows the first cycle. Figure 2 The circuit diagram for the operation of the pixel circuit.

[0034] Figure 5 This shows the second cycle. Figure 2 The circuit diagram for the operation of the pixel circuit.

[0035] Figure 6 This shows the third cycle. Figure 2 The circuit diagram for the operation of the pixel circuit.

[0036] Figure 7 This shows the fourth period Figure 2 The circuit diagram for the operation of the pixel circuit.

[0037] Figure 8 This shows the fifth cycle. Figure 2 The circuit diagram for the operation of the pixel circuit.

[0038] Figure 9 This shows the sixth cycle. Figure 2 The circuit diagram for the operation of the pixel circuit.

[0039] Figure 10 This shows the seventh period Figure 2 The circuit diagram for the operation of the pixel circuit.

[0040] Figure 11 It shows that it is applied to Figure 2 A timing diagram of an example of the signals of a pixel circuit.

[0041] Figure 12 It is shown Figure 1 A circuit diagram of an example pixel circuit for a display panel.

[0042] Figure 13 It is shown Figure 1 A circuit diagram of an example pixel circuit for a display panel.

[0043] Figure 14 It is shown Figure 1 A circuit diagram of an example pixel circuit for a display panel.

[0044] Figure 15 This is a block diagram illustrating an electronic device according to one or more embodiments of the present disclosure.

[0045] Figure 16 It is shown that Figure 15 A diagram illustrating an example of an electronic device implemented as a smartphone. Detailed Implementation

[0046] This disclosure will be explained in detail below with reference to the accompanying drawings.

[0047] In light of the entire contents of this disclosure, those skilled in the art will understand that each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or combined with one another, and may be technically interlocked and operated in a variety of suitable ways, and each embodiment may be implemented independently of one another or in combination with one another in any suitable way, unless otherwise stated or implied.

[0048] Figure 1 This is a block diagram illustrating a display device according to one or more embodiments of the present disclosure.

[0049] refer to Figure 1 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500. The display panel driver may also include a transmit driver 600. In one or more embodiments, the display panel driver can output... Figure 2 The initial voltage VINT.

[0050] The display panel 100 has a display area on which an image is displayed and a peripheral area adjacent to the display area.

[0051] The display panel 100 includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels PX electrically connected to the gate lines GL and the data lines DL. The gate lines GL may extend in a first direction D1, and the data lines DL may extend in a second direction D2 intersecting the first direction D1. Each of the plurality of pixels PX may include pixel circuitry.

[0052] The drive controller 200 receives input image data IMG and input control signal CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may also include white image data. The input image data IMG may also include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0053] The drive controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0054] The drive controller 200 generates a first control signal CONT1 based on the input control signal CONT for controlling the operation of the gate driver 300, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0055] The drive controller 200 generates a second control signal CONT2 based on the input control signal CONT for controlling the operation of the data driver 500, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0056] The drive controller 200 generates a data signal DATA based on the input image data IMG. The drive controller 200 outputs the data signal DATA to the data driver 500.

[0057] The drive controller 200 generates a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and outputs the third control signal CONT3 to the gamma reference voltage generator 400.

[0058] The drive controller 200 generates a fourth control signal CONT4 based on the input control signal CONT for controlling the operation of the transmitter driver 600, and outputs the fourth control signal CONT4 to the transmitter driver 600.

[0059] The gate driver 300 generates a gate signal to drive the pixel PX connected to the gate line GL in response to a first control signal CONT1 received from the drive controller 200. The gate driver 300 can output the gate signal to the gate line GL.

[0060] In one or more embodiments, the gate driver 300 may be disposed in the peripheral region. In one or more embodiments, the gate driver 300 may be integrated into the peripheral region.

[0061] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to the level of the data signal DATA.

[0062] For example, the gamma reference voltage generator 400 can be located in the drive controller 200 or in the data driver 500.

[0063] The data driver 500 receives a second control signal CONT2 and a data signal DATA from the drive controller 200, and receives a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 uses the gamma reference voltage VGREF to convert the data signal DATA into a data voltage VDATA of analog type (see [link to relevant documentation]). Figure 2 The data driver 500 outputs the data voltage VDATA to the data line DL. Figure 2 The data voltage VDATA can have Figure 3 Pulse Width Data Voltage Level VPWM and Figure 3 The low initialization voltage level VINTL.

[0064] In one or more embodiments, the data driver 500 may be located in the peripheral region. In one or more embodiments, the data driver 500 may be integrated into the peripheral region.

[0065] The transmitter driver 600 generates a transmit signal EM in response to a fourth control signal CONT4 received from the drive controller 200. The transmitter driver 600 can output the transmit signal EM to the display panel 100. The transmit signal EM may include... Figure 3 The first transmission signal EM1 and the second transmission signal EM2.

[0066] In one or more embodiments, the transmitter driver 600 may be located in the peripheral region. In one or more embodiments, the transmitter driver 600 may be integrated into the peripheral region.

[0067] Figure 3 It is shown Figure 3 A circuit diagram of an example pixel circuit for a display panel.

[0068] refer to Figure 3 and Figure 3 The pixel circuit may include a first circuit PC and a second circuit CC.

[0069] The first circuit PC can be a pulse width modulation circuit PC used to perform pulse width modulation. The second circuit CC can be a constant current generating circuit CC used to generate a constant current.

[0070] The first circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5, as well as a first capacitor C1. The second circuit CC may include a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9, as well as a second capacitor C2. The second circuit CC may include a light-emitting element EE.

[0071] For example, the light-emitting element EE can be a light-emitting diode (LED). In one or more embodiments, the light-emitting element EE can be a micro LED. The light-emitting element EE can be based on... Figure 3 Pulse Width Data Voltage Level VPWM and Figure 3 It emits light using a constant current voltage level (VCCG).

[0072] The pixel circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, a second capacitor C2, and a light-emitting element EE.

[0073] The first transistor T1 may include a control electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3.

[0074] The second transistor T2 may include a control electrode that receives a first scan signal SPWM[n], a first electrode that receives a data voltage VDATA, and a second electrode connected to the second node N2. The second transistor T2 may apply the data voltage VDATA to the first transistor T1 in response to the first scan signal SPWM[n].

[0075] The third transistor T3 may include a control electrode that receives the first scan signal SPWM[n], a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The third transistor T3 may be connected to both the first node N1 and the third node N3.

[0076] The fourth transistor T4 may include a control electrode that receives the first transmit signal EM1, a first electrode that receives the first power voltage VDD1, and a second electrode connected to the second node N2. The fourth transistor T4 may apply the first power voltage VDD1 to the second node N2 in response to the first transmit signal EM1.

[0077] The fifth transistor T5 may include a control electrode for receiving the second transmission signal EM2, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4. The fifth transistor T5 may apply a voltage from the fourth node N4 to the third node N3 in response to the second transmission signal EM2. The first transmission signal EM1 and the second transmission signal EM2 may be different.

[0078] The sixth transistor T6 may include a control electrode that receives the first transmit signal EM1, a first electrode that receives the second power voltage VDD2, and a second electrode connected to the fifth node N5. The sixth transistor T6 may apply the second power voltage VDD2 to the fifth node N5 in response to the first transmit signal EM1.

[0079] The seventh transistor T7 may include a control electrode connected to the fourth node N4, a first electrode connected to the fifth node N5, and a second electrode connected to the sixth node N6. The seventh transistor T7 can apply a drive current to the light-emitting element EE in response to the voltage of the fourth node N4.

[0080] The eighth transistor T8 may include a control electrode that receives the initialization signal BCB, a first electrode that receives the light-emitting element initialization voltage VAINT, and a second electrode connected to the sixth node N6. The eighth transistor T8 may apply the light-emitting element initialization voltage VAINT to the sixth node N6 in response to the initialization signal BCB.

[0081] The ninth transistor T9 may include a control electrode for receiving the second scan signal SCCG, a first electrode for receiving the initialization voltage VINT, and a second electrode connected to the fourth node N4. The ninth transistor T9 can apply the initialization voltage VINT to the fourth node N4. Additionally, the ninth transistor T9 can apply the initialization voltage VINT to the first node N1. The initialization voltage VINT may have… Figure 2 Low initialization voltage level VINTL and Figure 3 The constant current voltage level VCCG. The initialization voltage VINT can be an AC voltage. For example, the ninth transistor T9 can be referred to as the initialization transistor.

[0082] The first capacitor C1 may include a first electrode for receiving the sweep frequency signal VSWEEP and a second electrode connected to the first node N1.

[0083] The second capacitor C2 may include a first electrode that receives the second electrical voltage VDD2 and a second electrode connected to the fourth node N4.

[0084] Therefore, a pixel circuit can include nine transistors and two capacitors.

[0085] In this embodiment, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type transistors. The second transistor T2, the third transistor T3, and the ninth transistor T9 can be N-type transistors.

[0086] In this embodiment, some transistors in the pixel circuit can be P-type transistors, and others can be N-type transistors. For example, the P-type transistors can be low-temperature polysilicon (LTPS) transistors. For example, the N-type transistors can be oxide transistors. Specifically, the second transistor T2, the third transistor T3, and the ninth transistor T9 can be configured as N-type transistors, and therefore, the current leakage of the second transistor T2, the third transistor T3, and the ninth transistor T9 can be reduced, allowing the pixel circuit to operate stably even when using relatively low power voltages. Therefore, by configuring the second transistor T2, the third transistor T3, and the ninth transistor T9 as N-type transistors, the power consumption of the display device can be reduced.

[0087] In this embodiment, the force applied to the first node N1 and the fourth node N4 is... Figure 2 Low initialization voltage level VINTL and Figure 4 The constant current voltage level VCCG can be output from the same voltage terminal, which reduces the number of transistors and signal lines.

[0088] Furthermore, the ninth transistor T9 can change the voltage of the first node N1 and the fourth node N4, thereby reducing the number of transistors.

[0089] Based on the emission intensity of each pixel, Figure 2 The pulse width data voltage level VPWM can have the same or different values. Figure 5 The constant current voltage level (VCCG) can have the same voltage level for all pixels. Alternatively, Figure 2 The constant current voltage level (VCCG) can have a first voltage level for red pixels, a second voltage level different from the first voltage level for green pixels, and a third voltage level different from the first and second voltage levels for blue pixels.

[0090] For example, the first power voltage VDD1 and the second power voltage VDD2 can be high power voltages used to determine the luminous level of the light-emitting element EE, and the third power voltage VSS can be a low power voltage used to determine the luminous level of the light-emitting element EE. The first power voltage VDD1 and the second power voltage VDD2 can be higher than the third power voltage VSS.

[0091] Furthermore, the first power voltage VDD1 can be higher than the second power voltage VDD2.

[0092] During the emission cycle, the light-emitting element EE can emit light while the first transistor T1 is off and the seventh transistor T7 is on. During the emission cutoff cycle, when the first transistor T1 is on and the first power voltage VDD1 is applied to the control electrode of the seventh transistor T7, the seventh transistor T7 can be turned off and the light-emitting element EE can stop emitting light.

[0093] At this time, since the first power voltage VDD1 becomes greater than the second power voltage VDD2, the seventh transistor T7 can more reliably remain in the off state when the first power voltage VDD1 is applied to the control electrode of the seventh transistor T7.

[0094] For example, the initial voltage VAINT of the light-emitting element can be lower than the third power supply voltage VSS. When the initial voltage VAINT of the light-emitting element is lower than the third power supply voltage VSS, leakage current can be prevented from flowing into the light-emitting element EE.

[0095] In this embodiment, the first scan signal SPWM[n] can be a row-by-row scan signal with different timing for each pixel row. Here, [n] can represent the nth pixel row. The first scan signal SPWM[n] is applied... Figure 6 The pixel circuit can be a pixel circuit included in the nth pixel row.

[0096] The initialization signal BCB and the second scan signal SCCG can be global scan signals with the same timing, independent of pixel rows. The first transmission signal EM1 and the second transmission signal EM2 can also be global scan signals with the same timing, independent of pixel rows.

[0097] The first power voltage VDD1, the second power voltage VDD2, the third power supply voltage VSS, and the initialization voltage VAINT of the light-emitting element can be DC voltages. On the other hand, the initialization voltage VINT can be AC ​​voltages.

[0098] Figure 2 It shows that it is applied to Figure 7 A timing diagram of an example of the signal of a pixel. Figure 2 This shows the first cycle TP1A. Figure 8 The circuit diagram for the operation of the pixel circuit. Figure 2 This shows the second cycle TP2A. Figure 9 The circuit diagram for the operation of the pixel circuit. Figure 2 This shows the third cycle TP3A. Figure 10 The circuit diagram for the operation of the pixel circuit. Figure 2 This shows the fourth period TP4A. Figure 3 The circuit diagram for the operation of the pixel circuit. Figure 4 This shows the fifth period TP5A. Figure 3 The circuit diagram for the operation of the pixel circuit. Figure 5 This shows the sixth period TP6A. Figure 3 The circuit diagram for the operation of the pixel circuit. Figure 6 This shows the seventh period TP7A. Figure 3 Circuit diagram of pixel circuit operation

[0099] In this embodiment, the first cycle TP1A can be the first initialization cycle, the second cycle TP2A can be the second initialization cycle, the third cycle TP3A can be the pulse width modulation data writing and compensation cycle, the fourth cycle TP4A can be the constant current voltage writing cycle, the fifth cycle TP5A can be the transmission cycle, the sixth cycle TP6A can be the transmission cutoff cycle, and the seventh cycle TP7A can be the discharge cycle.

[0100] The width of the fifth cycle TP5A, which is the transmission cycle, can be determined by the pulse width data voltage level VPWM.

[0101] refer to Figure 7 and Figure 3In the first cycle TP1A, the data voltage VDATA can have a low initialization voltage level VinTL, the initialization voltage VINT can have a low initialization voltage level VinTL, the initialization signal BCB can have an active level, the first scan signal SPWM[n] can have an active level, the second scan signal SCCG can have an active level, the first transmit signal EM1 can have an inactive level, the second transmit signal EM2 can have an active level, and the sweep frequency signal VSWEEP can have a high level.

[0102] In this paper, when the transistor receiving the initialization signal BCB, the first scan signal SPWM[n], the second scan signal SCCG, the first transmit signal EM1, and the second transmit signal EM2 is a P-type transistor, the effective level is low and the ineffective level is high. When the transistor receiving the initialization signal BCB, the first scan signal SPWM[n], the second scan signal SCCG, the first transmit signal EM1, and the second transmit signal EM2 is an N-type transistor, the effective level is high and the ineffective level is low.

[0103] The first cycle TP1A can be the first initialization cycle. During the first cycle TP1A, transistors T3, T5, T8, and T9 can be turned on. Transistor T4 can be turned off during the first cycle TP1A.

[0104] In the first cycle TP1A, the control electrode of the first transistor T1 can be initialized to a low initialization voltage level VINTL by the ninth transistor T9. In the first cycle TP1A, the second node N2 can be initialized to a low initialization voltage level VINTL by the second transistor T2. In the first cycle TP1A, the first electrode (e.g., the anode) of the light-emitting element EE can be initialized to the light-emitting element initialization voltage VAINT by the eighth transistor T8.

[0105] refer to Figure 8 and Figure 3 In the second cycle TP2A following the first cycle TP1A, the initialization voltage VINT can have a low initialization voltage level VINTL, the initialization signal BCB can have an active level, the first scan signal SPWM[n] can have an inactive level, the second scan signal SCCG can have an active level, the first transmit signal EM1 can have an inactive level, the second transmit signal EM2 can have an inactive level, and the sweep frequency signal VSWEEP can have a high level.

[0106] The second cycle TP2A can be the second initialization cycle. During the second cycle TP2A, the fifth transistor T5 can be turned off. During the second cycle TP2A, the eighth transistor T8 and the ninth transistor T9 can be turned on.

[0107] In the second cycle TP2A, the fourth node N4 can be initialized to a low initialization voltage level VINTL by the ninth transistor T9. In the second cycle TP2A, the first electrode (e.g., the anode) of the light-emitting element EE can be initialized to the light-emitting element initialization voltage VAINT by the eighth transistor T8.

[0108] refer to Figure 9 and Figure 3 In the third cycle TP3A following the second cycle TP2A, the initialization voltage VINT can have a low initialization voltage level VINTL, the first scan signal SPWM[n] can have an active level, the second scan signal SCCG can have an inactive level, the first transmit signal EM1 can have an inactive level, the second transmit signal EM2 can have an inactive level, the sweep frequency signal VSWEEP can have a high level, and the initialization signal BCB can have an active level.

[0109] The third cycle TP3A can be the pulse width modulation data writing and compensation cycle. In the third cycle TP3A, the second transistor T2 can be turned on in response to the first scan signal SPWM[n]. Because the first node N1 can have a low initialization voltage level VINTL in the first cycle TP1A, the first transistor T1 can be turned on in the third cycle TP3A. The third transistor T3 can be turned on in response to the first scan signal SPWM[n]. In the third cycle TP3A, the eighth transistor T8 can remain on.

[0110] In the third cycle TP3A, the pulse width data voltage level VPWM can be applied to the control electrode (e.g., first node N1) of the first transistor T1 via the path of the second transistor T2, the first transistor T1, and the third transistor T3. The threshold voltage of the first transistor T1 can be compensated by the pulse width data voltage level VPWM via the diode-connected third transistor T3.

[0111] In the third cycle TP3A, the voltage level of the control electrode of the first transistor T1 can be VPWM+Vth_T1. Here, Vth_T1 can be the threshold voltage of the first transistor T1. In the third cycle TP3A, when VPWM+Vth_T1 is completely stored in the control electrode of the first transistor T1 (e.g., the first node N1), the first transistor T1 can be turned off.

[0112] In the third cycle TP3A, the fifth transistor T5 can be turned off in response to the second transmit signal EM2. Therefore, the voltage of the fourth node N4 can remain at the low initialization voltage level VinTL.

[0113] refer to Figure 10 and Figure 11 In the fourth cycle TP4A following the third cycle TP3A, the initialization signal BCB can have an active level, the first scan signal SPWM[n] can have an inactive level, the second scan signal SCCG can have an active level, the first transmit signal EM1 can have an inactive level, the second transmit signal EM2 can have an inactive level, the sweep frequency signal VSWEEP can have a high level, and the initialization voltage VINT can have a constant current voltage level VCCG.

[0114] The fourth cycle TP4A can be a constant current voltage write cycle. During the fourth cycle TP4A, the ninth transistor T9 can be turned on in response to the second scan signal SCCG. During the fourth cycle TP4A, the eighth transistor T8 can remain on.

[0115] In the fourth cycle TP4A, a constant current voltage level VCCG can be applied to the control electrode of the seventh transistor T7 through the ninth transistor T9. In the fourth cycle TP4A, when the constant current voltage level VCCG is applied to the control electrode of the seventh transistor T7, the seventh transistor T7 can be turned on.

[0116] refer to Figure 2 and Figures 4 to 10 In the fifth cycle TP5A after the fourth cycle TP4A, the initialization signal BCB can have an invalid level, the first scan signal SPWM[n] can have an invalid level, the second scan signal SCCG can have an invalid level, the first transmit signal EM1 can have an active level, the second transmit signal EM2 can have an active level, and the sweep frequency signal VSWEEP can gradually decrease from a high level.

[0117] The fifth cycle TP5A can be the emission cycle. In the fifth cycle TP5A, the fourth transistor T4 and the sixth transistor T6 can be turned on in response to the first emission signal EM1. The fifth transistor T5 can be turned on in response to the second emission signal EM2, and the seventh transistor T7 can be turned on in response to the constant current-voltage level VCCG.

[0118] In the fifth cycle TP5A, the light-emitting element EE emits light through the current flowing through the path of the sixth transistor T6, the seventh transistor T7, and the light-emitting element EE. A drive current applied to the light-emitting element EE can be generated based on a constant current-voltage level VCCG.

[0119] refer to Figure 12 and Figure 1 In the sixth cycle TP6A after the fifth cycle TP5A, the initialization signal BCB can have an invalid level, the first scan signal SPWM[n] can have an invalid level, the second scan signal SCCG can have an invalid level, the first transmit signal EM1 can have an active level, the second transmit signal EM2 can have an active level, and the sweep frequency signal VSWEEP can continue to gradually decrease after the fifth cycle TP5A.

[0120] The sixth cycle, TP6A, can be the transmit cutoff cycle. As the sweep signal VSWEEP decreases, the first transistor T1 can turn on at a specific time point. For example, a specific point could mean that the voltage at the first node N1 has an effective level of the first transistor T1. The time point at which the first transistor T1 turns on can be determined by the pulse width data voltage level VPWM applied to the control electrode of the first transistor T1.

[0121] When the first transistor T1 is turned on, the first power voltage VDD1 can be applied to the control electrode of the seventh transistor T7 through the path of the fourth transistor T4, the first transistor T1, and the fifth transistor T5.

[0122] When the first power voltage VDD1 is applied to the control electrode of the seventh transistor T7 and the seventh transistor T7 is turned off, the light-emitting element EE can stop emitting light.

[0123] refer to Figure 12 and Figure 12 In the seventh cycle TP7A following the sixth cycle TP6A, the initialization signal BCB can have an active level, the first scan signal SPWM[n] can have an inactive level, the second scan signal SCCG can have an inactive level, the first transmit signal EM1 can have an inactive level, the second transmit signal EM2 can have an inactive level, and the sweep frequency signal VSWEEP can have a high level.

[0124] The seventh cycle TP7A can be a discharge cycle. In the seventh cycle TP7A, the first electrode (e.g., the anode) of the light-emitting element EE can be initialized to the light-emitting element initialization voltage VAINT by the eighth transistor T8.

[0125] According to this embodiment, the pixel circuit may include nine transistors and two capacitors. The pixel circuit can be driven by pulse width modulation to perform internal compensation of the threshold voltage, and includes fewer transistors compared to conventional pixel circuits, allowing for high integration. Therefore, the pixel circuit can be applied to ultra-high resolution display devices.

[0126] In addition, at least one transistor in the pulse width modulation circuit PC and at least one transistor in the constant current generation circuit CC can be an N-type transistor, which can reduce power consumption.

[0127] In addition, the first transistor T1 of the pulse width modulation circuit PC and the seventh transistor T7 of the constant current generation circuit CC can be P-type transistors, which can improve mobility.

[0128] In addition, the light-emitting element initialization voltage VAINT applied to the second electrode of the eighth transistor T8 can be lower than the third power supply voltage VSS applied to the cathode of the light-emitting element EE, thereby improving the black characteristics of the pixel circuit.

[0129] In addition, the low initialization voltage level VINTL applied to the control electrode of the first transistor T1 and the constant current voltage level VCCG applied to the control electrode of the seventh transistor T7 can be output from the same voltage terminal, which allows for a reduction in the number of transistors and signal lines.

[0130] Furthermore, through the second transmit signal EM2 and the fifth transistor T5, the ninth transistor T9 can apply a low initialization voltage level VINTL to the first node N1. Therefore, the ninth transistor T9 can be both a transistor for initializing the first node N1 and a transistor for applying a constant current voltage level VCCG to the fourth node N4. This improves the integration density of the pixel circuitry.

[0131] Figure 2 It shows that it is applied to Figure 13 A timing diagram of an example of the signals of a pixel circuit.

[0132] Apart from the timing of the second scan signal SCCG in the third cycle TP3B, the driving timing of the pixel circuit according to this embodiment is consistent with the reference. Figure 1 The described driving timings are essentially the same, so the same reference numerals will be used, and any repeated explanations of the above components will be omitted.

[0133] In this embodiment, during the second cycle TP2A, the initialization voltage VINT can have a low initialization voltage level VINTL, the initialization signal BCB can have an active level, the first scan signal SPWM[n] can have an inactive level, the second scan signal SCCG can have an active level, the first transmit signal EM1 can have an inactive level, the second transmit signal EM2 can have an inactive level, and the sweep frequency signal VSWEEP can have a high level.

[0134] In the third cycle TP3B following the second cycle TP2A, the initialization voltage VINT can have a low initialization voltage level VINTL, the first scan signal SPWM[n] can have an active level, the second scan signal SCCG can have an active level, the first transmit signal EM1 can have an inactive level, the second transmit signal EM2 can have an inactive level, the sweep frequency signal VSWEEP can have a high level, and the initialization signal BCB can have an active level.

[0135] According to this embodiment, the pixel circuit may include nine transistors and two capacitors. The pixel circuit can be driven by pulse width modulation to perform internal compensation of the threshold voltage, and includes fewer transistors compared to conventional pixel circuits, allowing for high integration. Therefore, the pixel circuit can be applied to ultra-high resolution display devices.

[0136] In addition, at least one transistor in the pulse width modulation circuit PC and at least one transistor in the constant current generation circuit CC can be an N-type transistor, which can reduce power consumption.

[0137] In addition, the first transistor T1 of the pulse width modulation circuit PC and the seventh transistor T7 of the constant current generation circuit CC can be P-type transistors, which can improve mobility.

[0138] In addition, the light-emitting element initialization voltage VAINT applied to the second electrode of the eighth transistor T8 can be lower than the third power supply voltage VSS applied to the cathode of the light-emitting element EE, thereby improving the black characteristics of the pixel circuit.

[0139] In addition, the low initialization voltage level VINTL applied to the control electrode of the first transistor T1 and the constant current voltage level VCCG applied to the control electrode of the seventh transistor T7 can be output from the same voltage terminal, which allows for a reduction in the number of transistors and signal lines.

[0140] Furthermore, through the second transmit signal EM2 and the fifth transistor T5, the ninth transistor T9 can apply a low initialization voltage level VINTL to the first node N1. Therefore, the ninth transistor T9 can be both a transistor for initializing the first node N1 and a transistor for applying a constant current voltage level VCCG to the fourth node N4. This improves the integration density of the pixel circuitry.

[0141] Figure 13 It is shown Figure 13 A circuit diagram of an example of the pixel circuitry of the display panel 100.

[0142] refer to Figure 2 Apart from some differences in components of the second circuit CCA, Figure 14pixel circuit and Figure 1 The pixel circuits are essentially the same, so the same reference numerals will be used and any repeated explanations of the above components will be omitted.

[0143] The second circuit CCA may include a sixth transistor T6A and a seventh transistor T7A. The sixth transistor T6A may include a control electrode for receiving the first transmission signal EM1, a first electrode connected to the fifth node N5A, and a second electrode connected to the sixth node N6A. The seventh transistor T7A may include a control electrode connected to the fourth node N4, a first electrode for receiving the second power voltage VDD2, and a second electrode connected to the fifth node N5A. The first electrode of the light-emitting element EE may be connected to the sixth node N6A.

[0144] According to this embodiment, the pixel circuit may include nine transistors and two capacitors. The pixel circuit can be driven by pulse width modulation to perform internal compensation of the threshold voltage, and includes fewer transistors compared to conventional pixel circuits, allowing for high integration. Therefore, the pixel circuit can be applied to ultra-high resolution display devices.

[0145] In addition, at least one transistor in the pulse width modulation circuit PC and at least one transistor in the constant current generation circuit CC can be an N-type transistor, which can reduce power consumption.

[0146] In addition, the first transistor T1 of the pulse width modulation circuit PC and the seventh transistor T7 of the constant current generation circuit CC can be P-type transistors, which can improve mobility.

[0147] In addition, the light-emitting element initialization voltage VAINT applied to the second electrode of the eighth transistor T8 can be lower than the third power supply voltage VSS applied to the cathode of the light-emitting element EE, thereby improving the black characteristics of the pixel circuit.

[0148] In addition, the low initialization voltage level VINTL applied to the control electrode of the first transistor T1 and the constant current voltage level VCCG applied to the control electrode of the seventh transistor T7 can be output from the same voltage terminal, which allows for a reduction in the number of transistors and signal lines.

[0149] Furthermore, through the second transmit signal EM2 and the fifth transistor T5, the ninth transistor T9 can apply a low initialization voltage level VINTL to the first node N1. Therefore, the ninth transistor T9 can be both a transistor for initializing the first node N1 and a transistor for applying a constant current voltage level VCCG to the fourth node N4. This improves the integration density of the pixel circuitry.

[0150] Figure 14 It is shownFigure 14 A circuit diagram of an example of the pixel circuitry of the display panel 100.

[0151] refer to Figure 2 Except for the fourth transistor T4 and the sixth transistor T6, which are N-type transistors, Figure 2 pixel circuit and Figure 15 The pixel circuits are essentially the same, so the same reference numerals will be used and any repeated explanations of the above components will be omitted.

[0152] In this embodiment, the pixel circuit may include a first circuit PCB and a second circuit CCB. In this embodiment, the fourth transistor T4 and the sixth transistor T6 may be N-type transistors. Therefore, current leakage can be further reduced, allowing the pixel circuit to operate more stably. Additionally, the power consumption of the display device can be further reduced.

[0153] Figure 16 It is shown Figure 15 A circuit diagram of an example of the pixel circuitry of the display panel 100.

[0154] refer to Figure 15 In addition to the third power supply voltage VSS being applied to the first electrode of the eighth transistor T8, Figure 1 pixel circuit and Figure 16 The pixel circuits are essentially the same, so the same reference numerals will be used and any repeated explanations of the above components will be omitted.

[0155] In this embodiment, the pixel circuit may include a first circuit PC and a second circuit CCC. In this embodiment, the first electrode of the eighth transistor T8 may receive a third power supply voltage VSS instead of... Figure 1 The initial voltage VAINT of the light-emitting element is adjusted. Therefore, the number of lines connected to the pixel circuit can be reduced. This allows for further improvement in the integration of the display device.

[0156] Figure 1 This is a block diagram illustrating an electronic device 1000 according to one or more embodiments of the present disclosure. Figure 1 It is shown that Figure 16 A diagram illustrating an example of an electronic device 1000 implemented as a smartphone.

[0157] refer to ​ The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may be... ​The display device. Furthermore, the electronic device 1000 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (USB) devices, other electronic devices, etc.

[0158] In one or more embodiments, such as ​ As shown, electronic device 1000 can be implemented as a smartphone. However, electronic device 1000 is not limited to this. For example, electronic device 1000 can be implemented as a cellular phone, video phone, smartboard, smartwatch, tablet PC, car navigation system, computer display, laptop computer, head-mounted display (HMD) device, television (TV), etc.

[0159] Processor 1010 can perform various computing functions or tasks. Processor 1010 can be a microprocessor, central processing unit (CPU), application processor (AP), etc. Processor 1010 can be connected to other components via address bus, control bus, data bus, etc. In addition, processor 1010 can be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0160] Processor 1010 can ​ Input image data IMG, application launch signal (app-on signal) APPON and ​ The input control signal CONT is output to ​ The drive controller 200.

[0161] The memory device 1020 can store data for the operation of the electronic device 1000. For example, the memory device 1020 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.).

[0162] Storage device 1030 may include solid-state drive (SSD) devices, hard disk drive (HDD) devices, CD-ROM devices, etc. I / O device 1040 may include input devices such as keyboards, keypads, mice, touchpads, touchscreens, etc., and output devices such as printers, speakers, etc. In some embodiments, display device 1060 may be included in I / O device 1040. Power supply 1050 provides power for the operation of electronic device 1000. Display device 1060 may be connected to other components via a bus or other communication link.

[0163] refer to ​ The electronic device 1000 disclosed herein is shown as being implemented as a smartphone, but the disclosure is not limited thereto. The electronic device 1000 may be a television, monitor, laptop computer, and / or tablet computer. Furthermore, the electronic device 1000 may be used in an automobile.

[0164] The display device according to the embodiments can be applied to display devices including computers, laptops, mobile phones, smartphones, smart boards, PMPs, PDAs, MP3 players, etc.

[0165] The foregoing is illustrative of this disclosure and should not be construed as limiting it. Although several embodiments of this disclosure have been described, those skilled in the art will readily understand that many modifications may be made to the embodiments without substantially departing from the novel teachings and aspects of this disclosure. Therefore, all such modifications are intended to be included within the scope of this disclosure as defined in the claims. In the claims, the clauses for "device plus function" are intended to cover structures performing the functions described herein, and not only structural equivalents but also equivalent structures. Therefore, it should be understood that the foregoing is illustrative of this disclosure and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims and their equivalents. This disclosure is defined by the appended claims and their equivalents included therein.

Claims

1. A pixel circuit, characterized in that, The pixel circuit includes: The first transistor includes a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; The second transistor is configured to apply a data voltage to the first transistor; A third transistor is connected to the first node and the third node; A fourth transistor is configured to apply a first power voltage to the second node in response to a first transmit signal; The fifth transistor is configured to apply a voltage of the fourth node to the third node in response to a second transmission signal different from the first transmission signal; The seventh transistor is configured to apply a drive current to the light-emitting element and is connected to the fourth node; The ninth transistor is configured to apply an initialization voltage to the fourth node; and The light-emitting element is configured to emit light based on the driving current. The initialization voltage has a low initialization voltage level or a constant current voltage level, and Wherein, the first transistor is a P-type transistor, the second transistor is an N-type transistor, the third transistor is an N-type transistor, and the seventh transistor is a P-type transistor.

2. The pixel circuit according to claim 1, characterized in that, The ninth transistor includes a control electrode configured to receive a second scan signal, a first electrode configured to receive the initialization voltage, and a second electrode connected to the fourth node.

3. The pixel circuit according to claim 1, characterized in that, The pixel circuit further includes a first capacitor, which includes a first electrode configured to receive a sweep frequency signal and a second electrode connected to the first node.

4. The pixel circuit according to claim 1, characterized in that, The pixel circuit further includes an eighth transistor, which includes a control electrode configured to receive an initialization signal, a first electrode configured to receive an initialization voltage for the light-emitting element, and a second electrode connected to the light-emitting element.

5. The pixel circuit according to claim 1, characterized in that, The pixel circuit further includes a sixth transistor, which includes a control electrode configured to receive the first transmitted signal, a first electrode configured to receive a second electrical voltage, and a second electrode connected to the seventh transistor.

6. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes a second capacitor, which includes a first electrode that receives a second electrical voltage and a second electrode connected to the fourth node.

7. The pixel circuit according to claim 1, characterized in that, The second transistor includes a control electrode configured to receive a first scan signal, a first electrode configured to receive the data voltage, and a second electrode connected to the second node. The third transistor includes a control electrode configured to receive the first scan signal, a first electrode connected to the first node, and a second electrode connected to the third node. The seventh transistor includes a control electrode connected to the fourth node, a first electrode connected to the fifth node, and a second electrode connected to the light-emitting element.

8. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes a first capacitor, a second capacitor, a sixth transistor, and an eighth transistor. The second transistor includes a control electrode configured to receive a first scan signal, a first electrode configured to receive the data voltage, and a second electrode connected to the second node. The third transistor includes a control electrode configured to receive the first scan signal, a first electrode connected to the first node, and a second electrode connected to the third node. The fourth transistor includes a control electrode configured to receive the first transmitted signal, a first electrode configured to receive the first power voltage, and a second electrode connected to the second node. The fifth transistor includes a control electrode configured to receive the second transmitted signal, a first electrode connected to the third node, and a second electrode connected to the fourth node. The sixth transistor includes a control electrode configured to receive the first transmitted signal, a first electrode connected to the fifth node, and a second electrode connected to the sixth node. The seventh transistor includes a control electrode connected to the fourth node, a first electrode configured to receive a second power voltage, and a second electrode connected to the fifth node. The eighth transistor includes a control electrode configured to receive an initialization signal, a first electrode configured to receive an initialization voltage for a light-emitting element, and a second electrode connected to the sixth node. The ninth transistor includes a control electrode configured to receive a second scan signal, a first electrode configured to receive the initialization voltage, and a second electrode connected to the fourth node. The first capacitor includes a first electrode configured to receive a swept frequency signal and a second electrode connected to the first node. The second capacitor includes a first electrode configured to receive the second electrical voltage and a second electrode connected to the fourth node. The light-emitting element includes a first electrode connected to the sixth node and a second electrode configured to receive a third electrical voltage.

9. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes a first capacitor, a second capacitor, a sixth transistor, and an eighth transistor. The second transistor includes a control electrode configured to receive a first scan signal, a first electrode configured to receive the data voltage, and a second electrode connected to the second node. The third transistor includes a control electrode configured to receive the first scan signal, a first electrode connected to the first node, and a second electrode connected to the third node. The fourth transistor includes a control electrode configured to receive the first transmitted signal, a first electrode configured to receive the first power voltage, and a second electrode connected to the second node. The fifth transistor includes a control electrode configured to receive the second transmitted signal, a first electrode connected to the third node, and a second electrode connected to the fourth node. The sixth transistor includes a control electrode configured to receive the first transmitted signal, a first electrode configured to receive a second electrical voltage, and a second electrode connected to the fifth node. The seventh transistor includes a control electrode connected to the fourth node, a first electrode connected to the fifth node, and a second electrode connected to the sixth node. The eighth transistor includes a control electrode configured to receive an initialization signal, a first electrode configured to receive an initialization voltage for a light-emitting element, and a second electrode connected to the sixth node. The ninth transistor includes a control electrode configured to receive a second scan signal, a first electrode configured to receive the initialization voltage, and a second electrode connected to the fourth node. The first capacitor includes a first electrode configured to receive a swept frequency signal and a second electrode connected to the first node. The second capacitor includes a first electrode configured to receive the second electrical voltage and a second electrode connected to the fourth node. The light-emitting element includes a first electrode connected to the sixth node and a second electrode configured to receive a third electrical voltage.

10. The pixel circuit according to claim 9, characterized in that, The fourth, fifth, sixth, and eighth transistors are P-type transistors, and the ninth transistor is an N-type transistor.

11. The pixel circuit according to claim 9, characterized in that, The fifth and eighth transistors are P-type transistors, and the fourth, sixth, and ninth transistors are N-type transistors.

12. The pixel circuit according to claim 9, characterized in that, The initial voltage of the light-emitting element is the third power voltage.

13. The pixel circuit according to claim 9, characterized in that, In the first cycle, the initialization voltage has the low initialization voltage level, the first scan signal has an active level, the second scan signal has an active level, the first transmit signal has an inactive level, the second transmit signal has an active level, and the initialization signal has an active level. During the first cycle, the third transistor, the fifth transistor, the eighth transistor, and the ninth transistor are turned on, while the fourth transistor is turned off.

14. The pixel circuit according to claim 13, characterized in that, In the second cycle following the first cycle, the initialization voltage has the low initialization voltage level, the first scan signal has an invalid level, the second scan signal has the valid level, the first transmit signal has the invalid level, and the second transmit signal has an invalid level. During the second cycle, the ninth transistor is turned on, and the fifth transistor is turned off.

15. The pixel circuit according to claim 14, characterized in that, In the third cycle following the second cycle, the first scan signal has the active level, and the second transmit signal has the inactive level. In the third cycle, the second transistor and the third transistor are turned on, and the fifth transistor is turned off.

16. The pixel circuit according to claim 15, characterized in that, In the fourth cycle following the third cycle, the initialization voltage has the constant current voltage level, the second scan signal has the active level, and the second transmit signal has the inactive level. In the fourth cycle, the ninth transistor is turned on and the fifth transistor is turned off.

17. The pixel circuit according to claim 16, characterized in that, In the fifth cycle following the fourth cycle, the frequency sweep signal gradually decreases from a high level, and the first transmitted signal has an effective level. During the fifth cycle, the sixth transistor and the seventh transistor are turned on.

18. The pixel circuit according to claim 17, characterized in that, In the sixth cycle following the fifth cycle, the frequency sweep signal gradually decreases, and the second transmitted signal has the effective level, and In the sixth cycle, the first transistor and the fifth transistor are turned on, and the seventh transistor is turned off.

19. The pixel circuit according to claim 18, characterized in that, In the seventh cycle following the sixth cycle, the sweep signal has the high level, the first transmit signal has the invalid level, the second transmit signal has the invalid level, and the initialization signal has the valid level. During the seventh cycle, the eighth transistor is turned on.

20. A display device, characterized in that, The display device includes: Display panel, including pixel circuitry; A gate driver configured to apply a gate signal to the pixel circuit; A transmit driver, configured to apply a transmit signal to the pixel circuit; and A data driver, configured to apply a data voltage to the pixel circuitry, The pixel circuit includes: The first transistor includes a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; The second transistor is configured to apply the data voltage to the first transistor; A third transistor is connected to the first node and the third node; A fourth transistor is configured to apply a first power voltage to the second node in response to a first transmit signal; The fifth transistor is configured to apply a voltage of the fourth node to the third node in response to a second transmission signal different from the first transmission signal; The seventh transistor is configured to apply a drive current to the light-emitting element and is connected to the fourth node; The ninth transistor is configured to apply an initialization voltage to the fourth node; and The light-emitting element is configured to emit light based on the driving current. The initialization voltage has a low initialization voltage level or a constant current voltage level, and Wherein, the first transistor is a P-type transistor, the second transistor is an N-type transistor, the third transistor is an N-type transistor, and the seventh transistor is a P-type transistor.

21. An electronic device, including a display device, characterized in that, The display device includes: a display panel, including pixel circuitry; and The display driver is configured to drive the display panel. The pixel circuit includes: The first transistor includes a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; The second transistor is configured to apply a data voltage to the first transistor; A third transistor is connected to the first node and the third node; A fourth transistor is configured to apply a first power voltage to the second node in response to a first transmit signal; The fifth transistor is configured to apply a voltage of the fourth node to the third node in response to a second transmission signal different from the first transmission signal; The seventh transistor is configured to apply a drive current to the light-emitting element and is connected to the fourth node; The ninth transistor is configured to apply an initialization voltage to the fourth node; and The light-emitting element is configured to emit light based on the driving current. The initialization voltage has a low initialization voltage level or a constant current voltage level, and Wherein, the first transistor is a P-type transistor, the second transistor is an N-type transistor, the third transistor is an N-type transistor, and the seventh transistor is a P-type transistor.

22. The electronic device according to claim 21, characterized in that, The electronic devices include cellular phones, video phones, smart panels, televisions, smartwatches, car navigation systems, computer displays, laptop computers, or head-mounted display devices.

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