LED chip
By introducing a dam structure on the outside of the epitaxial unit in the LED chip, the problems of edge and corner chipping during the cutting and film-making process of the epitaxial unit are solved, thereby improving the light extraction efficiency and reliability of the LED chip.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2026-04-07
AI Technical Summary
During the LED chip manufacturing process, the epitaxial unit is prone to problems such as edge chipping and corner chipping due to the pressure of the supporting film during cutting and film flipping, resulting in abnormal appearance.
In the design of LED chips, a dam structure is introduced on the outside of the epitaxial unit to share the lateral force applied to the edge of the epitaxial unit, alleviate the pressure effect, and define the cutting position during the cutting process to block metal sputtering.
It effectively reduces edge and corner chipping problems caused by pressure on epitaxial cells, reduces appearance abnormalities, improves light extraction efficiency, and reduces leakage current caused by metal sputtering.
Smart Images
Figure CN224098074U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of LED technology, and more particularly to an LED chip. Background Technology
[0002] Light-emitting diodes (LEDs), as a new generation of lighting source, have many advantages such as high efficiency, energy saving, environmental friendliness, and long lifespan, and are widely used in lighting, displays, backlighting, and other fields. With continuous technological advancements and sustained market demand growth, the LED industry has developed rapidly, and its manufacturing processes and technologies are constantly being innovated and improved. However, many technical challenges still exist in the LED manufacturing process, with edge chipping being one of them. Utility Model Content
[0003] In view of the above problems, this application provides an LED chip to reduce edge chipping during the LED chip manufacturing process. The specific solution is as follows:
[0004] An LED chip, comprising:
[0005] A first substrate, the surface of the first substrate having a first region and a second region surrounding the first region;
[0006] An epitaxial cell located in a first region of the first substrate and a dam structure located in a second region of the first substrate, wherein the epitaxial cell includes a stacked P-type semiconductor layer, a quantum well active layer and an N-type semiconductor layer, and in a first direction, the dam structure is located in at least a portion of the region outside the epitaxial cell, and there is a gap between the dam structure and the epitaxial cell, wherein the first direction is parallel to the plane of the first substrate.
[0007] The P electrode is located on the side of the first substrate away from the epitaxial unit.
[0008] Optionally, the dam structure is arranged around the perimeter of the extension unit.
[0009] Optionally, the dam structure is composed of multiple columnar units, and the distance between adjacent columnar units is not less than 3 micrometers.
[0010] Optionally, in the first direction, the distance between the dam structure and the extension unit is not less than 3 micrometers and not greater than the width of the second region.
[0011] Optionally, in the first direction, the width of the dam structure is greater than 5 micrometers.
[0012] Optionally, the P-type semiconductor layer includes a P-type confinement layer located on the side of the quantum well active layer away from the N-type semiconductor layer; the LED chip further includes a P-type window layer located on the side of the P-type semiconductor layer away from the quantum well active layer.
[0013] Optionally, it may also include an omnidirectional reflective layer located between the P-type window layer and the first substrate.
[0014] Optionally, the omnidirectional reflective layer includes:
[0015] A first ohmic contact layer is located on the surface of the P-type window layer facing the first substrate. The first ohmic contact layer covers the third region of the P-type window layer and exposes the fourth region of the P-type window layer.
[0016] A dielectric layer located on the surface of the first ohmic contact layer facing the first substrate, the dielectric layer having a plurality of through holes, the through holes exposing a portion of the first ohmic contact layer;
[0017] The conductive filler located within the through hole;
[0018] A mirror layer located on the side of the dielectric layer facing the first substrate, the mirror layer being a conductive layer and electrically connected to the conductive filler;
[0019] The P electrode is electrically connected to the P-type semiconductor layer through the first substrate, the mirror layer, the conductive filler, and the first ohmic contact layer.
[0020] Optionally, the dielectric layer includes a first constituent layer, a second constituent layer and a third constituent layer stacked together, wherein the first constituent layer is an ITO layer or an IZO layer or an Al2O3 layer, the second constituent layer is a SiO2 layer, and the third constituent layer is an Al2O3 layer or an ITO layer or an IZO layer.
[0021] The conductive filler includes stacked Au layers, Zn layers and Au layers, or includes stacked Au layers, Be layers and Au layers;
[0022] The mirror layer comprises stacked Ag, TiW, Ti, Pt, and Au layers.
[0023] Optionally, the N-type semiconductor layer includes an N-type confinement layer located on the side of the quantum well active layer away from the P-type semiconductor layer, and an N-type roughening layer located on the side of the N-type confinement layer away from the quantum well active layer.
[0024] The LED chip provided in this application embodiment includes, in addition to the epitaxial unit located in the first region of the first substrate, a dam structure located in the second region of the first substrate. In a plane parallel to the first substrate, the dam structure is located in at least a portion of the outer side of the epitaxial unit. Thus, during the replacement of the carrier film at the bottom of the LED chip using a lamination process, the dam structure can be used to share the lateral force applied to the edge of the epitaxial unit, thereby reducing the possibility of the epitaxial unit being damaged by pressure, alleviating problems such as edge chipping and corner chipping during the LED chip manufacturing process, and reducing abnormal appearance. Attached Figure Description
[0025] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.
[0026] Figure 1 This application provides a schematic diagram of the structure of an LED chip;
[0027] Figure 2 A schematic diagram of another LED chip provided in this application;
[0028] Figure 3 A top view of an LED chip provided in this application;
[0029] Figure 4 A top view of an LED chip provided in this application;
[0030] Figure 5 A flowchart illustrating a method for manufacturing an LED chip provided in this application;
[0031] Figures 6-15 This is a schematic diagram of some of the structures involved in the manufacturing process of an LED chip provided in this application. Detailed Implementation
[0032] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0033] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.
[0034] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0035] As described in the background section, there are still many technical challenges in the LED manufacturing process, one of which is edge chipping.
[0036] This is because LED manufacturing involves cutting an LED structure containing multiple LED chips into multiple independent LED chips. During the cutting process, cutting marks are created on the carrier film on the back of the LED chip that supports the LED chip. Therefore, a flipping process is needed to replace the carrier film on the back of the LED chip with a new carrier film. Specifically, the flipping process of the LED chip includes: attaching a carrier film to the front of the LED chip using a lamination process. The LED chip includes a substrate and an epitaxial structure, with the epitaxial structure located in a portion of the front of the substrate, and a height difference existing between the surface of the epitaxial structure and the surface of the substrate; flipping the LED chip to remove the carrier film on the back of the LED chip; attaching another carrier film to the back of the LED chip using a lamination process; and finally removing the carrier film on the front of the LED chip, completing the replacement of the carrier film on the back of the LED chip.
[0037] Because of the height difference between the surface of the epitaxial structure and the surface of the substrate, during the process of bonding the carrier film to the front or back of the LED chip using the lamination process, the edge area of the epitaxial structure may be damaged due to pressure, resulting in problems such as edge chipping and corner chipping.
[0038] In view of this, embodiments of this application provide an LED chip, such as... Figure 1 As shown, the LED chip includes:
[0039] A first substrate 10, the surface of the first substrate 10 having a first region and a second region surrounding the first region;
[0040] The epitaxial unit 21 located in the first region of the first substrate 10 and the dam structure 22 located in the second region of the first substrate 10, as shown in... Figure 2As shown, the epitaxial unit 21 includes a stacked P-type semiconductor layer 211, a quantum well active layer 212, and an N-type semiconductor layer 213. In the first direction X, the dam structure 22 is located at least in a portion of the outer side of the epitaxial unit 21, and there is a gap between the dam structure 22 and the epitaxial unit 21. The first direction X is parallel to the plane where the first substrate 10 is located.
[0041] The P electrode 30 is located on the side of the first substrate 10 away from the epitaxial unit 21.
[0042] Optionally, in one embodiment of this application, the LED chip further includes a first carrier film 40 located on the side of the P electrode 30 away from the first substrate 10. Optionally, the first carrier film can be a blue film, a white film, or other types of carrier films. This application does not limit this, and it depends on the specific circumstances.
[0043] The LED chip provided in this application embodiment includes, in addition to the epitaxial unit located in the first region of the first substrate, a dam structure located in the second region of the first substrate. In a plane parallel to the first substrate, the dam structure is located at least in a portion of the outer side of the epitaxial unit. Thus, during the replacement of the carrier film at the bottom of the LED chip using a lamination process, the dam structure can be used to share the lateral force applied to the edge of the epitaxial unit, thereby reducing the possibility of the epitaxial unit being damaged by pressure, alleviating problems such as edge chipping and corner chipping during the LED chip manufacturing process, and reducing appearance abnormalities.
[0044] Optionally, in one embodiment of this application, such as Figure 3 As shown, in a plane parallel to the plane of the first substrate 10, the dam structure 22 is arranged around the epitaxial unit 21. During the replacement of the carrier film at the bottom of the LED chip using a lamination process, the dam structure 22 can distribute the lateral force applied to the edge of the epitaxial unit 21, protecting each side of the epitaxial unit 21 and further reducing the risk of damage due to pressure. This alleviates problems such as edge chipping and corner breakage during LED chip manufacturing. The lateral force applied to the edge of the epitaxial unit refers to a force applied to the edge of the epitaxial unit at an angle greater than 0° and less than 90° to the direction perpendicular to the plane of the first substrate.
[0045] In another embodiment of this application, such as Figure 4As shown, the dam structure 22 is composed of multiple columnar units 221, and the distance between adjacent columnar units 221 is not less than 3 micrometers. Therefore, during the replacement of the carrier film at the bottom of the LED chip using a lamination process, the multiple columnar units 221 can share the lateral force applied to the edge of the epitaxial unit 21. Optionally, the columnar units 221 can be arranged around the epitaxial unit 21, using multiple columnar units 221 to protect each side of the epitaxial unit 21, further reducing the possibility of the epitaxial unit 21 being damaged by pressure, and alleviating problems such as edge chipping and corner breakage during LED chip manufacturing.
[0046] Based on any of the above embodiments, in one embodiment of this application, in the first direction, the distance between the dam structure and the epitaxial unit is not less than 3 micrometers and not greater than the width of the second region, so as to avoid the dam structure and the epitaxial unit becoming too small, increasing the manufacturing difficulty. It should be noted that in this embodiment, the second region of the first substrate is the region where the dicing channel is located in a conventional LED chip, and the width of the second region is the width of the dicing channel in a conventional LED chip, so that the addition of the dam structure does not increase the size of the LED chip in the first direction. However, this application does not limit this, and it depends on the specific situation.
[0047] Based on any of the above embodiments, in one embodiment of this application, the width of the dam structure in the first direction is greater than 5 micrometers, so that during the replacement of the carrier film at the bottom of the LED chip using the lamination process, the dam structure can provide sufficient support for the force applied to the epitaxial unit, better share the lateral force applied to the edge of the epitaxial unit 21, thereby effectively protecting each side of the epitaxial unit using the dam structure, further reducing the possibility of the epitaxial unit being crushed by pressure, and alleviating problems such as edge chipping and corner chipping during the LED chip manufacturing process. However, this application does not limit this, and it depends on the specific circumstances.
[0048] Based on any of the above embodiments, in one embodiment of this application, the following continues... Figure 2As shown, the P-type semiconductor layer 211 includes a P-type confinement layer located on the side of the quantum well active layer 212 away from the N-type semiconductor layer 213; the N-type semiconductor layer 213 includes an N-type confinement layer 2131 located on the side of the quantum well active layer 212 away from the P-type semiconductor layer 211 and an N-type roughening layer 2132 located on the side of the N-type confinement layer 2131 away from the quantum well active layer 212. The P-type confinement layer, the quantum well active layer, and the N-type confinement layer constitute the light-emitting layer of the LED chip, used to generate light. The N-type roughening layer is used to change the angle of light emitted from the light-emitting layer that travels to the surface of the N-type roughening layer, increasing the light emission efficiency of the epitaxial unit, thereby improving the light extraction efficiency of the LED chip.
[0049] Optionally, based on the above embodiments, in one embodiment of this application, the following continues... Figure 2 As shown, the LED chip further includes a P-type window layer 50 located on the side of the P-type semiconductor layer 211 away from the quantum well active layer 212, to form a low-resistance path on the side of the P-type semiconductor layer 211 away from the quantum well active layer 212, thereby laterally diffusing the current provided by the P electrode 30 at the interface between the P-type window layer 50 and the P-type semiconductor layer 211 to the entire P-type semiconductor layer 211, reducing the current density gradient. Optionally, in one embodiment of this application, the P-type window layer can be a P-type doped GaP layer with a doping concentration of 2×10⁻⁶. 18 cm -3 However, this application does not impose any restrictions on this, and it depends on the specific circumstances.
[0050] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 2 As shown, the LED chip further includes an omnidirectional reflective layer 60 located between the P-type window layer 50 and the first substrate 10, so as to reflect at least part of the light emitted from the side of the P-type window layer 50 away from the quantum well active layer 212 back to the side of the N-type confinement layer 2131 away from the quantum well active layer 212, that is, to reflect at least part of the light from the non-light-emitting side of the LED chip back to the light-emitting side of the LED chip, thereby improving the light extraction efficiency of the LED chip.
[0051] Optionally, in one embodiment of this application, the omnidirectional reflective layer 60 includes:
[0052] A first ohmic contact layer 61 is located on the surface of the P-type window layer 50 facing the first substrate 10. The first ohmic contact layer 61 covers the third region of the P-type window layer 50 and exposes the fourth region of the P-type window layer 50.
[0053] A dielectric layer 62 is located on the surface of the first ohmic contact layer 61 facing the first substrate 10. The dielectric layer 62 has a plurality of through holes, and the through holes expose a portion of the first ohmic contact layer 61.
[0054] The conductive filler 63 is located within the through hole;
[0055] A mirror layer 64 is located on the side of the dielectric layer 62 facing the first substrate 10. The mirror layer 64 is a conductive layer and is electrically connected to the conductive filler 63.
[0056] It should be noted that, in this embodiment, the P electrode 30 is electrically connected to the P-type semiconductor layer 211 in sequence through the first substrate 10, the mirror layer 64, the conductive filler 63 and the first ohmic contact layer 61.
[0057] Specifically, in one embodiment of this application, the first ohmic contact layer can be a P-type doped GaP layer. When both the first ohmic contact layer and the P-type window layer are P-type doped GaP layers, the doping concentration of the first ohmic contact layer is greater than the doping concentration of the P-type window layer, so as to reduce the resistance of the first ohmic contact layer.
[0058] It should be noted that the P-type GaP layer has a certain light absorption effect. In this embodiment, the first ohmic contact layer covers the third region of the P-type window layer and exposes the fourth region of the P-type window layer. This can reduce the light absorption of the first ohmic contact layer by using the first ohmic contact layer to electrically connect the conductive filler and the P-type window layer, thereby reducing the impact of the first ohmic contact layer on the light extraction efficiency of the LED chip.
[0059] Optionally, in one embodiment of this application, the third region includes multiple sub-regions, the fourth region includes multiple sub-regions, and the sub-regions of the third region and the fourth region are arranged alternately. However, this application does not limit this arrangement and it depends on the specific circumstances.
[0060] Based on any of the above embodiments, in one embodiment of this application, the dielectric layer includes a stacked first constituent layer, a second constituent layer, and a third constituent layer, wherein the first constituent layer is an ITO layer, an IZO layer, or an Al2O3 layer, the second constituent layer is a SiO2 layer, and the third constituent layer is an Al2O3 layer, an ITO layer, or an IZO layer; the conductive filler may include a stacked Au layer, a Zn layer, and an Au layer, or it may include a stacked Au layer, a Be layer, and an Au layer; the mirror layer includes a stacked Ag layer, a TiW layer, a Ti layer, a Pt layer, and an Au layer. However, this application does not limit this, and the specific method depends on the circumstances.
[0061] Optionally, in one embodiment of this application, the first substrate 10 and the mirror layer 64 are bonded together by a metal bonding layer 70 to achieve a fixed connection between the first substrate 10 and the omnidirectional reflective layer 60.
[0062] Based on any of the above embodiments, in one embodiment of this application, the LED chip further includes: a second ohmic contact layer 80 located in a portion of the epitaxial unit 21 away from the first substrate 10, and an N electrode 90 electrically connected to the second ohmic contact layer 80 and the N-type semiconductor layer 213.
[0063] In summary, in the LED chip provided in this application embodiment, at least a portion of the outer side of the epitaxial unit has a dam structure. Thus, during the replacement of the carrier film at the bottom of the LED chip using a lamination process, the dam structure can be used to share the lateral force applied to the edge of the epitaxial unit, thereby reducing the possibility of the epitaxial unit being damaged by pressure, alleviating problems such as edge chipping and corner chipping during the LED chip manufacturing process, and reducing appearance abnormalities.
[0064] Furthermore, in the LED chip provided in this application embodiment, at least a portion of the outer side of the epitaxial unit has a dam structure. During the process of cleaving the first substrate from the side away from the P electrode of the first carrier film to form multiple LED chips, the position of the dam structure is used to define the cutting position, so that the cutting position is located on the side of the dam structure away from the epitaxial unit. Thus, when cleaving the first substrate from the side away from the P electrode of the first carrier film, the dam structure is used to block the metal sputtering generated by laser cutting, so as to effectively reduce the leakage current ratio of the LED chip caused by metal sputtering generated by laser cutting.
[0065] Accordingly, embodiments of this application also provide a method for manufacturing an LED chip, such as... Figure 5 As shown, the manufacturing method includes:
[0066] S1: An epitaxial layer is formed on the surface of a semiconductor substrate, the epitaxial layer comprising a stacked N-type semiconductor layer, a quantum well active layer, and a P-type semiconductor layer.
[0067] Optionally, in one embodiment of this application, the P-type semiconductor layer includes a P-type confinement layer, and the N-type semiconductor layer includes an N-type roughening layer and an N-type confinement layer. In this embodiment, as shown... Figure 6 As shown, forming an epitaxial layer on the surface of the semiconductor substrate 100 includes:
[0068] A buffer layer 101 is formed on the surface of the semiconductor substrate 100. Optionally, the semiconductor substrate 100 is a GaAs substrate and the buffer layer 101 is a GaAs buffer layer.
[0069] A corrosion-stopping layer 102 is formed on the surface of the buffer layer 101 away from the semiconductor substrate 100;
[0070] A second ohmic contact layer 80 is formed on the side of the corrosion stop layer 102 away from the buffer layer 101. Optionally, the second ohmic contact layer 80 is a GaAs ohmic contact layer.
[0071] An N-type roughening layer 2132 is formed on the side of the second ohmic contact layer 80 away from the corrosion stop layer 102;
[0072] An N-type confinement layer 2131 is formed on the side of the N-type roughened layer 2132 away from the second ohmic contact layer 80;
[0073] A quantum well active layer 212 is formed on the side of the N-type confinement layer 2131 away from the N-type roughening layer 2132;
[0074] A P-type semiconductor layer 211 is formed on the side of the quantum well active layer 212 away from the N-type confinement layer 2131, and the P-type semiconductor layer includes the P-type confinement layer.
[0075] Optionally, in one embodiment of this application, the epitaxial layer is formed by a deposition process, but this application does not limit this process and it depends on the specific circumstances.
[0076] Based on the above embodiments, in one embodiment of this application, such as Figure 7 As shown, the method further includes: forming a P-type window layer 50 on the side of the epitaxial layer away from the semiconductor substrate 100. Optionally, the P-type window layer 50 is a P-type doped GaP layer with a doping concentration of 2 × 10⁻⁶. 18 cm -3 However, this application does not impose any restrictions on this, and it depends on the specific circumstances.
[0077] Based on any of the above embodiments, in one embodiment of this application, before fixing the side of the epitaxial layer away from the semiconductor substrate to the first substrate, such as... Figure 8As shown, the method further includes: forming an omnidirectional reflective layer 60 on the side of the P-type semiconductor layer 211 away from the quantum well active layer 212, so as to reflect at least part of the light emitted from the side of the P-type window layer 50 or the P-type semiconductor layer 211 away from the quantum well active layer 212 back to the side of the N-type confinement layer 2131 away from the quantum well active layer 212, that is, to reflect at least part of the light from the non-light-emitting side of the LED chip back to the light-emitting side of the LED chip, thereby improving the light extraction efficiency of the LED chip.
[0078] Optionally, in one embodiment of this application, the following continues... Figure 8 As shown, forming an omnidirectional reflective layer 60 on the side of the P-type semiconductor layer 211 away from the quantum well active layer 212 includes:
[0079] A first ohmic contact layer 61 is formed on the surface of the P-type window layer 50 away from the semiconductor substrate 100. The first ohmic contact layer 61 covers the third region of the P-type window layer 50 and exposes the fourth region of the P-type window layer 50.
[0080] A dielectric layer 62 is formed on the surface of the first ohmic contact layer 61 away from the semiconductor substrate 100. The dielectric layer 62 has a plurality of through holes, and the through holes expose a portion of the first ohmic contact layer 61.
[0081] A conductive filler 63 is formed inside the through hole;
[0082] A mirror layer 64 is formed on the side of the dielectric layer 62 away from the semiconductor substrate 100. The mirror layer 64 is a conductive layer and is electrically connected to the conductive filler 63.
[0083] Optionally, based on the above embodiments, in one embodiment of this application, the first ohmic contact layer may be a p-type doped GaP layer, and the doping concentration of the first ohmic contact layer is greater than the doping concentration of the p-type window layer; in this embodiment, a first ohmic contact layer is formed on the surface of the p-type window layer away from the semiconductor substrate, the first ohmic contact layer covers a third region of the p-type window layer, and the fourth region of the p-type window layer is exposed, including:
[0084] A first ohmic contact layer is formed on the side of the P-type window layer away from the epitaxial layer, covering the surface of the P-type window layer.
[0085] The first ohmic contact layer is etched so that it covers the third region of the P-type window layer and exposes the fourth region of the P-type window layer.
[0086] Specifically, in one embodiment of this application, the first ohmic contact layer is etched such that the first ohmic contact layer covers the third region of the P-type window layer, and the fourth region of the P-type window layer is exposed, including:
[0087] The surface of the first ohmic contact layer was cleaned using acetone, isopropanol, deionized water, etc.
[0088] A first photoresist pattern is formed on the surface of the first ohmic contact layer;
[0089] Using the first photoresist pattern as a mask, a wet or dry etching method is used to remove the portion of the first ohmic contact layer that covers the fourth region of the P-type window layer, so that the first ohmic contact layer only covers the third region of the P-type window layer, exposing the fourth region of the P-type window layer.
[0090] Remove the first photoresist pattern.
[0091] Optionally, in one embodiment of this application, the dielectric layer includes a stacked first constituent layer, a second constituent layer, and a third constituent layer, wherein the first constituent layer is an ITO layer, an IZO layer, or an Al2O3 layer, the second constituent layer is a SiO2 layer, and the third constituent layer is an Al2O3 layer, an ITO layer, or an IZO layer. In this embodiment, a dielectric layer is formed on the surface of the first ohmic contact layer away from the semiconductor substrate, and the dielectric layer has a plurality of vias, the vias exposing a portion of the first ohmic contact layer.
[0092] A first constituent layer, a second constituent layer, and a third constituent layer are sequentially vapor-deposited on the entire surface of the first ohmic contact layer away from the semiconductor substrate to form a stacked first constituent layer, a second constituent layer, and a third constituent layer.
[0093] The first, second, and third constituent layers are etched to form a plurality of vias penetrating the first, second, and third constituent layers, thereby obtaining a dielectric layer located on the surface of the first ohmic contact layer away from the semiconductor substrate. The dielectric layer has a plurality of vias, and the vias expose a portion of the first ohmic contact layer.
[0094] Optionally, in one embodiment of this application, the conductive filler may include stacked Au layers, Zn layers, and Au layers, or it may include stacked Au layers, Be layers, and Au layers. In this embodiment, forming a conductive filler within the through-hole includes:
[0095] A second photoresist pattern is formed on the surface of the dielectric layer on the side away from the P-type window layer;
[0096] A conductive filling layer is deposited on the side of the second photoresist pattern away from the P-type window layer and on the entire surface of the via. The conductive filling layer may include stacked Au, Zn and Au layers, or stacked Au, Be and Au layers.
[0097] Using a stripping process, the portion of the conductive filling layer located on the surface of the second photoresist pattern is removed, while the portion of the conductive filling layer located within the via is retained, thus forming a conductive filler within the via.
[0098] Remove the second photoresist pattern and clean the surface of the dielectric layer away from the P-type window layer.
[0099] Optionally, in one embodiment of this application, the mirror layer includes stacked Ag, TiW, Ti, Pt, and Au layers. In this embodiment, forming the mirror layer on the side of the dielectric layer away from the semiconductor substrate may include: sputtering the mirror layer on the side of the dielectric layer away from the semiconductor substrate using a sputtering process, wherein the mirror layer is a metal mirror layer.
[0100] S2: Fix the side of the epitaxial layer away from the semiconductor substrate to the first substrate, and remove the semiconductor substrate.
[0101] Optionally, in one embodiment of this application, fixing the side of the epitaxial layer away from the semiconductor substrate to the first substrate and removing the semiconductor substrate includes:
[0102] like Figure 9 As shown, the epitaxial layer is fixed to the first substrate 10 on the side away from the semiconductor substrate 100 using a bonding process. Optionally, in one embodiment of this application, a metal mirror layer is formed on the side of the epitaxial layer away from the semiconductor substrate 100, and a metal bonding layer 70 is formed on the first substrate 10. The metal mirror layer and the metal bonding layer are bonded using a bonding process to fix the side of the epitaxial layer away from the semiconductor substrate to the first substrate.
[0103] like Figure 10 As shown, the semiconductor substrate is removed.
[0104] It should be noted that, in this embodiment, if a buffer layer and an etching stop layer are formed between the semiconductor substrate and the epitaxial layer, the method further includes removing the buffer layer and the etching stop layer after removing the semiconductor substrate.
[0105] It should also be noted that, in this embodiment, the P-electrode is electrically connected to the P-type semiconductor layer through the omnidirectional reflective layer and the first substrate. Optionally, the first substrate is a highly doped silicon substrate, but this application does not limit it and it depends on the specific circumstances.
[0106] Optionally, in one embodiment of this application, after removing the semiconductor substrate and exposing the surface of the second ohmic contact layer away from the N-type roughening layer, as follows: Figure 11 As shown, the method further includes: etching the second ohmic contact layer 80, retaining a portion of the second ohmic contact layer 80 located in the central region of the N-type roughening layer 2132; forming an N-electrode 90 covering the second ohmic contact layer 80, the N-electrode 90 being electrically connected to the second ohmic contact layer 80 and the N-type roughening layer 2132.
[0107] S3: As Figure 12 As shown, the epitaxial layer is cut from the side away from the first substrate to form multiple epitaxial units 21 and multiple dam structures 22. The dam structures 22 correspond one-to-one with the epitaxial units 21. In a first direction, the dam structure 22 is located at least in the outer part of the epitaxial unit 21, and there is a gap between the dam structure 22 and the epitaxial unit 21. The first direction is parallel to the plane of the first substrate. Therefore, in the subsequent process of replacing the carrier film at the bottom of the LED chip using a lamination process, the dam structure 22 can be used to share the lateral force applied to the edge of the epitaxial unit 21, reducing the possibility of the epitaxial unit 21 being crushed due to pressure, and alleviating problems such as edge chipping and corner chipping during the LED chip manufacturing process.
[0108] Optionally, in one embodiment of this application, the dam structure is arranged around the epitaxial unit in a plane parallel to the plane of the first substrate. This allows the dam structure to share the lateral forces applied to the edge of the epitaxial unit during the replacement of the carrier film at the bottom of the LED chip using a lamination process. The dam structure protects each side of the epitaxial unit, further reducing the risk of the epitaxial unit being damaged by pressure and alleviating problems such as edge chipping and corner breakage during LED chip manufacturing.
[0109] In another embodiment of this application, the dam structure 22 is composed of multiple columnar units 221, and the distance between adjacent columnar units 221 is not less than 3 micrometers. This allows the multiple columnar units 221 to share the lateral forces applied to the edge of the epitaxial unit 21 during the replacement of the carrier film at the bottom of the LED chip using a lamination process. Optionally, the columnar units 221 can be arranged around the epitaxial unit 21, protecting each side of the epitaxial unit 21 and further reducing the risk of the epitaxial unit 21 being damaged by pressure, thus mitigating problems such as edge chipping and corner breakage during LED chip manufacturing.
[0110] Based on any of the above embodiments, in one embodiment of this application, in the first direction, the distance between the dam structure and the epitaxial unit is not less than 3 micrometers and not greater than the width of the second region, so as to avoid the distance between the dam structure and the epitaxial unit being too small, increasing the possibility of short circuits between the dam structure and the epitaxial unit. It should be noted that in this embodiment, the second region of the first substrate is the region where the dicing channel is located in a conventional LED chip, and the width of the second region is the width of the dicing channel in a conventional LED chip, so that the addition of the dam structure does not increase the size of the LED chip in the first direction. However, this application does not limit this, and it depends on the specific circumstances.
[0111] Based on any of the above embodiments, in one embodiment of this application, the width of the dam structure in the first direction is greater than 5 micrometers, so that during the replacement of the carrier film at the bottom of the LED chip using the film pressing process, the dam structure can provide a fixed and sufficient support force for the force applied to the epitaxial unit, better distributing the lateral force applied to the edge of the epitaxial unit 21. Thus, the dam structure can be used to effectively protect each side of the epitaxial unit, further reducing the possibility of the epitaxial unit being crushed by pressure, and alleviating problems such as edge chipping and corner chipping during the LED chip manufacturing process. However, this application does not limit this, and it depends on the specific circumstances.
[0112] Optionally, in one embodiment of this application, after the N electrode is formed, the method for manufacturing the LED chip further includes:
[0113] The portion of the N-type roughening layer not covered by the N electrode is roughened to improve the light extraction efficiency of the light-emitting side of the LED chip.
[0114] A protective layer is formed covering the N-type roughening layer and the dam structure. It should be noted that, in this embodiment, the protective layer exposes a portion of the N-electrode area to facilitate the lead-out of the N-electrode.
[0115] Optionally, in one embodiment of this application, the protective layer is a silicon nitride layer, but this application does not limit it and it depends on the specific circumstances.
[0116] S4: As Figure 13 As shown, a P-electrode 30 is formed on the side of the first substrate 10 away from the epitaxial unit.
[0117] Optionally, in one embodiment of this application, before forming the P electrode on the side of the first substrate away from the epitaxial unit, the method further includes: grinding the first substrate from the side of the first substrate away from the epitaxial unit until a first substrate of a target thickness is obtained, and then forming the P electrode on the surface of the first substrate away from the epitaxial unit.
[0118] S5: Continue as follows Figure 13 As shown, a second carrier film 401 is fixed on the side of the P electrode 30 away from the first substrate 10, that is, the entire LED chip is pasted onto the second carrier film 401.
[0119] S6: As Figure 14 As shown, the first substrate 10 is cleaved from the side of the second carrier film 401 away from the P electrode 30 to form a plurality of LED chips.
[0120] Optionally, in one embodiment of this application, laser cutting is used to cleave the first substrate from the side of the second carrier film away from the P electrode to form a plurality of LED chips.
[0121] It should be noted that, by cleaving the first substrate from the side of the second carrier film away from the P electrode to form multiple LED chips, the cutting position can be defined using the position of the dam structure, such that the cutting position is located on the side of the dam structure away from the epitaxial unit, for example... Figure 13 The cutting position K is used to block the metal sputtering generated by laser cutting when the first substrate is cleaved from the side away from the P electrode from the second carrier film, thereby effectively reducing the leakage rate of the LED chip caused by the metal sputtering generated by laser cutting onto the epitaxial unit.
[0122] S7: As Figure 15 As shown, a flipping process is used to remove the second carrier film on the surface of the first substrate 10 away from the epitaxial layer, and to fix the first carrier film 40 on the surface of the first substrate 10 away from the epitaxial layer.
[0123] Optionally, in one embodiment of this application, a flipping process is used to remove the second carrier film from the surface of the first substrate away from the epitaxial layer, and to fix the first carrier film on the surface of the first substrate away from the epitaxial layer, comprising:
[0124] A third carrier film is fixed on the side of the epitaxial unit away from the first substrate;
[0125] Remove the second carrier film;
[0126] A first carrier film is fixed on the side of the first substrate away from the epitaxial unit;
[0127] Remove the third carrier film.
[0128] In summary, when manufacturing an LED chip using the LED chip manufacturing method provided in this application embodiment, at least a portion of the outer side of the epitaxial unit has a dam structure. This allows the dam structure to share the lateral force applied to the edge of the epitaxial unit during the replacement of the carrier film at the bottom of the LED chip using a lamination process. This reduces the risk of the epitaxial unit being damaged by pressure, alleviates problems such as edge chipping and corner breakage during LED chip manufacturing, and minimizes appearance abnormalities.
[0129] Furthermore, when fabricating an LED chip using the LED chip fabrication method provided in this application embodiment, during the process of cleaving the first substrate from the side away from the P electrode of the second carrier film to form multiple LED chips, the position of the dam structure can be used to define the cutting position, so that the cutting position is located on the side of the dam structure away from the epitaxial unit. Thus, when cleaving the first substrate from the side away from the P electrode of the second carrier film, the dam structure can block the metal sputtering generated by laser cutting, thereby effectively reducing the leakage current ratio of the LED chip caused by metal sputtering generated by laser cutting.
[0130] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. For the apparatuses disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.
[0131] It should be noted that, in the description of this application, the accompanying drawings and embodiments are illustrative rather than restrictive. The same reference numerals throughout the embodiments identify the same structures. It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in an article or device comprising the aforementioned element.
[0132] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. An LED chip, characterized in that, include: A first substrate, the surface of the first substrate having a first region and a second region surrounding the first region; An epitaxial cell located in a first region of the first substrate and a dam structure located in a second region of the first substrate, wherein the epitaxial cell includes a stacked P-type semiconductor layer, a quantum well active layer and an N-type semiconductor layer, and in a first direction, the dam structure is located at least in a portion of the outer side of the epitaxial cell, and there is a gap between the dam structure and the epitaxial cell, and the first direction is parallel to the plane of the first substrate. The P electrode is located on the side of the first substrate away from the epitaxial unit.
2. The LED chip according to claim 1, characterized in that, The dam structure is arranged around the perimeter of the extended unit.
3. The LED chip according to claim 1, characterized in that, The dam structure is composed of multiple columnar units, and the distance between adjacent columnar units is not less than 3 micrometers.
4. The LED chip according to any one of claims 1-3, characterized in that, In the first direction, the distance between the dam structure and the extension unit is not less than 3 micrometers and not greater than the width of the second region.
5. The LED chip according to any one of claims 1-3, characterized in that, In the first direction, the width of the dam structure is greater than 5 micrometers.
6. The LED chip according to claim 1, characterized in that, The P-type semiconductor layer includes a P-type confinement layer located on the side of the quantum well active layer away from the N-type semiconductor layer; the LED chip also includes a P-type window layer located on the side of the P-type semiconductor layer away from the quantum well active layer.
7. The LED chip according to claim 6, characterized in that, Also includes: An omnidirectional reflective layer located between the P-type window layer and the first substrate.
8. The LED chip according to claim 7, characterized in that, The omnidirectional reflective layer includes: A first ohmic contact layer is located on the surface of the P-type window layer facing the first substrate. The first ohmic contact layer covers the third region of the P-type window layer and exposes the fourth region of the P-type window layer. A dielectric layer located on the surface of the first ohmic contact layer facing the first substrate, the dielectric layer having a plurality of through holes, the through holes exposing a portion of the first ohmic contact layer; The conductive filler located within the through hole; A mirror layer located on the side of the dielectric layer facing the first substrate, the mirror layer being a conductive layer and electrically connected to the conductive filler; The P electrode is electrically connected to the P-type semiconductor layer through the first substrate, the mirror layer, the conductive filler, and the first ohmic contact layer.
9. The LED chip according to claim 8, characterized in that, The dielectric layer includes a first constituent layer, a second constituent layer and a third constituent layer stacked together, wherein the first constituent layer is an ITO layer or an IZO layer or an Al2O3 layer, the second constituent layer is a SiO2 layer, and the third constituent layer is an Al2O3 layer or an ITO layer or an IZO layer. The conductive filler includes stacked Au layers, Zn layers and Au layers, or includes stacked Au layers, Be layers and Au layers; The mirror layer comprises stacked Ag, TiW, Ti, Pt, and Au layers.
10. The LED chip according to claim 1, characterized in that, The N-type semiconductor layer includes an N-type confinement layer located on the side of the quantum well active layer away from the P-type semiconductor layer, and an N-type roughening layer located on the side of the N-type confinement layer away from the quantum well active layer.