Interface device adaptive to multiple scenes

Abstract

The utility model relates to an interface device adaptive to multiple scenes. The interface device comprises a main control board, a storage module, a communication interface module and an emergency power supply module, the communication interface module comprises a first interface connected with the main control board and N paths of second interfaces connected with the photoelectric module, wherein N is a positive integer greater than 1; the emergency power supply module comprises a power supply switching circuit based on a metal oxide semiconductor field effect transistor (MOSFET); the input end of the power supply switching circuit comprises a main power supply and a standby power supply, a diode D1 is connected between the main power supply and the output, the standby power supply is connected with the drain electrode of a P-channel field effect transistor Q1, the source electrode of the P-channel field effect transistor Q1 is connected with the output, and the positive electrode of the diode D1 and the grid electrode of the P-channel field effect transistor Q1 are grounded through a filtering voltage stabilizing unit. The interface device provided by the utility model is reliable in power supply switching and strong in adaptability, the power consumption of the whole board is less than or equal to 4W, and the interface device can be suitable for various application scenes with higher requirements on equipment performance, such as aerospace, military affairs, industrial automation and the like.

Description

TECHNICAL FIELD

[0001] The utility model relates to communication technical field, concretely relates to an interface device adapting to multiple scenes. BACKGROUND

[0002] With the rapid development of industrial automation, internet of things and intelligent terminal, multiple scene interface device needs to meet multiple requirements such as high compatibility, strong anti-interference, stable power supply and safety protection. The traditional interface equipment is insufficient in interface expansion capacity on the one hand, most of which only supports single communication protocol or fixed type photoelectric module (such as infrared, laser, etc.), which is difficult to adapt to the diversification demand of complex scene, and lacks effective isolation design in signal transmission, which is easy to be disturbed by common mode and lead to signal distortion. On the other hand, the emergency power switching circuit depends on the unidirectional conduction scheme of diode, which has problems such as large voltage drop loss and slow switching response, and the switching of main and standby power supply is easy to cause voltage drop or instantaneous power failure, affecting the system stability. UTILITY MODEL CONTENTS

[0003] In view of the problems in the prior art, the utility model provides an interface device adapting to multiple scenes, which is reliable in power switching and strong in adaptability.

[0004] The interface device adapting to multiple scenes of the utility model comprises a storage module, a communication interface module and an emergency power module.

[0005] The communication interface module comprises a first interface connected with a main control board and N second interfaces connected with photoelectric modules, wherein N is a positive integer greater than 1.

[0006] The emergency power module comprises a power switching circuit based on MOSFET; the input end of the power switching circuit comprises a main power supply and a standby power supply, a diode D1 is connected between the main power supply and the output, the drain of a P-channel field effect transistor Q1 is connected with the standby power supply, the source of the P-channel field effect transistor Q1 is connected with the output, and the anode of the diode D1 and the gate of the P-channel field effect transistor Q1 are grounded through a filter and voltage stabilizing unit; the filter and voltage stabilizing unit is composed of a resistor R2, a capacitor C1 and a resistor R3 in parallel.

[0007] Further, the interface device of the utility model further comprises a main control board, the main control board comprises a SOC chip, and the SOC chip integrates an ARM processor and an FPGA.

[0008] Further, the storage module of the interface device of the utility model comprises a FLASH and a DDR3 memory connected with the ARM processor through a parallel bus.

[0009] Further, the interface device is characterized in that the FLASH is divided into a security version area and a service version area through address lines, and the FLASH is a FLASH capable of being used for firmware storage and automatically rolling back after upgrade failure.

[0010] Further, the interface device is characterized in that the photoelectric module comprises any one or more of an infrared module, a white light module, a laser irradiation module, a laser receiving module and a light spot module.

[0011] Further, the interface device is characterized in that the interface device further comprises a key destruction signal processing module, and the key destruction signal processing module comprises a key destruction signal processing circuit.

[0012] The key destruction signal processing circuit comprises an optocoupler isolator U1, an external voltage of the key destruction signal is connected to a pin 1 of the optocoupler isolator U1 through a resistor R1, a pin 2 of the optocoupler isolator U1 is directly grounded to form an input signal loop, a pin 4 of the optocoupler isolator U1 is connected to a power supply DVDD_3V3 and grounded through a capacitor C3, and an output pin 3 of the optocoupler isolator U1 is connected to an IO of the FPGA and grounded through a resistor R4.

[0013] Further, the interface device is characterized in that the interface device further comprises a communication fault isolation module, and the communication fault isolation module comprises an isolation circuit; the isolation circuit is constructed based on an isolation type transceiver U8, and a main control side power supply is connected to 2 and 7 pins of the U8 after multi-stage filtering through C96, C97, C102 and C98; wherein a 33Ω resistor is connected in series in a signal input part: DATA_TX is connected to the 6 pin through R112, DE is connected to the 5 pin through R116, RE is connected to the 4 pin through R118, and DATA_RX is connected to the 3 pin through R120; a differential impedance matching is realized through a 120Ω resistor at an isolation output end, RS422_TX+ is output by the 11 pin through R114, and TX- is directly connected by the 12 pin; RS422_RX+ is led out by the 14 pin through R119 at a receiving end, and RX- is directly connected by the 13 pin; 10 and 15 pins of the U8 of the isolation type transceiver are independently connected to an isolation side power supply, and a ground plane is physically isolated in cooperation with a main control side GND1 and an isolation side GND2.

[0014] Further, the interface device is characterized in that the interface device further comprises a receiving buffer area and a sending buffer area supporting two sets of independent data lines, address lines and control lines respectively.

[0015] Further, the interface device is characterized in that the interface device further comprises a power consumption management module, and the power consumption management module adopts a synchronous step-down DC-DC converter; the synchronous step-down DC-DC converter is a four-channel wide voltage input DC-DC converter, an input voltage range is 4V~20V, and an output voltage range is 0.6V~5.5V.

[0016] Further, the interface device further includes a multi-module cooperative upgrading module integrated in the ARM processor, the multi-module cooperative upgrading module includes a control interface, and the safe version area of the storage module is accessed through a parallel bus, and the power-off protection of the emergency power module is triggered through a GPIO alarm signal.

[0017] Compared with the prior art, the utility model has the following beneficial technical effects:

[0018] The interface device suitable for multiple scenes has the emergency power module, the P-channel MOSFET (Q1) and the diode D1 cooperate to form a quick switching circuit, and the filter and voltage stabilizing unit of R2, C1 and R3 is combined, so that the voltage drop loss is greatly reduced when the main and standby power sources are switched, the response time is shortened, and system downtime caused by voltage drop is avoided.

[0019] Secondly, the communication interface module in the interface device supports N-way photoelectric modules (infrared, laser, etc.) flexible expansion, and the transceiving buffer area of two sets of independent data lines, address lines and control lines is combined to realize full-duplex communication and multi-protocol compatibility; the synchronous step-down DC-DC converter provides 4V-20V wide voltage input and 0.6V-5.5V accurate output, adapts to different peripheral power supply requirements, and greatly reduces overall power consumption.

[0020] In addition, the interface device adopts ARM processor and FPGA cooperative control, triggers the parallel bus to access the safe version area through the multi-module cooperative upgrading module, and links the power-off protection mechanism of the emergency power module, realizes real-time linkage and fault isolation of the communication, power supply and storage module, is suitable for high-noise and strong-interference scenes such as industrial control and security monitoring, and the comprehensive performance is improved. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 It is a schematic block diagram of the interface device suitable for multiple scenes in the utility model embodiment 1;

[0022] Figure 2 It is a circuit diagram of the power switching circuit in the utility model embodiment 1;

[0023] Figure 3 It is an automatic rollback safety version flow chart in the utility model embodiment 1;

[0024] Figure 4 It is a circuit diagram of the key destruction signal processing module in the utility model embodiment 1;

[0025] Figure 5 It is a circuit diagram of the isolation circuit in the utility model embodiment 1;

[0026] Figure 6The circuit principle diagram of the synchronous step-down DC-DC converter is described in Embodiment 1 of the utility model.

[0027] Figure 7 The schematic block diagram of the multi-module cooperative upgrading module is described in Embodiment 1 of the utility model. DETAILED DESCRIPTION

[0028] For the purpose, technical solutions and advantages of the embodiments of the utility model, the technical solutions in the embodiments of the utility model will be described clearly and completely below. The specific conditions are not marked in the embodiments, and are carried out according to conventional conditions or manufacturer's recommended conditions.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this technology belongs. The terms used in the specification are only for the purpose of describing specific embodiments and are not intended to limit the utility model. The term "and / or" used herein includes any and all combinations of one or more related listed items. DETAILED DESCRIPTION

[0031] An interface device suitable for multiple scenes comprises a storage module, a communication interface module and an emergency power supply module.

[0032] The communication interface module comprises a first interface connected with a main control board and N second interfaces connected with photoelectric modules, wherein N is a positive integer greater than 1.

[0033] The emergency power supply module comprises a power supply switching circuit based on MOSFET. An input end of the power supply switching circuit comprises a main power supply and a backup power supply. A diode D1 is connected between the main power supply and an output. A drain of a P-channel field effect transistor Q1 is connected with the backup power supply. A source of the P-channel field effect transistor Q1 is connected with the output. A positive electrode of the diode D1 and a gate of the P-channel field effect transistor Q1 are grounded through a filter and voltage stabilizing unit. The filter and voltage stabilizing unit is composed of a resistor R2, a capacitor C1 and a resistor R3 in parallel.

[0034] In other embodiments, the interface device further comprises a main control board, and the main control board comprises a SOC chip, and the SOC chip integrates an ARM processor and an FPGA.

[0035] In other embodiments, the storage module comprises a FLASH and a DDR3 memory connected with the ARM processor through a parallel bus.

[0036] In other embodiments, the FLASH is divided into a security version area and a business version area through an address line, and the FLASH is a FLASH capable of being used for firmware storage and automatically rolling back after upgrading failure.

[0037] In other embodiments, the optoelectronic module includes any one or more of an infrared module, a white light module, a laser illumination module, a laser receiving module, and a light spot module.

[0038] In other embodiments, the interface device further includes a key-destroying signal processing module, the key-destroying signal processing module including a key-destroying signal processing circuit;

[0039] The key-destroying signal processing circuit includes an optocoupler U1, an external voltage of the key-destroying signal being connected to pin 1 of the optocoupler U1 through a resistor R1; pin 2 of the optocoupler U1 is directly grounded to form an input signal loop; pin 4 of the optocoupler U1 is connected to a power supply DVDD_3V3 and grounded through a capacitor C3; an output pin 3 of the optocoupler U1 is connected to an IO of the FPGA and grounded through a resistor R4.

[0040] In other embodiments, the interface device further includes a communication fault isolation module, the communication fault isolation module including an isolation circuit; the isolation circuit being constructed based on an isolation transceiver U8, the isolation transceiver U8 being connected to a main control side power supply through C96, C97, C102, and C98 after multi-stage filtering; wherein a signal input part is connected in series with a 33Ω resistor: DATA_TX is connected to pin 6 through R112, DE is connected to pin 5 through R116, RE is connected to pin 4 through R118, and DATA_RX is connected to pin 3 through R120; an isolation output end is matched in differential impedance through a 120Ω resistor, RS422_TX+ is output by pin 11 through R114, and TX- is directly connected by pin 12; a receiving end RS422_RX+ is led out by pin 14 through R119, and RX- is directly connected by pin 13; pin 10 and pin 15 of the isolation transceiver U8 are independently connected to an isolation side power supply, and the ground planes of the main control side GND1 and the isolation side GND2 are physically isolated.

[0041] In other embodiments, the interface device further includes a receiving buffer and a sending buffer that respectively support two sets of independent data lines, address lines, and control lines.

[0042] In other embodiments, the interface device further includes a power consumption management module, the power consumption management module adopting a synchronous step-down DC-DC converter, the synchronous step-down DC-DC converter being a four-channel wide voltage input DC-DC converter, an input voltage range being 4V~20V, and an output voltage range being 0.6V~5.5V.

[0043] In other embodiments, the interface device further comprises a multi-module cooperative upgrade module integrated in the ARM processor, the multi-module cooperative upgrade module comprises a control interface and accesses a safe version area of the storage module through a parallel bus and triggers the power-off protection of the emergency power module through a GPIO alarm signal Embodiment 1

[0044] An interface device suitable for multiple scenes, comprising a storage module, a communication interface module and an emergency power module.

[0045] The communication interface module comprises a first interface connected with a main control board and N second interfaces connected with photoelectric modules, wherein N is a positive integer greater than 1; in this embodiment 1, as shown in the figure, N is 5, corresponding to infrared modules, white light modules, laser irradiation modules, laser receiving modules and light spot modules of the photoelectric modules respectively. The first interface and the second interfaces are both RS422 interfaces. Figure 1

[0046] The emergency power module comprises a power switching circuit based on MOSFET; the input end of the power switching circuit comprises a main power supply and a backup power supply, a diode D1 is connected between the main power supply and the output, the drain of a P-channel field effect transistor Q1 is connected with the backup power supply, the source of the P-channel field effect transistor Q1 is connected with the output, and the anode of the diode D1 and the gate of the P-channel field effect transistor Q1 are both grounded through a filter and voltage stabilizing unit; the filter and voltage stabilizing unit is composed of a resistor R2, a capacitor C1 and a resistor R3 in parallel.

[0047] As shown in the figure, in this embodiment 1, the main power supply is DVDD_28V_MAIN and the backup power supply is DVDD_28V_BACKUP: Figure 2

[0048] When DVDD_28V_MAIN has power, the P-channel field effect transistor Q1 is cut off, even if there is a body diode current flowing through, but because DVDD_28V_MAIN is higher than DVDD_28V_BACKUP, the Vgs of the P-channel field effect transistor Q1 is greater than 0, so the body diode of the P-channel field effect transistor Q1 is cut off, and therefore, power is supplied by DVDD_28V_MAIN at this time; when DVDD_28V_MAIN has no power, the P-channel field effect transistor Q1 is turned on and starts to be powered by DVDD_28V_BACKUP.

[0049] ​​The storage module includes a FLASH and a DDR3 memory connected with an ARM processor through a parallel bus. The FLASH is divided into a security version area and a service version area through address lines. The FLASH is a FLASH capable of being used for firmware storage and automatically rolling back after upgrade failure. In the embodiment 1, a 256Mb Flash is used, there are 25 address lines (A0~A24) and 8 data lines (D0~D7), the A0~A23 address lines cooperate with the data lines to control a 128Mb interval, and the A0~A23 address lines cooperate with the data lines to control a 128Mb interval.

[0050] The FLASH cooperates with FPGA program update, as shown in the specific steps as follows: Figure 3

[0051] Power-on initialization: the starting point of the flow, the system starts and completes initialization.

[0052] Waiting for receiving instructions: the system is in a waiting state, waiting for external instruction input.

[0053] Judging whether it is an FPGA instruction for updating:

[0054] If no, continue to loop and wait for receiving instructions.

[0055] If yes, go to the next step.

[0056] Receiving program files: receiving program files related to FPGA update.

[0057] Setting the security version effective: ensuring the safety of the current operation, and activating the security version.

[0058] Receiving FPGA programs: obtaining FPGA programs to be burned.

[0059] Burning FPGA programs: burning programs into FPGA.

[0060] Judging whether the burning is successful:

[0061] If yes, executing setting the security version invalid, and then reporting the update result, indicating that the update is completed.

[0062] If no, also reporting the update result, indicating that the upgrade fails, and automatically rolling back the security version.

[0063] The interface device further includes a main control board, a key destruction signal processing module, a communication fault isolation module, a power consumption management module, and a multi-module cooperative upgrade module.

[0064] The main control board includes a SOC chip, and the SOC chip integrates an ARM processor and an FPGA. ​

[0065] The key-destroying signal processing module comprises a key-destroying signal processing circuit;

[0066] As shown in Figure 4 The key-destroying signal processing circuit comprises an opto-coupler U1, an external voltage of the key-destroying signal is connected to pin 1 of the opto-coupler U1 through a resistor R1, pin 2 of the opto-coupler U1 is directly grounded to form an input signal loop, pin 4 of the opto-coupler U1 is connected to a power supply DVDD_3V3 and grounded through a capacitor C3, and pin 3 of the opto-coupler U1 is connected to an IO of the FPGA and grounded through a resistor R4.

[0067] In the embodiment 1, the key-destroying signal HY-IN is an external voltage of 16V-32V, when the key-destroying signal HY-IN comes in, the phototriode is turned on and the output is 0, when the key-destroying signal disappears, the phototriode is cut off and the output is 3.3V. The resistor R1 plays a current-limiting role, and the resistor R2 is a pull-down resistor, which ensures that EK_IN_N keeps low when there is no signal input.

[0068] The interface device further comprises a communication fault isolation module, the communication fault isolation module comprises an isolation circuit; the isolation circuit is constructed based on an isolation type transceiver U8, and is connected to pins 2 and 7 of the U8 through a main control side power supply after multi-stage filtering of C96, C97, C102 and C98; wherein the signal input part is connected in series by a 33Ω resistor: DATA_TX is connected to pin 6 through R112, DE is connected to pin 5 through R116, RE is connected to pin 4 through R118, and DATA_RX is connected to pin 3 through R120; the isolation output end realizes differential impedance matching through a 120Ω resistor, RS422_TX+ is output by pin 11 through R114, and TX- is directly connected by pin 12; the receiving end RS422_RX+ is led out by pin 14 through R119, and RX- is directly connected by pin 13; pins 10 and 15 of the U8 of the isolation type transceiver are independently connected to an isolation side power supply, and the ground planes of the main control side GND1 and the isolation side GND2 are physically isolated.

[0069] In this embodiment 1, the isolated transceiver U8 is an ADM2682EBRZ. The main control side power supply VCC_3V3 is connected to pins 2 and 7 (VCC1, VCC2) of U8 after being filtered through multiple stages by C96 (100nF), C97 (10μF), C102 (10μF), and C98 (100nF), providing a stable power supply to the control side. The signal input section uses 33Ω resistors connected in series: DATA_TX to pin 6 (TxD) via R112, DE to pin 5 via R116, RE to pin 4 via R118, and DATA_RX to pin 3 via R120. The isolation output is differentially impedance matched via a 120Ω resistor. RS422_TX+ is output from pin 11 (Y) via R114, and TX- is directly connected to pin 12 (Z). The receiving end RS422_RX+ is led out from pin 14 (A) via R119, and RX- is directly connected to pin 13 (B). Pins 10 (VISOUT) and 15 (VISOIN) of U8 are independently connected to the isolation side power supply. Combined with the physical isolation between the main control side GND1 (pin 8) and the isolation side GND2, electrical isolation for full-duplex RS-422 communication is achieved, effectively suppressing common-mode interference and making it suitable for data transmission in high-noise environments.

[0070] Through the physical isolation design of the isolated transceiver U8 with the main control side GND1 and the isolation side GND2, combined with differential impedance matching (120Ω resistor at the RS422_TX± / RX± terminal) and the key destruction signal processing of the optocoupler U1, common-mode interference and electromagnetic noise are effectively suppressed, ensuring signal transmission integrity.

[0071] The interface device also includes a power management module, which employs a synchronous buck DC-DC converter. The synchronous buck DC-DC converter is a four-channel wide voltage input DC-DC converter with an input voltage range of 4V to 20V and an output voltage range of 0.6V to 5.5V.

[0072] In this embodiment 1, the 28V power supply is converted to 5V voltage through an isolated power supply. The 5V voltage input meets the input requirements of the DC-DC converter. The output voltage is set to 1V, 1.5V, 1.8V, and 3.3V through the feedback resistor, which meets the output requirements of the DC-DC converter. Two 22uF ceramic capacitors are connected to the external input terminal, and each output is connected to a large-capacity 47uF ceramic capacitor for filtering.

[0073] like Figure 6 As shown, the input configuration is as follows: the signal DDVD_1V / 5V / 3V_EN is connected to the RUN, SVIN and other pins of chip U9 via resistors (such as R6037, R6041, etc.) to control the operation of the circuit.

[0074] The DDVD_5V pin is connected to the VIN pin to provide input power to the chip.

[0075] Output configuration: Chip U9 outputs four-way voltage through VOUT1-VOUT4, each output is connected with feedback resistance (such as R6035, R6036, etc.), used for setting output voltage value, and is matched with capacitor (such as C105, C109, etc. 47μF capacitor) for filtering, to ensure stable output.

[0076] MODE1, MODE2 and other pins configure working mode through resistance, and other control pins (such as TRACK / SS1-TRACK / SS4) participate in output adjustment and state monitoring.

[0077] The circuit contains perfect power input and ground connection, to ensure normal work of chip U9, and part of pins realize signal isolation and level matching through resistance.

[0078] The circuit realizes multi-way stable voltage output through input control, feedback resistance setting and filtering, and is suitable for systems needing multiple power rails.

[0079] The interface device further comprises a multi-module cooperative upgrading module integrated in the ARM processor, the multi-module cooperative upgrading module comprises a control interface, and accesses a security version area of a storage module through a parallel bus, and triggers power-off protection of the emergency power supply module through a GPIO alarm signal.

[0080] As shown in Figure 7 In the embodiment 1, the upper computer can perform upgrading operation on the interface device through the RS232 serial port, after restart takes effect, the interface device sends an upgrading instruction through CAN broadcast, specifies a target module ID and a firmware version for sending, the sub-module receives and returns a check result after completion, if the check passes, performs Flash erase-write operation, the interface device monitors timeout, and fails to trigger rollback to the old version and retransmission.

[0081] The interface device further comprises a receiving buffer and a sending buffer which respectively support two sets of independent data lines, address lines and control lines. In the embodiment 1, the Block RAM (BRAM) in the FPGA is adopted to realize the receiving buffer and the sending buffer, two sets of independent data lines, address lines and control lines are supported, each port can independently perform read-write operation, the sending buffer is written through Port A, and the receiving buffer is read through Port B.

[0082] The embodiments described above are part of the embodiments of the present application, rather than all the embodiments. The detailed description of the embodiments of the present application is not intended to limit the scope of the claimed application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of protection of the present application.

Claims

1. An interface device adaptable to multiple scenarios, characterized in that, The interface device comprises a storage module, a communication interface module and an emergency power module. The communication interface module comprises a first interface connected with a master control board and N second interfaces connected with photoelectric modules, wherein N is a positive integer greater than 1. The emergency power module comprises a power switching circuit based on MOSFET; the input end of the power switching circuit comprises a main power supply and a backup power supply; a diode D1 is connected between the main power supply and an output; the backup power supply is connected with the drain of a P-channel field effect transistor Q1; the source of the P-channel field effect transistor Q1 is connected with the output; the positive electrode of the diode D1 and the gate of the P-channel field effect transistor Q1 are grounded through a filter and voltage stabilizing unit; the filter and voltage stabilizing unit is composed of a resistor R2, a capacitor C1 and a resistor R3 in parallel.

2. The interface device of claim 1, wherein, The interface device further comprises a master control board, and the master control board comprises a SOC chip integrating an ARM processor and an FPGA.

3. The interface device of claim 1, wherein, The storage module comprises a FLASH and a DDR3 memory connected with the ARM processor through a parallel bus.

4. The interface device of claim 3, wherein, The FLASH is divided into a security version area and a service version area through address lines, and the FLASH is a FLASH capable of being used for firmware storage and automatically rolling back after upgrade failure.

5. The interface device of claim 1, wherein, The photoelectric module comprises any one or more of an infrared module, a white light module, a laser irradiation module, a laser receiving module and a light spot module.

6. The interface device of claim 2, wherein, The interface device further comprises a key destruction signal processing module, and the key destruction signal processing module comprises a key destruction signal processing circuit. The key destruction signal processing circuit comprises an optocoupler isolator U1; an external voltage serving as a key destruction signal is connected to the pin 1 of the optocoupler isolator U1 through a resistor R1; the pin 2 of the optocoupler isolator U1 is directly grounded to form an input signal loop; the pin 4 of the optocoupler isolator U1 is connected with a power supply DVDD_3V3 and grounded through a capacitor C3; the output pin 3 of the optocoupler isolator U1 is connected with an IO of the FPGA and grounded through a resistor R4.

7. The interface device of claim 1, wherein, The interface device further comprises a communication fault isolation module, and the communication fault isolation module comprises an isolation circuit; the isolation circuit is constructed based on an isolation type transceiver U8; a main control side power supply is connected with the 2 and 7 pins of the U8 after multi-stage filtering through C96, C97, C102 and C98; the signal input part is connected in series with a 33Ω resistor: DATA_TX is connected to the 6 pin through R112, DE is connected to the 5 pin through R116, RE is connected to the 4 pin through R118, and DATA_RX is connected to the 3 pin through R120; The isolation output end realizes differential impedance matching through a 120Ω resistor, RS422_TX+ is output by the 11 pin through R114, and TX- is directly connected by the 12 pin; the receiving end RS422_RX+ is led out by the 14 pin through R119, and RX- is directly connected by the 13 pin; the 10 and 15 pins of the U8 of the isolation type transceiver are independently connected with an isolation side power supply, and the ground planes of the main control side GND1 and the isolation side GND2 are physically isolated.

8. The interface device of claim 1, wherein, The interface device further comprises a receiving buffer and a sending buffer respectively supporting two sets of independent data lines, address lines and control lines.

9. The interface device of claim 1, wherein, The interface device further comprises a power consumption management module, the power consumption management module adopts a synchronous step-down DC-DC converter, the synchronous step-down DC-DC converter is a four-channel wide voltage input DC-DC converter, the input voltage range is 4V~20V, and the output voltage range is 0.6V~5.5V.

10. The interface device of claim 2, wherein, The interface device further comprises a multi-module cooperative upgrading module integrated in the ARM processor, the multi-module cooperative upgrading module comprises a control interface, and a safe version area of a storage module is accessed through a parallel bus, and power-off protection of the emergency power supply module is triggered through a GPIO alarm signal.

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