Double-sided TOPCon photovoltaic cell, photovoltaic module and photovoltaic system

Abstract

The utility model discloses a double-sided TOPCon photovoltaic cell, a photovoltaic module and a photovoltaic system, and relates to the technical field of photovoltaic cells. The photovoltaic cell comprises a silicon wafer, and a P + emitter layer, a first tunneling oxide layer, a first doped polycrystalline silicon layer, a first oxide layer, a second doped polycrystalline silicon layer, an aluminum oxide layer, a first antireflection film layer and a front electrode are sequentially arranged on the front face of the silicon wafer. Wherein the first tunneling oxide layer, the first doped polycrystalline silicon layer, the first oxide layer and the second doped polycrystalline silicon layer are arranged in a grid line area; a second tunneling oxide layer, a third doped polycrystalline silicon layer, a second oxide layer, a fourth doped polycrystalline silicon layer, a second antireflection film layer and a back electrode are sequentially arranged on the back surface of the silicon wafer; wherein the second oxide layer and the fourth doped polycrystalline silicon layer are arranged in a grid line area. Therefore, the band gap width and defects of the polycrystalline silicon are greatly improved, the parasitic absorption effect is eliminated or reduced, and the overall efficiency of the battery is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of photovoltaic cells, in particular to a bifacial TOPCon photovoltaic cell, a photovoltaic module and a photovoltaic system. BACKGROUND

[0002] The existing bifacial TOPCon cell structure has a tunneling oxide layer and a doped polysilicon layer covering the entire surface of the silicon wafer to form a passivation layer. The band gap width of the polysilicon in this cell structure and the defects will deteriorate the performance of the cell; and the polysilicon has a serious parasitic absorption, which will absorb sunlight of a certain wavelength when used on the front surface of the silicon wafer, reducing the short-circuit current, and will cause parasitic absorption of long-wave band when used on the back surface, thereby causing poor long-wave response of the cell, low bifacial rate and other problems. SUMMARY

[0003] The purpose of the present application is to provide a bifacial TOPCon photovoltaic cell, which can greatly improve the band gap width and defects of the polysilicon, eliminate the parasitic absorption effect of the polysilicon on the front surface, reduce the parasitic absorption effect of the polysilicon on the back surface caused by excessive thickness, and improve the overall efficiency of the cell.

[0004] The first aspect of the present application provides a bifacial TOPCon photovoltaic cell, comprising a silicon wafer, the silicon wafer comprising opposite front and back surfaces, the front surface of the silicon wafer and the back surface of the silicon wafer being respectively provided with a grid line area and a non-grid line area, the front surface of the silicon wafer being sequentially provided with a P+ emitter layer, a first tunneling oxide layer, a first doped polysilicon layer, a first oxide layer, a second doped polysilicon layer, an aluminum oxide layer, a first anti-reflection film layer and a front electrode; wherein the first tunneling oxide layer, the first doped polysilicon layer, the first oxide layer and the second doped polysilicon layer are arranged in the grid line area of the front surface of the silicon wafer; the back surface of the silicon wafer is sequentially provided with a second tunneling oxide layer, a third doped polysilicon layer, a second oxide layer, a fourth doped polysilicon layer, a second anti-reflection film layer and a back electrode; wherein the second oxide layer and the fourth doped polysilicon layer are arranged in the grid line area of the back surface of the silicon wafer.

[0005] In an optional manner, the silicon wafer is an N-type silicon wafer.

[0006] In an optional manner, the resistivity of the silicon wafer is 0.5-2 Ω·cm.

[0007] In an optional manner, the size of the silicon wafer is 182x182 mm, 182x210 mm or 210x210 mm.

[0008] In an optional manner, the thickness of the silicon wafer is 130 μm or 110 μm.

[0009] In an alternative way, the back surface is a tower base structure, the tower base has a size of 5-15 μm, and the reflectivity of the tower base is 30-50%.

[0010] In an alternative way, the thickness of the first tunneling oxide layer is greater than the thickness of the first oxide layer.

[0011] In an alternative way, the thickness of the second tunneling oxide layer is greater than the thickness of the second oxide layer.

[0012] In an alternative way, the thickness of the first tunneling oxide layer is 1.5-2 nm.

[0013] In an alternative way, the thickness of the second tunneling oxide layer is 1.5-2 nm.

[0014] In an alternative way, the thickness of the first oxide layer is 1-1.5 nm.

[0015] In an alternative way, the thickness of the second oxide layer is 1-1.5 nm.

[0016] In an alternative way, the thickness of the first doped polysilicon layer is less than the thickness of the second doped polysilicon layer.

[0017] In an alternative way, the thickness of the third doped polysilicon layer is less than the thickness of the fourth doped polysilicon layer.

[0018] In an alternative way, the first doped polysilicon layer and the second doped polysilicon layer have the same conductivity type, the third doped polysilicon layer and the fourth doped polysilicon layer have the same conductivity type, and the conductivity types of the first doped polysilicon layer and the second doped polysilicon layer are opposite to those of the third doped polysilicon layer and the fourth doped polysilicon layer.

[0019] In an alternative way, the doping concentration of the first doped polysilicon layer is less than the doping concentration of the second doped polysilicon layer.

[0020] In an alternative way, the doping concentration of the third doped polysilicon layer is less than the doping concentration of the fourth doped polysilicon layer.

[0021] In an alternative way, the thickness of the first doped polysilicon layer is 50-80 nm.

[0022] In an alternative way, the thickness of the second doped polysilicon layer is 80-150 nm.

[0023] In an alternative way, the thickness of the third doped polysilicon layer is 50-80 nm.

[0024] In an alternative way, the fourth doped polysilicon layer has a thickness of 80-150 nm.

[0025] In an alternative way, the first and second doped polysilicon layers are P-type, and the third and fourth doped polysilicon layers are N-type.

[0026] In an alternative way, the first doped polysilicon layer has a concentration of 3-5×10 19 atom / cm 3 , and the second doped polysilicon layer has a concentration of 4-6×10 19 atom / cm 3 .

[0027] In an alternative way, the third doped polysilicon layer has a concentration of 2-3×10 20 atom / cm 3 , and the fourth doped polysilicon layer has a concentration of 3-5×10 20 atom / cm 3 .

[0028] In an alternative way, the first antireflection film layer has a thickness less than that of the second antireflection film layer.

[0029] In an alternative way, the first antireflection film layer has a thickness of 50-85 nm, and / or the second antireflection film layer has a thickness of 75-105 nm.

[0030] In an alternative way, the aluminum oxide has a thickness of 3-7 nm.

[0031] The second aspect of the present application provides a photovoltaic module comprising the bifacial TOPCon photovoltaic cell of the first aspect of the present application.

[0032] The third aspect of the present application provides a photovoltaic system comprising the photovoltaic module of the second aspect of the present application.

[0033] Compared with the prior art, the bifacial TOPCon photovoltaic cell prepared by the present application has a passivation contact structure on the front and back surfaces, respectively, and a polycrystalline silicon-free structure is used in the non-grid line area of the front surface to avoid polycrystalline silicon parasitic absorption; a relatively thin polycrystalline silicon structure is used on the back surface to reduce polycrystalline silicon parasitic absorption. BRIEF DESCRIPTION OF DRAWINGS

[0034] The accompanying drawings, which are included to provide a further understanding of the present application and constitute a part of this application, illustrate certain illustrative embodiments of the present application and together with the general description of the present application given above and the detailed description of the present application given below, serve to explain the present application. In the drawings:

[0035] Figure 1 A schematic diagram of one embodiment of a bifacial TOPCon photovoltaic cell of the present application is shown.

[0036] Reference signs:

[0037] 10-silicon wafer; 20-P+emitter layer; 301-first tunneling oxide layer; 302-first doped polysilicon layer; 303-first oxide layer; 304-second doped polysilicon layer; 40-aluminum oxide layer; 501-first anti-reflective film layer; 502-second anti-reflective film layer; 601-front electrode; 602-back electrode; 701-second tunneling oxide layer; 702-third doped polysilicon layer; 703-second oxide layer; 704-fourth doped polysilicon layer. DETAILED DESCRIPTION

[0038] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that the description is merely exemplary and is not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques have been omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0039] Further, the terms "first", "second", etc. are used only for the purpose of description and do not constitute a limitation on or imply a relative importance of the indicated technical features. Thus, features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited. The meaning of "several" is one or more, unless otherwise explicitly and specifically limited.

[0040] A first aspect of the present application provides a bifacial TOPCon photovoltaic cell, such as Figure 1 As shown, the photovoltaic cell comprises:

[0041] The silicon wafer 10 is an N-type single crystal silicon wafer 10, which means that the crystal bar grown by the Czochralski method is subjected to squaring, chamfering, slicing, cleaning and sorting to obtain the silicon wafer 10.

[0042] The silicon wafer 10 includes opposite front and back surfaces. After the silicon wafer 10 is prepared into a photovoltaic cell, it will be prepared into a photovoltaic module. The photovoltaic module needs to have one surface mainly facing the sun to absorb sunlight. The surface facing the sunlight is generally referred to as the front surface. The other surface opposite to the front surface is referred to as the back surface.

[0043] The front surface of the silicon wafer 10 is divided into a grid line area and a non-grid line area. In a photovoltaic cell, electrodes are needed to collect and transmit current, and the electrodes are generally referred to as grid lines. The grid lines are divided into main grid lines and auxiliary grid lines. Compared with the main grid lines, the auxiliary grid lines are more in number and narrower in width. In some cells, the main grid lines can not be provided. The grid line area of the present application refers to the area where the auxiliary grid lines are printed subsequently. The non-grid line area of the present application refers to the area where the auxiliary grid lines are not prepared subsequently.

[0044] The front surface of the silicon wafer 10 is provided with, in sequence, a P+ emitter layer 20, a first tunneling oxide layer 301, a first doped polysilicon layer 302, a first oxide layer 303, a second doped polysilicon layer 304, an aluminum oxide layer 40, a first antireflection film layer 501, and a front surface electrode 601. The first tunneling oxide layer 301, the first doped polysilicon layer 302, the first oxide layer 303, and the second doped polysilicon layer 304 are provided in the grid line area of the front surface of the silicon wafer 10.

[0045] The back surface of the silicon wafer 10 is provided with, in sequence, a second tunneling oxide layer 701, a third doped polysilicon layer 702, a second oxide layer 703, a fourth doped polysilicon layer 704, a second antireflection film layer 502, and a back surface electrode 602. The second oxide layer 703 and the fourth doped polysilicon layer 704 are provided in the grid line area of the back surface of the silicon wafer 10.

[0046] By preparing a passivation contact structure on the front and back surfaces of a photovoltaic cell, on the one hand, a structure without polysilicon is adopted in the non-grid line area of the front surface of the photovoltaic cell, and the passivation structure is provided in the grid line area, so that the passivation effect is ensured and polysilicon parasitic absorption is avoided. On the other hand, a third doped polysilicon layer is provided in the non-grid line area of the back surface of the photovoltaic cell, and a fourth doped polysilicon layer is provided in the grid line area. A thin polysilicon structure is adopted on the back surface, polysilicon parasitic absorption is reduced, and the efficiency of the photovoltaic cell is effectively improved.

[0047] In an optional manner, the resistivity of the silicon wafer 10 is 0.5-2 Ω·cm. For example, it can be 0.5 Ω·cm, 0.6 Ω·cm, 0.7 Ω·cm, 0.8 Ω·cm, 0.9 Ω·cm, 1.0 Ω·cm, 1.1 Ω·cm, 1.2 Ω·cm, 1.3 Ω·cm, 1.4 Ω·cm, 1.5 Ω·cm, 1.6 Ω·cm, 1.7 Ω·cm, 1.8 Ω·cm, 1.9 Ω·cm, 2.0 Ω·cm, 2.1 Ω·cm, 2.2 Ω·cm, 2.3 Ω·cm, 2.4 Ω·cm, or 2.5 Ω·cm.

[0048] In an optional manner, the size of the silicon wafer 10 is 182×182 mm, 182×210 mm, or 210×210 mm.

[0049] In an alternative embodiment, the thickness of the silicon wafer 10 is 130 μm or 110 μm.

[0050] In an alternative embodiment, the thickness of the first tunneling oxide layer 301 is greater than the thickness of the first oxide layer 303; in a specific embodiment, the thickness of the first tunneling oxide layer 301 is 1.5-2 nm; the thickness of the first oxide layer 303 is 1-1.5 nm. If the thickness of the first oxide layer 303 is too thin, it cannot block the corrosion from the interface; if the thickness of the oxide blocking layer is too thick, it will completely block the boron from entering the amorphous silicon layer on the front side, affecting the barrier effect and the doping effect.

[0051] In an alternative embodiment, the thickness of the second tunneling oxide layer 701 is greater than the thickness of the second oxide layer 703; in a specific embodiment, the thickness of the second tunneling oxide layer 701 is 1.5-2 nm; the thickness of the second oxide layer 703 is 1-1.5 nm. If the thickness of the second oxide layer 703 is too thin, it cannot block the corrosion from the interface; if the thickness of the oxide blocking layer is too thick, it will completely block the boron from entering the amorphous silicon layer on the front side, affecting the barrier effect and the doping effect.

[0052] In an alternative embodiment, the thickness of the first doped polysilicon layer 302 is less than the thickness of the second doped polysilicon layer 304. In some specific embodiments, the thickness of the first doped polysilicon layer 302 is 50-80 nm; for example, it can be 50 nm, 53 nm, 55 nm, 57 nm, 60 nm, 62 nm, 64 nm, 65 nm, 66 nm, 68 nm, 69 nm, 70 nm, 72 nm, 75 nm, 78 nm, or 80 nm; the thickness of the second doped polysilicon layer 304 is 80-150 nm, for example, it can be 80 nm, 81 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, 125 nm, 130 nm, 135 nm, 140 nm, 145 nm, or 150 nm. The thickness of the doped polysilicon layer will affect the diffusion of the doping elements; in order to ensure that the first doped polysilicon layer can reach a certain doping concentration, and not too many doping elements diffuse to the first tunneling oxide layer, affecting the tunneling passivation effect of the first tunneling oxide layer, the thickness of the second doped polysilicon layer is between 80-150 nm, and the thickness of the first doped polysilicon layer is less than the thickness of the second doped polysilicon layer, so as to ensure the concentration of the first doped polysilicon layer and the passivation effect of the first tunneling oxide layer.

[0053] In an alternative way, the thickness of the third doped polysilicon layer 702 is less than the thickness of the fourth doped polysilicon layer 704. In some specific embodiments, the thickness of the third doped polysilicon layer 702 is 50-80 nm, for example, it can be 50 nm, 53 nm, 55 nm, 57 nm, 60 nm, 62 nm, 64 nm, 65 nm, 66 nm, 68 nm, 69 nm, 70 nm, 72 nm, 75 nm, 78 nm or 80 nm; the thickness of the fourth doped polysilicon layer 704 is 80-150 nm, for example, it can be 80 nm, 81 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, 125 nm, 130 nm, 135 nm, 140 nm, 145 nm or 150 nm. The third doped polysilicon layer 702 is disposed in the non-gate line area, and the excessive thickness of the third doped polysilicon layer 702 will increase the parasitic absorption. The third doped polysilicon layer 702 disposed in the non-gate line area is thinner, thereby effectively reducing the parasitic absorption.

[0054] In an alternative way, the first doped polysilicon layer 302 and the second doped polysilicon layer 304 have the same conductivity type. In a specific embodiment, the conductivity type of the first doped polysilicon layer 302 and the second doped polysilicon layer 304 is P type.

[0055] In an alternative way, the third doped polysilicon layer 702 and the fourth doped polysilicon layer 704 have the same conductivity type. In a specific embodiment, the conductivity type of the third doped polysilicon layer 702 and the fourth doped polysilicon layer 704 is N type.

[0056] In an alternative way, the conductivity type of the first doped polysilicon layer 302 and the second doped polysilicon layer 304 is opposite to that of the third doped polysilicon layer 702 and the fourth doped polysilicon layer 704; in a specific embodiment, the conductivity type of the first doped polysilicon layer 302 and the second doped polysilicon layer 304 is P type, and the conductivity type of the third doped polysilicon layer 702 and the fourth doped polysilicon layer 704 is N type.

[0057] In an alternative way, the doping concentration of the first doped polysilicon layer is less than the doping concentration of the second doped polysilicon layer; in a specific embodiment, the concentration of the first doped polysilicon layer is 3-5×10 19 atom / cm 3 , for example, it can be 3×10 19 atom / cm 3 , 3.5×10 19 atom / cm 3 , 4×10 19 atom / cm 34.5x10 19 atom / cm 3 5x10 19 atom / cm 3 ; the second doped polysilicon layer has a concentration of 4-6x10 19 atom / cm 3 , for example, 4x10 19 atom / cm 3 , 4.5x10 19 atom / cm 3 , 5x10 19 atom / cm 3 , 5.5x10 19 atom / cm 3 , or 6x10 19 atom / cm 3 ; thus, the two doped polysilicon layers have different concentrations, forming a high-low potential barrier, and improving the carrier transmission effect.

[0058] In an alternative way, the third doped polysilicon layer has a doping concentration less than the doping concentration of the fourth doped polysilicon layer; in a specific embodiment, the third doped polysilicon layer has a concentration of 2-3x10 20 atom / cm 3 , for example, 2x10 20 atom / cm 3 , 2.5x10 20 atom / cm 3 , or 3x10 20 atom / cm 3 ; the fourth doped polysilicon layer has a concentration of 3-5x10 20 atom / cm 3 , for example, 3x10 20 atom / cm 3 , 3.5x10 20 atom / cm 3 , 4x10 20 atom / cm 3 , 4.5x10 20 atom / cm 3 , or 5x10 20 atom / cm 3 ; thus, the two doped polysilicon layers have different concentrations, forming a high-low potential barrier, and improving the carrier transmission effect.

[0059] In an alternative way, the aluminum oxide has a thickness of 3-7nm. For example, 3nm, 4nm, 5nm, 6nm, or 7nm.

[0060] In an alternative way, the thickness of the first anti-reflective film layer 501 is less than the thickness of the second anti-reflective film layer 502. In a specific embodiment, the thickness of the first anti-reflective film layer 501 is 50-85 nm; for example, it can be 50 nm, 55 nm, 60 nm, 65 nm, 66 nm, 68 nm, 69 nm, 70 nm, 72 nm, 75 nm, 78 nm, 80 nm, 81 nm, or 85 nm 90 nm. The thickness of the second anti-reflective film layer 502 is 75 nm-105 nm, for example, it can be 70 nm, 72 nm, 75 nm, 78 nm, 80 nm, 81 nm, 85 nm, 90 nm, 95 nm, 100 nm, or 105 nm.

[0061] In an alternative way, before LPCVD, the structure of the back surface is a tower base structure, and the size of the tower base structure is 5-15 μm; for example, it can be 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, or 15 μm; preferably, the tower base is 5-10 μm; more preferably, the tower base is 5-7 μm. Preferably, the reflectivity of the tower base is 30%-50%, for example, it can be 30%, 35%, 40%, 45%, or 50%. The tower base structure can ensure the contact resistivity with the gate line, and the reflectivity can increase the response to long-wave band of light, thereby improving the efficiency. It is worth noting that the size of the tower base in the present application refers to the size of the tower base in the orthographic projection of the silicon wafer. Generally, the orthographic projection of the tower base is a quadrilateral, and at this time, the size of the tower base is the maximum side length of the orthographic projection, which is 5-15 μm.

[0062] The pyramid structure refers to a surface topography structure similar to a pyramid, and the tower base structure refers to a surface topography structure after the tower top part of the pyramid structure is cut off. In some specific embodiments, the pyramid structure can be formed by laser etching, mechanical method, or plasma etching, and the tower base structure is formed by alkali polishing treatment.

[0063] The second aspect of the present application provides a photovoltaic module comprising the bifacial TOPCon photovoltaic cell of the first aspect of the present application.

[0064] The third aspect of the present application provides a photovoltaic system comprising the photovoltaic module of the second aspect of the present application.

[0065] The preparation method of the photovoltaic cell of the present application and its effects will be described below in combination with a specific embodiment of the present application, and the photovoltaic cell of the present application will be further explained and described. EMBODIMENT

[0066] Step 101: Select an N-type single crystal silicon wafer, the resistivity of the silicon wafer is 0.5-2.5 Ω·cm, the size of the silicon wafer is 182×182 mm, the thickness is 130 µm, and the double sides of the N-type single crystal silicon wafer are textured by using NaOH aqueous solution; then, boron diffusion is performed on the silicon wafer in a tube furnace, the temperature of the boron diffusion is 950℃, and a P+ layer is formed on the front side of the silicon wafer;

[0067] Step 102: Remove the BSG layer on the front side of the silicon wafer by using a chain machine, the mass fraction of HF in the chain machine is 7.65%, and the process time is 60 seconds; then, a first tunneling oxide layer, a first amorphous silicon layer, a first oxide layer, and a second amorphous silicon layer are sequentially deposited on the surface of the silicon wafer by using LPCVD; the thicknesses of the layers are 1.5 nm, 80 nm, 1 nm, and 120 nm, respectively; after boron diffusion and annealing treatment, the first amorphous silicon layer and the second amorphous silicon layer form a P-type first doped polysilicon layer and a P-type second doped polysilicon layer.

[0068] Step 103: Remove the BSG layer on the back side of the silicon wafer by using a chain machine, remove the second doped polysilicon layer on the back side of the silicon wafer by using an alkali tank, remove the first oxide layer on the back side of the silicon wafer by using a chain machine again, remove the first doped polysilicon layer on the back side of the silicon wafer by using an alkali tank, and remove the first tunneling oxide layer and the BSG layer on the back side of the silicon wafer by using a chain machine again. Among them, the mass fraction of HF in the chain machine is 7.65%, and the process time is 60 seconds; the mass fraction of KOH in the alkali tank is 7.92%, the mass fraction of H2O2 is 2.5%, the treatment temperature is 65℃, and the time is 350 seconds.

[0069] Then, the back side of the silicon wafer is polished by using an alkali solution, so that a 7 µm tower base is formed on the back side of the silicon wafer, and the reflectivity of the tower base is 39.2%. In the polishing solution, the mass fraction of KOH is 3.43%, the mass fraction of H2O2 is 2.5%, the treatment temperature is 65℃, and the time is 200 seconds.

[0070] Then, a second tunneling oxide layer, a third amorphous silicon layer, a second oxide layer, and a fourth amorphous silicon layer are sequentially deposited on the surface of the silicon wafer by using LPCVD; the thicknesses of the layers are 1.5 nm, 50 nm, 1 nm, and 100 nm, respectively; after phosphorus diffusion and annealing treatment, the first amorphous silicon layer and the second amorphous silicon layer form an N-type first doped polysilicon layer and an N-type second doped polysilicon layer.

[0071] Step 104: remove the PSG layer on the back surface of the silicon wafer by a chain machine, then remove the fourth doped polysilicon layer on the front surface of the silicon wafer by an alkali tank, then remove the second oxide layer on the front surface of the silicon wafer by a chain machine, then remove the third doped polysilicon layer on the front surface of the silicon wafer by an alkali tank, then remove the second tunnel oxide layer and the BSG layer on the back surface of the silicon wafer by a chain machine. Among them, the mass fraction of HF in the chain machine is 7.65%, and the process time is 60 seconds; the mass fraction of KOH in the alkali tank is 7.92%; the mass fraction of H2O2 is 2.5%, and the treatment temperature is 65℃, and the time is 350 seconds.

[0072] Step 105: scan the second doped polysilicon layer on the non-grid line area of the front surface of the silicon wafer and the fourth doped polysilicon layer on the back surface of the silicon wafer by a picosecond laser with a spot diameter of 90µm, a wavelength of 355nm, a repetition frequency of 150KHz, an output power of 10W, and a laser energy density of 1.8J / cm2;

[0073] Step 106: remove the second doped polysilicon layer on the non-grid line area of the front surface of the silicon wafer and the fourth doped polysilicon layer on the non-grid line area of the back surface of the silicon wafer by a solution with a mass fraction of KOH of 7.92% and a mass fraction of H2O2 of 2.5%;

[0074] Step 107: remove the first oxide layer on the non-grid line area of the front surface of the silicon wafer and scan the first doped polysilicon layer on the non-grid line area of the front surface of the silicon wafer by a picosecond laser with a spot diameter of 90µm, a wavelength of 355nm, a repetition frequency of 150KHz, an output power of 10W, and a laser energy density of 1.8J / cm2.

[0075] Step 108: remove the first doped polysilicon layer on the non-grid line area of the front surface of the silicon wafer by a solution with a mass fraction of KOH of 7.92% and a mass fraction of H2O2 of 2.5%.

[0076] Step 109: remove the BSG layer and the second tunnel oxide layer on the non-grid line area of the front surface of the silicon wafer and the PSG layer and the second oxide layer on the non-grid line area of the back surface of the silicon wafer by double-sided acid treatment using a mixed solution of HF with a mass fraction of 37% and HCl with a mass fraction of 49% and water, at a temperature of 25℃, and a treatment time of 150 seconds.

[0077] Step 110: deposit an aluminum oxide layer on the front surface of the silicon wafer;

[0078] Step 111: deposit a first anti-reflective film layer on the front surface of the silicon wafer and a second anti-reflective film layer on the back surface of the silicon wafer, respectively;

[0079] Step 112: prepare a front electrode and a back electrode on the grid line area of the front surface of the silicon wafer and the back surface of the silicon wafer, respectively.

[0080] Through the above steps, a finished product bifacial TOPCon bifacial cell is prepared, the photovoltaic cell comprising a silicon wafer 10,

[0081] The front surface of the silicon wafer 10 is sequentially provided with a P+ emitter layer 20, a first tunneling oxide layer 301, a first doped polysilicon layer 302, a first oxide layer 303, a second doped polysilicon layer 304, an aluminum oxide layer 40, a first antireflection film layer 501, and a front surface electrode 601; wherein the first tunneling oxide layer 301, the first doped polysilicon layer 302, the first oxide layer 303, and the second doped polysilicon layer 304 are arranged in the grid line area of the front surface of the silicon wafer 10; wherein the thicknesses of the first tunneling oxide layer 301, the first doped polysilicon layer 302, the first oxide layer 303, and the second doped polysilicon layer 304 are 1.5 nm, 80 nm, 1 nm, and 120 nm, respectively; the first doped polysilicon layer 302 and the second doped polysilicon layer 304 are P-type, and the doping concentrations are 3.65×10 1 atom / cm 3 and 4.65×10 19 atom / cm 3 ; the thickness of the aluminum oxide layer 40 is 6 nm, and the first antireflection film layer 501 is a SiNx antireflection film with a thickness of 75 nm.

[0082] The back surface of the silicon wafer 10 is sequentially provided with a second tunneling oxide layer 701, a third doped polysilicon layer 702, a second oxide layer 703, a fourth doped polysilicon layer 704, a second antireflection film layer 502, and a back surface electrode 602; wherein the second oxide layer 703 and the fourth doped polysilicon layer 704 are arranged in the grid line area of the back surface of the silicon wafer 10. The thicknesses of the second tunneling oxide layer 701, the third doped polysilicon layer 702, the second oxide layer 703, and the fourth doped polysilicon layer 704 are 1.5 nm, 50 nm, 1 nm, and 100 nm, respectively; the third doped polysilicon layer 702 and the fourth doped polysilicon layer 704 are N-type, and the doping concentrations are 3.65×10 20 atom / cm 3 and 4.65×10 20 atom / cm 3 ; the first antireflection film layer 501 is a SiNx antireflection film with a thickness of 90 nm. A cell efficiency tester is used to test the electrical performance of the photovoltaic cell.

[0083] Compared with Example 1, there is no step 105-109; through the above steps, the finished product bifacial TOPCon bifacial cell is:

[0084] The front surface of the silicon wafer is sequentially provided with a P+ emitter layer, a first tunneling oxide layer, a first doped polysilicon layer, a first oxide layer, a second doped polysilicon layer, an aluminum oxide layer, a first anti-reflection film layer, and a front electrode; wherein the thicknesses of the first tunneling oxide layer, the first doped polysilicon layer, the first oxide layer, and the second doped polysilicon layer are 1.5 nm, 80 nm, 1 nm, and 120 nm, respectively; the first doped polysilicon layer and the second doped polysilicon layer are P-type, and the doping concentrations are 3.65×10 19 atom / cm 3 and 4.65×10 19 atom / cm 3 ; the thickness of the aluminum oxide layer is 6 nm, and the first anti-reflection film layer is a SiNx anti-reflection film with a thickness of 75 nm.

[0085] The back surface of the silicon wafer is sequentially provided with a second tunneling oxide layer, a third doped polysilicon layer, a second oxide layer, a fourth doped polysilicon layer, a second anti-reflection film layer, and a back electrode; wherein the thicknesses of the second tunneling oxide layer, the third doped polysilicon layer, the second oxide layer, and the fourth doped polysilicon layer are 1.5 nm, 50 nm, 1 nm, and 100 nm, respectively; the third doped polysilicon layer and the fourth doped polysilicon layer are N-type, and the doping concentrations are 3.65×10 20 atom / cm 3 and 4.65×10 20 atom / cm 3 ; the first anti-reflection film layer is a SiNx anti-reflection film with a thickness of 90 nm.

[0086] Compared with Example 1,

[0087] Step 107: The first oxide layer on the front surface of the silicon wafer and the second oxide layer on the back surface of the silicon wafer are removed by using a picosecond laser with a spot diameter of 90 µm, a wavelength of 355 nm, a repetition frequency of 150 KHz, an output power of 10 W, and a laser energy density of 1.8 J / cm2, and the first doped polysilicon layer on the front surface of the silicon wafer and the third doped polysilicon layer on the back surface of the silicon wafer are scanned.

[0088] Step 108: The first doped polysilicon layer on the front surface of the silicon wafer and the third doped polysilicon layer on the back surface of the silicon wafer are removed by using a solution with a mass fraction of 7.92% of KOH and a mass fraction of 2.5% of H2O2.

[0089] Step 109: The BSG layer and the second tunneling oxide layer on the front surface of the silicon wafer and the PSG layer and the first tunneling oxide layer on the back surface of the silicon wafer are removed by using a mixed solution of HF with a mass fraction of 37% and HCl with a mass fraction of 49% and water, with a temperature of 25°C and a processing time of 150 seconds.

[0090] By the above steps, a finished double-sided TOPCon double-sided cell is prepared, wherein, as shown in Figure 1 The photovoltaic cell includes a silicon wafer 10,

[0091] By the above steps, a finished double-sided TOPCon double-sided cell is prepared as follows:

[0092] The front side of the silicon wafer is sequentially provided with a P+ emitter layer, a first tunneling oxide layer, a first doped polysilicon layer, a first oxide layer, a second doped polysilicon layer, an aluminum oxide layer, a first antireflection film layer, and a front electrode; wherein the first tunneling oxide layer, the first doped polysilicon layer, the first oxide layer, and the second doped polysilicon layer are arranged in the grid line area of the front side of the silicon wafer; wherein the thicknesses of the first tunneling oxide layer, the first doped polysilicon layer, the first oxide layer, and the second doped polysilicon layer are 1.5 nm, 80 nm, 1 nm, and 120 nm, respectively; the first doped polysilicon layer and the second doped polysilicon layer are P-type, and the doping concentrations are 3.65×10 19 atom / cm 3 and 4.65×10 19 atom / cm 3 , respectively; the thickness of the aluminum oxide layer is 6 nm, and the first antireflection film layer is a SiNx antireflection film with a thickness of 75 nm.

[0093] The back side of the silicon wafer is sequentially provided with a second tunneling oxide layer, a third doped polysilicon layer, a second oxide layer, a fourth doped polysilicon layer, a second antireflection film layer, and a back electrode; wherein the second tunneling oxide layer, the third doped polysilicon layer, the second oxide layer, and the fourth doped polysilicon layer are arranged in the grid line area of the back side of the silicon wafer; the thicknesses of the second tunneling oxide layer, the third doped polysilicon layer, the second oxide layer, and the fourth doped polysilicon layer are 1.5 nm, 50 nm, 1 nm, and 100 nm, respectively; the third doped polysilicon layer and the fourth doped polysilicon layer are N-type, and the doping concentrations are 3.65×10 20 atom / cm 3 and 4.65×10 20 atom / cm 3 , respectively; the first antireflection film layer is a SiNx antireflection film with a thickness of 90 nm.

[0094] The following table is the electrical performance data of Example 1 and Comparative Examples 1-2. As can be seen from the table, (1) compared with the double-sided passivation layer structure of Comparative Example 1 which is fully covered, the efficiency value of the cell sheet of Example 1 is increased by nearly 0.4%, which greatly improves the efficiency. (2) Compared with Example 1, the back passivation layer in Comparative Example 2 affects the tower base structure, resulting in a decrease of 0.2% in the efficiency value.

[0095] Table 1 Electrical performance data of Example 1 and Comparative Examples 1-2

[0096]

[0097] Although the application has been described in connection with various embodiments thereof, it will be understood that the application is capable of further modifications and that this application is intended to cover any and all such variations, using the scope of the claims. The word "comprising" does not exclude other components or steps not mentioned. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. A single processor or other unit can fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

[0098] Although the application has been described in connection with specific embodiments thereof, it will be understood that it is capable of further modifications and this application is intended to cover any and all such variations, using the scope of the claims. The description and drawings merely schematically illustrate specific embodiments of the application, it being understood that the application is not limited to these but is only limited by the scope of the claims. Obviously many modifications and variations of this application are possible in light of its teachings. It is therefore to be understood that within the scope of the claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A bifacial TOPCon photovoltaic cell, characterized in that, The device includes a silicon wafer, which has a front side and a back side, and the front side and the back side of the silicon wafer are respectively provided with gate line regions and non-gate line regions. The silicon wafer has a P+ emitter layer, a first tunneling oxide layer, a first doped polysilicon layer, a first oxide layer, a second doped polysilicon layer, an aluminum oxide layer, a first antireflection film layer, and a front electrode disposed sequentially on the front side; wherein the first tunneling oxide layer, the first doped polysilicon layer, the first oxide layer, and the second doped polysilicon layer are disposed in the gate line region on the front side of the silicon wafer. The back side of the silicon wafer is sequentially provided with a second tunneling oxide layer, a third doped polysilicon layer, a second oxide layer, a fourth doped polysilicon layer, a second antireflection film layer, and a back electrode; wherein the second oxide layer and the fourth doped polysilicon layer are disposed in the gate line region on the back side of the silicon wafer.

2. The photovoltaic cell as described in claim 1, characterized in that, The silicon wafer is an N-type silicon wafer, and / or, The resistivity of the silicon wafer is 0.5~2Ω·cm, and / or, The silicon wafer has dimensions of 182×182mm, 182×210mm, or 210×210mm, and / or, The thickness of the silicon wafer is 130 μm or 110 μm.

3. The photovoltaic cell as described in claim 1, characterized in that, The thickness of the first tunneling oxide layer is greater than the thickness of the first oxide layer; and / or, The thickness of the second tunneling oxide layer is greater than the thickness of the second oxide layer; and / or, The thickness of the first doped polysilicon layer is less than the thickness of the second doped polysilicon layer; and / or, The thickness of the third doped polysilicon layer is less than the thickness of the fourth doped polysilicon layer; and / or, The first doped polysilicon layer and the second doped polysilicon layer have the same conductivity type, the third doped polysilicon layer and the fourth doped polysilicon layer have the same conductivity type, and the first doped polysilicon layer and the second doped polysilicon layer have opposite conductivity types to the third doped polysilicon layer and the fourth doped polysilicon layer.

4. The photovoltaic cell as described in claim 3, characterized in that, The thickness of the first tunneling oxide layer is 1.5-2 nm; and / or, The thickness of the second tunneling oxide layer is 1.5-2 nm; and / or, The thickness of the first oxide layer is 1-1.5 nm; and / or, The thickness of the second oxide layer is 1-1.5 nm. The thickness of the first doped polysilicon layer is 50-80 nm; and / or, The thickness of the second doped polysilicon layer is 80-150 nm; and / or, The thickness of the third doped polycrystalline silicon layer is 50-80 nm; and / or, The thickness of the fourth doped polysilicon layer is 80-150 nm; and / or, The first and second doped polysilicon layers are P-type; the third and fourth doped polysilicon layers are N-type.

5. The photovoltaic cell as described in claim 1, characterized in that, The back side is a tower base structure with a size of 5-15μm and a reflectivity of 30%-50%.

6. The photovoltaic cell as described in claim 1, characterized in that, The thickness of the first antireflective coating is less than the thickness of the second antireflective coating.

7. The photovoltaic cell as described in claim 1, characterized in that, The thickness of the first antireflective coating is 50-85 nm; and / or the thickness of the second antireflective coating is 75 nm-105 nm.

8. The photovoltaic cell as described in claim 1, characterized in that, The thickness of the alumina is 3-7 nm.

9. A photovoltaic module, characterized in that, Includes the photovoltaic cell described in any one of claims 1-8.

10. A photovoltaic system, characterized in that, Includes the photovoltaic module as described in claim 9.

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