Surge protection circuit and system thereof

Abstract

The utility model provides a surge protection circuit, which comprises a first switch tube, a first diode, a signal amplitude limiting circuit and a protection diode, and is characterized in that the anode of the first diode is coupled with the first pole of the first switch tube, and the cathode of the first diode is coupled with the second pole of the first switch tube; the first end of the signal amplitude limiting circuit is coupled with the cathode of the first diode; the anode of the protection diode is coupled to the first pole of the first switch tube, and the cathode is coupled to the second end of the signal amplitude limiting circuit. According to the utility model, on the premise of not increasing the complexity of external devices, the shunting proportion can be optimized according to the surge intensity, the surge protection efficiency is obviously improved, the cost and the packaging difficulty are low, and the structure is suitable for application scenes with low-current integrated MOSFETs and low conduction voltage drop requirements.

Description

Technical Field

[0001] This utility model relates to the field of surge protection technology, specifically but not limited to a surge protection circuit. Background Technology

[0002] In circuit applications, a surge is a transient overvoltage or overcurrent phenomenon that can be caused by lightning strikes, load switching, or electrostatic discharge (ESD). Without effective protection measures, surges can cause internal components of a chip (such as NMOS transistors) to break down or burn out. Therefore, designing simple and reliable surge protection circuits is crucial.

[0003] Common surge protection solutions currently include, for example Figure 1 As shown, it mainly includes: an NMOS transistor, a parasitic diode D1, and an external encapsulated protection diode D0. The NMOS transistor is integrated inside the chip and has a weak current capability. The parasitic diode D1 is the inherent body diode of the NMOS transistor and is connected in reverse parallel between the source and drain. The external encapsulated protection diode D0 is used to enhance surge withstand capability.

[0004] When a forward surge occurs between the source and drain of an NMOS transistor, the current path includes two paths: (1) D1 path: the surge current flows to the drain through the parasitic diode D1, and (2) D0 path: the surge current is shunted through the external diode D0. The specific shunting ratio is determined by the forward voltage drop (VF) of D1 and D0. If the forward voltage drop (VF) of D0 is high, most of the current flows to D1, which may cause D1 to be damaged by overcurrent. If the VF of D0 is low, D0 needs to bear a larger current, and a large-size or high-performance diode needs to be selected. If the total surge current is I, and the voltage drop of D1 when it flows through the maximum allowable current I1 is VF1, then the current capability of D0 when the voltage drop of D1 is VF1 should not be less than I-I1.

[0005] In view of this, a new structure is needed to solve at least some of the above problems. Utility Model Content

[0006] In response to at least one or more problems in the background art, this utility model proposes a surge protection circuit and system that, without increasing the complexity of external components, optimizes the current shunt ratio according to the surge intensity, significantly improves surge protection efficiency, and has low cost and packaging difficulty.

[0007] According to one aspect of the present invention, a surge protection circuit includes a first switching transistor, a first diode, a signal limiting circuit, and a protection diode, wherein:

[0008] The anode of the first diode is coupled to the first terminal of the first switching transistor, and the cathode is coupled to the second terminal of the first switching transistor.

[0009] The first terminal of the signal limiting circuit is coupled to the cathode of the first diode;

[0010] The anode of the protection diode is coupled to the first terminal of the first switching transistor, and the cathode is coupled to the second terminal of the signal limiting circuit.

[0011] Optionally, the first switching transistor is an NMOS transistor, with its source coupled to the anode of the first diode, its drain coupled to the cathode of the first diode, and its gate coupled to the MOS driving circuit.

[0012] Optionally, the first diode is a parasitic diode of an NMOS transistor.

[0013] Optionally, the signal limiting circuit includes a first resistor, with a first end coupled to the cathode of a first diode and a second end coupled to the cathode of a protection diode. The first resistor is used to limit the current flowing through the first diode.

[0014] Optionally, the signal limiting circuit includes a second diode, whose anode is coupled to the second end of the first resistor and whose cathode is coupled to the first end of the first resistor. The second diode is used to clamp the voltage drop of the first resistor.

[0015] According to another aspect of the present invention, a surge protection system includes a protected circuit and any of the above-mentioned surge protection circuits, wherein the third terminal of the first switching transistor is coupled to the protected circuit.

[0016] According to another aspect of the present invention, a surge protection circuit includes an NMOS transistor, a signal limiting circuit, and a protection diode, wherein:

[0017] The source of the NMOS transistor is coupled to the anode of the protection diode, the drain is coupled to the first terminal of the signal limiting circuit, and the gate is coupled to the MOS driving circuit.

[0018] The second terminal of the signal limiting circuit is coupled to the cathode of the protection diode.

[0019] Optionally, the NMOS transistor has a parasitic diode, the anode of which is coupled to the source of the NMOS transistor, and the cathode of which is coupled to the drain of the NMOS transistor.

[0020] According to another aspect of the present invention, a surge protection system includes a protected circuit and any of the above-described surge protection circuits, wherein the gate of the NMOS transistor is coupled to the protected circuit.

[0021] The surge protection circuit and system proposed in this invention can optimize the shunt ratio according to the surge intensity without increasing the complexity of external components, thus significantly improving the surge protection performance. At the same time, it has low cost and low packaging difficulty, and is suitable for application scenarios with low current integrated MOSFET and low on-state voltage drop requirements. Attached Figure Description

[0022] The accompanying drawings are provided to further illustrate the present invention and, together with the description, serve to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0023] Figure 1 A schematic diagram of a surge protection circuit structure in the prior art is shown;

[0024] Figure 2 A schematic diagram of a surge protection circuit structure according to an embodiment of the present invention is shown.

[0025] Figure 3 A schematic diagram of a surge protection circuit structure according to another embodiment of the present invention is shown. Detailed Implementation

[0026] To further understand this utility model, preferred embodiments of this utility model are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of this utility model, and not for limiting the scope of the claims of this utility model.

[0027] The description in this section pertains to only a few typical embodiments, and this utility model is not limited to the scope of the embodiments described. Combinations of different embodiments, substitution of some technical features in different embodiments, and substitution of the same or similar prior art with some technical features in the embodiments are also within the scope of the description and protection of this utility model.

[0028] The terms "coupled" or "connected" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as a connection through an electrically conductive medium like a conductor, which may contain parasitic inductance or capacitance. It can also be a connection through intermediate circuits or components described in the embodiments of this specification. Indirect connections may also include connections through other active or passive devices that achieve the same or similar function, such as connections through switches, signal amplification circuits, follower circuits, or other circuits or components. "Multiple" or "more" indicates two or more.

[0029] One embodiment of this utility model proposes a surge protection circuit, such as... Figure 2As shown, the circuit includes a first switching transistor, a first diode D1, a signal limiting circuit, and a protection diode D0. Specifically: the anode of the first diode D1 is coupled to the first terminal of the first switching transistor, and the cathode is coupled to the second terminal of the first switching transistor; the first diode D1 forms a reverse current discharge path. The first terminal of the signal limiting circuit is coupled to the cathode of the first diode D1, and the second terminal is coupled to the cathode of the protection diode D0; the signal limiting circuit forms a signal limiting path. The anode of the protection diode D0 is coupled to the first terminal of the first switching transistor, and the cathode is coupled to the second terminal of the signal limiting circuit; the protection diode D0 conducts when the forward surge voltage of the first switching transistor exceeds a threshold value.

[0030] In one embodiment, the first switch is an NMOS transistor, which has a source, a drain, and a gate, wherein the source is coupled to the anode of the first diode D1, the drain is coupled to the cathode of the first diode D1, and the gate is coupled to the MOS driving circuit.

[0031] In one specific embodiment, the first diode D1 is a parasitic diode of the NMOS transistor.

[0032] In another embodiment, the first switch can be a PMOS transistor.

[0033] In one embodiment, the signal limiting circuit includes a first resistor R1, with its first end coupled to the cathode of a first diode D1 and its second end coupled to the cathode of a protection diode D0. The first resistor R1 limits the current flowing through the first diode D1, reducing the requirement for the forward conduction voltage of the protection diode D0, thereby providing better protection for the NMOS transistor. By setting the first resistor R1 for current limiting, the current shunt ratio of the first diode D1 is actively controlled, preventing the first diode D1 from being damaged by overcurrent, allowing the protection diode D0 to operate at a higher forward conduction voltage VF, reducing its dependence on size and manufacturing process.

[0034] In another implementation, such as Figure 2As shown, the signal limiting circuit includes a first resistor R1 and a second diode D2. The first end of the first resistor R1 is coupled to the cathode of the first diode D1, and the second end is coupled to the cathode of the protection diode D0. The first resistor R1 limits the current flowing through the first diode D1, reducing the requirement for the forward conduction voltage of the protection diode D0, thereby providing better protection for the NMOS transistor. By setting the first resistor R1 for current limiting, the current shunting ratio of the first diode D1 is actively controlled when a surge occurs, preventing the first diode D1 from being damaged by overcurrent, allowing the protection diode D0 to operate at a higher forward conduction voltage VF, reducing its dependence on size and manufacturing process. The anode of the second diode D2 is coupled to the second end of the first resistor R1, and the cathode is coupled to the first end of the first resistor R1. The second diode D2 clamps the voltage drop across the first resistor R1 at its forward conduction voltage, effectively reducing the system's conduction loss. By setting the second diode D2 in parallel with the first resistor R1, its clamping of the voltage drop across the first resistor R1 ensures low conduction loss when the first switching transistor is operating normally.

[0035] The specific working principle of this embodiment is as follows: When a surge event occurs, the surge current shunting path includes a first path (D1+R1) and a second path (external D0). The first path (D1+R1) is a current-limiting path, and at this time, the second diode D2 does not participate in conduction due to reverse bias. The first resistor R1 limits the current I1 in the first path, causing the forward voltage drop VF0 of the protection diode D0 to rise and satisfy: VF0 = VF1 + I1 × R1, where VF1 is the forward voltage drop of the first diode D1. At this time, the shunting current of the protection diode D0 is I - I1, where I is the total surge current. The two paths work together to shunt the current, thereby regulating the voltage and current.

[0036] When the NMOS transistor is normally turned on, the operating current of the NMOS transistor flows to the drain of the first switching transistor through the parallel-connected second diode D2 and the first resistor R1. The second diode D2 is forward-biased and clamps the voltage drop across the first resistor R1 to the forward voltage drop VF2 of the second diode D2. Since the second diode D2 provides a low-resistance path, it avoids the first resistor R1 from conducting alone and generating a large voltage drop, effectively reducing system power consumption.

[0037] In this embodiment, the effective forward conduction voltage VF of the protection diode D0 is increased by the first resistor R1, relaxing the restrictions on its specifications. At the same time, the first resistor R1 limits the current I1 of the first diode D1, ensuring that its current I1 < the safety threshold. By setting a parallel structure of the second diode D2 and the first resistor R1, automatic path switching is achieved, and because the second diode D2 clamps the voltage drop of the first resistor R1, conduction loss is reduced.

[0038] According to one embodiment of the present invention, a surge protection system is proposed, including a protected circuit and any of the above-mentioned surge protection circuits, wherein the third terminal of the first switching transistor is coupled to the protected circuit.

[0039] Another embodiment of this utility model proposes a surge protection circuit, such as... Figure 3 As shown, the circuit includes an NMOS transistor, a signal limiting circuit, and a protection diode D0. The NMOS transistor has a source, a drain, and a gate. Its source is coupled to the anode of the protection diode D0, its drain is coupled to the first terminal of the signal limiting circuit, and its gate is coupled to a MOS driving circuit. The second terminal of the signal limiting circuit is coupled to the cathode of the protection diode D0. The signal limiting circuit is used to form a signal limiting path.

[0040] In one embodiment, the NMOS transistor has a parasitic diode D1', the anode of which is coupled to the source of the NMOS transistor, and the cathode of which is coupled to the drain of the NMOS transistor.

[0041] In a further embodiment, the signal limiting circuit includes a first resistor R1, with its first end coupled to the cathode of the parasitic diode D1' and its second end coupled to the cathode of the protection diode D0. The first resistor R1 is used to limit the current flowing through the parasitic diode D1', reducing the requirement for the forward conduction voltage of the protection diode D0, thereby providing better protection for the NMOS transistor. By setting the first resistor R1 for current limiting, the current shunting ratio of the parasitic diode D1' is actively controlled, preventing the parasitic diode D1' from being damaged by overcurrent, allowing the protection diode D0 to operate at a higher forward conduction voltage VF, reducing its dependence on size and process.

[0042] In another further implementation, such as Figure 3 As shown, the signal limiting circuit includes a first resistor R1 and a second diode D2. The first terminal of the first resistor R1 is coupled to the cathode of the parasitic diode D1', and the second terminal is coupled to the cathode of the protection diode D0. The first resistor R1 limits the current flowing through the parasitic diode D1'. The anode of the second diode D2 is coupled to the second terminal of the first resistor R1, and the cathode is coupled to the first terminal of the first resistor R1. The second diode D2 clamps the voltage drop across the first resistor R1 at its forward conduction voltage, effectively reducing the system's conduction loss. By setting the second diode D2 in parallel with the first resistor R1, and utilizing its clamping effect on the voltage drop across the first resistor R1, low conduction loss is ensured during normal operation of the NMOS transistor.

[0043] Those skilled in the art should know that the logic controls such as "high level" and "low level", "set" and "reset", "AND gate" and "OR gate", "non-inverting input" and "inverting input" in the logic control involved in the specification or drawings can be interchanged or changed, and the same function or purpose as the above embodiment can be achieved by adjusting the subsequent logic control.

[0044] The description and application of this utility model herein are illustrative and not intended to limit the scope of the utility model to the above embodiments. The effects or advantages described in the specification may not be apparent in actual experimental examples due to uncertainties in specific conditions or parameters or other factors, and such descriptions are not intended to limit the scope of the utility model. Variations and modifications to the embodiments disclosed herein are possible, and various substitutions and equivalent components of the embodiments are well known to those skilled in the art. It should be clear to those skilled in the art that this utility model can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts without departing from the spirit or essential characteristics of the utility model. Other variations and modifications can be made to the embodiments disclosed herein without departing from the scope and spirit of the utility model.

Claims

1. A surge protection circuit, characterized in that, It includes a first switching transistor, a first diode, a signal limiting circuit, and a protection diode, wherein: The anode of the first diode is coupled to the first terminal of the first switching transistor, and the cathode is coupled to the second terminal of the first switching transistor. The first terminal of the signal limiting circuit is coupled to the cathode of the first diode; The anode of the protection diode is coupled to the first terminal of the first switching transistor, and the cathode is coupled to the second terminal of the signal limiting circuit.

2. The surge protection circuit according to claim 1, characterized in that, The first switching transistor is an NMOS transistor, with its source coupled to the anode of the first diode, its drain coupled to the cathode of the first diode, and its gate coupled to the MOS driving circuit.

3. The surge protection circuit according to claim 2, characterized in that, The first diode is a parasitic diode of an NMOS transistor.

4. The surge protection circuit according to claim 1, characterized in that, The signal limiting circuit includes a first resistor, the first end of which is coupled to the cathode of a first diode, and the second end of which is coupled to the cathode of a protection diode. The first resistor is used to limit the current flowing through the first diode.

5. The surge protection circuit according to claim 4, characterized in that, The signal limiting circuit includes a second diode, whose anode is coupled to the second end of the first resistor and whose cathode is coupled to the first end of the first resistor. The second diode is used to clamp the voltage drop of the first resistor.

6. A surge protection system, characterized in that, It includes the protected circuit and the surge protection circuit according to any one of claims 1-5, wherein the third terminal of the first switching transistor is coupled to the protected circuit.

7. A surge protection circuit, characterized in that, It includes an NMOS transistor, a signal limiting circuit, and a protection diode, wherein: the source of the NMOS transistor is coupled to the anode of the protection diode, the drain is coupled to the first terminal of the signal limiting circuit, and the gate is coupled to the MOS driving circuit; The second terminal of the signal limiting circuit is coupled to the cathode of the protection diode.

8. The surge protection circuit according to claim 7, characterized in that, The NMOS transistor has a parasitic diode, the anode of which is coupled to the source of the NMOS transistor, and the cathode of which is coupled to the drain of the NMOS transistor.

9. A surge protection system, characterized in that, It includes the protected circuit and the surge protection circuit according to any one of claims 7-8, wherein the gate of the NMOS transistor is coupled to the protected circuit.

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