Dead time control circuit and drive circuit
By designing a dead-time control circuit, using components such as current sources and power transistors, and combining them with external resistors, precise control of the dead time is achieved, solving the problem of the unadjustable dead time in bridge converter circuits and improving the robustness and stability of motor drive.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- XIAMEN KIWI MICROELECTRONICS TECH CO LTD
- Filing Date
- 2025-04-21
- Publication Date
- 2026-04-14
AI Technical Summary
In existing bridge converter circuits, the dead time built into the chip is not adjustable and has poor accuracy, which leads to increased bridge arm shoot-through or delay, affecting the robustness of motor drive.
A dead-time control circuit was designed, including a current source, a power transistor, a voltage balancing circuit, and a charging and discharging circuit. The dead time is precisely controlled by an external resistor, which improves the robustness of the drive circuit.
It enables precise adjustment of dead time, avoids bridge arm shoot-through, and improves the reliability and stability of the drive circuit.
Smart Images
Figure CN224124050U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of power electronics and relates to a drive control technology, particularly a dead time control circuit and a drive circuit. Background Technology
[0002] Bridge converter circuits include half-bridge drive circuits and full-bridge drive circuits. A half-bridge drive circuit uses two switching devices to control the forward and reverse motion of the motor; these switching devices are typically power transistors. For example... Figure 1 As shown, one switching device Q1 is connected to the positive terminal of the power supply, and another switching device Q2 is connected to the negative terminal. The switching state of the two switching devices is controlled by the drive circuit to control the current flow, thereby controlling the direction of motor movement. A half-bridge drive circuit is suitable for applications that only require controlling the forward and reverse motion of the motor. A full-bridge drive circuit uses four switching devices to control the forward, reverse, and braking motion of the motor. Two switching devices are connected to the positive terminal of the power supply, and the other two are connected to the negative terminal. The switching state of the four switching devices is controlled to control the direction and magnitude of the current, thereby achieving precise control of the motor.
[0003] In bridge converter circuits, the dead time built into the chip is typically not adjustable and has poor accuracy. Too small a dead time can easily lead to shoot-through in the bridge arms, damaging the circuit. Conversely, too large a dead time increases delay and is detrimental to high-speed driving.
[0004] In view of this, a new structure is needed to solve at least some of the above problems. Utility Model Content
[0005] To address one or more problems in the prior art, this utility model proposes a dead-time control circuit and a drive circuit.
[0006] According to one aspect of the present invention, a dead-time control circuit is disclosed, the dead-time control circuit having a dead-time pin, the dead-time control circuit comprising:
[0007] The first current source is coupled to the supply voltage;
[0008] The first power transistor is coupled in series with the first current source;
[0009] A voltage balancing circuit, whose input is coupled to the first terminal of the first power transistor, and whose output is coupled to the dead-time pin; and
[0010] The dead time generation circuit includes a second power transistor and a charging / discharging circuit. The first terminal of the second power transistor is coupled to the supply voltage, and the second terminal of the second power transistor is coupled to ground. The first terminal of the charging / discharging circuit is coupled to the dead time pin, and the second terminal of the charging / discharging circuit is coupled to the control terminal of the second power transistor.
[0011] In one embodiment, the charging and discharging circuit includes:
[0012] A current mirror circuit, the first terminal of which is coupled to a dead-time pin;
[0013] A second current source, the first terminal of which is coupled to the second terminal of a current mirror circuit, and the second terminal of which is coupled to ground; and
[0014] The first capacitor has its first terminal coupled to the first terminal of the second current source, and its second terminal coupled to ground.
[0015] In one embodiment, the voltage balancing circuit includes:
[0016] A third power transistor, its first terminal coupled to a first current source, its second terminal coupled to the first terminal of the first power transistor, and its control terminal coupled to the first terminal of the third power transistor; and
[0017] The fourth power transistor is connected in series between the current mirror circuit and the dead time pin. Its first terminal is coupled to the first terminal of the current mirror circuit, its second terminal is coupled to the dead time pin, and its control terminal is coupled to the control terminal of the third power transistor.
[0018] In one embodiment, the current mirror circuit includes:
[0019] The fifth power transistor has its first terminal coupled to the supply voltage, its second terminal coupled to the dead-time pin, and its control terminal coupled to the second terminal of the fifth power transistor; and
[0020] The sixth power transistor has its first terminal coupled to the supply voltage, its second terminal coupled to the first capacitor, and its control terminal coupled to the control terminal of the fifth power transistor.
[0021] In one embodiment, the dead time generation circuit further includes a third current source connected in series between the current mirror circuit and the second power transistor. The first terminal of the third current source is coupled to the supply voltage, and the second terminal of the third current source is coupled to the first terminal of the second power transistor.
[0022] In one embodiment, both the first power transistor and the second power transistor are N-type metal-oxide-semiconductor field-effect transistors.
[0023] In one embodiment, both the fifth and sixth power transistors are P-type metal-oxide-semiconductor field-effect transistors.
[0024] In one embodiment, the dead time control circuit includes a hysteresis comparator circuit, the input of which is coupled to the first terminal of the second power transistor, and the output of which outputs a dead time control signal.
[0025] According to another aspect of the present invention, a driving circuit is disclosed, the driving circuit comprising the dead time control circuit as described in any of the preceding claims.
[0026] In one embodiment, the driving circuit includes a dead time control circuit and a driving signal generation circuit. The output terminal of the dead time control circuit is coupled to the driving signal generation circuit, and the output terminal of the driving signal generation circuit is used to couple to the switching transistor of the bridge circuit.
[0027] This invention proposes a dead-time control circuit and a drive circuit. The dead-time control circuit includes a dead-time pin. It comprises a first current source, a first power transistor, a voltage balancing circuit, and a dead-time generation circuit. The first current source is coupled to the supply voltage. The first power transistor is connected in series with the first current source. The input terminal of the voltage balancing circuit is coupled to the first terminal of the first power transistor, and the output terminal of the voltage balancing circuit is coupled to the dead-time pin. The dead-time generation circuit includes a second power transistor and a charging / discharging circuit. The first terminal of the second power transistor is coupled to the supply voltage, and the second terminal of the second power transistor is coupled to ground. The first terminal of the charging / discharging circuit is coupled to the dead-time pin, and the second terminal of the charging / discharging circuit is coupled to the control terminal of the second power transistor. This invention provides a dead-time control circuit and a drive circuit that can achieve precise control of the dead time by connecting a corresponding external resistor, thereby improving the robustness of the drive circuit. Attached Figure Description
[0028] The accompanying drawings are provided to further illustrate the present invention and, together with the description, serve to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:
[0029] Figure 1 A schematic diagram of the circuit structure of a prior art bridge converter circuit is shown.
[0030] Figure 2 A schematic diagram of the dead-time control circuit according to an embodiment of the present invention is shown. Detailed Implementation
[0031] To further understand this utility model, preferred embodiments of this utility model are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of this utility model, and not for limiting the scope of the claims of this utility model.
[0032] The description in this section pertains to only a few typical embodiments, and this utility model is not limited to the scope of the embodiments described. Combinations of different embodiments, substitution of some technical features in different embodiments, and substitution of the same or similar prior art with some technical features in the embodiments are also within the scope of the description and protection of this utility model.
[0033] The terms "coupled" or "connected" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as a connection through an electrically conductive medium like a conductor, which may contain parasitic inductance or capacitance. It can also be a connection through intermediate circuits or components described in the embodiments of this specification. Indirect connections may also include connections through other active or passive devices that achieve the same or similar functions, such as connections through switches, signal amplification circuits, follower circuits, or other circuits or components. "Multiple" or "more" indicates two or more. Furthermore, in this invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship or order between these technical features.
[0034] One embodiment of this utility model discloses a dead-time control circuit. For example... Figure 2As shown, the dead-time control circuit includes a power supply pin VDD, a ground pin GND, and a dead-time pin DT. The power supply pin VDD is coupled to the power supply voltage terminal to provide the power supply voltage, and the dead-time pin DT is connected to an external resistor RDT. The dead-time control circuit includes a first current source I1, a first power transistor NM1, a voltage balancing circuit, and a dead-time generation circuit. The first terminal of the first current source I1 is coupled to the power supply voltage terminal to obtain the power supply voltage VDD. The first terminal of the first power transistor NM1 is coupled to the second terminal of the first current source I1, the second terminal of the first power transistor NM1 is grounded, and the control terminal of the first power transistor NM1 is coupled to the first terminal of the first power transistor NM1. The input terminal of the voltage balancing circuit is coupled to the first terminal of the first power transistor NM1, and the output terminal of the voltage balancing circuit is coupled to the dead-time pin DT. The voltage balancing circuit is used to control the terminal voltage of the dead-time pin DT based on the terminal voltage of the first terminal of the first power transistor NM1. In one embodiment, the voltage balancing circuit controls the terminal voltage of the first terminal of the first power transistor NM1 to be equal to the terminal voltage of the dead-time pin DT. In another embodiment, the voltage balancing circuit controls the difference between the first terminal voltage of the first power transistor NM1 and the terminal voltage of the dead time pin DT to be within a preset range. In one embodiment, the dead time generation circuit includes a second power transistor NM2 and a charging / discharging circuit. The first terminal of the second power transistor NM2 is coupled to the supply voltage VDD, and the second terminal of the second power transistor NM2 is coupled to ground. The first terminal of the charging / discharging circuit is coupled to the dead time pin DT, and the second terminal of the charging / discharging circuit is coupled to the control terminal of the second power transistor NM2. The dead time control circuit proposed in this invention can achieve precise control of the dead time by connecting a corresponding external resistor.
[0035] In one embodiment, such as Figure 2 As shown, the charging / discharging circuit includes a current mirror circuit, a second current source I2, and a first capacitor C1. The first terminal of the current mirror circuit is coupled to the dead-time pin DT. The first terminal of the second current source I2 is coupled to the second terminal of the current mirror circuit, and the second terminal of the second current source I2 is coupled to ground. The first terminal of the first capacitor C1 is coupled to the first terminal of the second current source I2, and the second terminal of the first capacitor C1 is coupled to ground. Figure 2 In one embodiment, the current mirror circuit includes a fifth power transistor PM1 and a sixth power transistor PM2. The first terminal of the fifth power transistor PM1 is coupled to the supply voltage VDD, the second terminal of the fifth power transistor PM1 is coupled to the dead-time pin DT, and the control terminal of the fifth power transistor PM1 is coupled to the second terminal of the fifth power transistor PM1. The first terminal of the sixth power transistor PM2 is coupled to the supply voltage, the second terminal of the sixth power transistor PM2 is coupled to a first capacitor, and the control terminal of the sixth power transistor PM2 is coupled to the control terminal of the fifth and sixth power transistors PM1.
[0036] In one embodiment, the voltage balancing circuit includes a third power transistor NM3 and a fourth power transistor NM4. The first terminal of the third power transistor NM3 is coupled to a first current source, the second terminal of the third power transistor NM3 is coupled to the first terminal of the first power transistor, and the control terminal of the third power transistor NM3 is coupled to the first terminal of the third power transistor. The fourth power transistor NM4 is connected in series between the current mirror circuit and the dead-time pin. The first terminal of the fourth power transistor NM4 is coupled to the first terminal of the current mirror circuit, the second terminal of the fourth power transistor NM4 is coupled to the dead-time pin, and the control terminal of the fourth power transistor NM4 is coupled to the control terminal of the third power transistor.
[0037] In one embodiment, such as Figure 2 As shown, the dead time generation circuit also includes a third current source I3, which is connected in series between the current mirror circuit and the second power transistor NM2. The first terminal of the third current source I3 is coupled to the supply voltage VDD, and the second terminal of the third current source I3 is coupled to the first terminal of the second power transistor NM2.
[0038] In one embodiment, the first and second power transistors can be one of the following transistors: bipolar junction transistor (BJT), metal-oxide-semiconductor field-effect transistor (MOSFET), junction field-effect transistor (JFET), and insulated-gate bipolar transistor (IGBT). Preferably, both the first and second power transistors are N-type MOSFETs (NMOS transistors). The first terminal of the first power transistor is the drain, the second terminal is the source, and the control terminal is the gate. The first terminal of the second power transistor is the drain, the second terminal is the source, and the control terminal is the gate. In one embodiment, the third and fourth power transistors in the voltage balancing circuit are both NMOS transistors. The fifth and sixth power transistors are both P-type MOSFETs.
[0039] In one embodiment, the dead time control circuit includes a hysteresis comparator circuit CM, the input of which is coupled to the first terminal of the second power transistor, and the output of which outputs a dead time control signal OUT_DT.
[0040] Combination Figure 2It can be seen that this utility model uses an external resistor RDT selectively coupled to the dead time pin DT to adjust the dead time. In one embodiment, based on the voltage balance circuit, the terminal voltage of the dead time pin DT is fixed, and the terminal voltage of the dead time pin DT is equal to the voltage threshold of the first power transistor NM1, which can be denoted as the voltage threshold Vth_NM1. Then the charging current of the first capacitor C1 is Vth_NM1 / (2*RDT). The dead time is equal to the time to charge the first capacitor C1 to the voltage threshold Vth_NM2 of the second power transistor NM2. Therefore, DT / C1*Vth_NM1 / (2*RDT)=Vth_NM2, where DT is the dead time, C1 is the capacitance value of the first capacitor, and RDT is the resistance value of the external resistor. Here, the current ratio of the current mirror is 2:1. In one embodiment, the first power transistor NM1 and the second power transistor NM2 can be NMOS transistors of the same type, then Vth_NM1 = Vth_NM2, and thus DT = 2*RDT*C1. Since the capacitance value of the first capacitor C1 is fixed in a selected drive circuit, the dead time is inversely proportional to the resistance value of the external resistor. The required dead time can be obtained by adjusting this external resistor, thereby realizing the adjustment and selection of the dead time. By controlling the dead time, the dead time requirements of various drive circuits can be met, avoiding bridge arm shoot-through and damage to devices, and improving the robustness of the drive circuit.
[0041] Another embodiment of this utility model discloses a driving circuit, which includes a dead-time control circuit as described in any of the preceding embodiments. In one embodiment, the driving circuit includes a dead-time control circuit and a driving signal generation circuit. The output terminal of the dead-time control circuit is coupled to the driving signal generation circuit, and the output terminal of the driving signal generation circuit is used to couple to each switching transistor of the bridge circuit. By adjusting the appropriate dead time, the bridge converter circuit can be controlled to operate normally. The dead-time control circuit and driving circuit proposed in this utility model can achieve precise control of the dead time by connecting a corresponding external resistor.
[0042] Those skilled in the art should know that the logic controls such as "high level" and "low level", "set" and "reset", "AND gate" and "OR gate", "non-inverting input" and "inverting input" in the logic control involved in the specification or drawings can be interchanged or changed, and the same function or purpose as the above embodiment can be achieved by adjusting the subsequent logic control.
[0043] The description and application of this utility model herein are illustrative and not intended to limit the scope of the utility model to the above embodiments. The effects or advantages described in the specification may not be apparent in actual experimental examples due to uncertainties in specific conditions or parameters or other factors, and such descriptions are not intended to limit the scope of the utility model. Variations and modifications to the embodiments disclosed herein are possible, and various substitutions and equivalent components of the embodiments are well known to those skilled in the art. It should be clear to those skilled in the art that this utility model can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts without departing from the spirit or essential characteristics of the utility model. Other variations and modifications can be made to the embodiments disclosed herein without departing from the scope and spirit of the utility model.
Claims
1. A dead-time control circuit, characterized in that, The dead time control circuit is provided with a dead time pin, and the dead time control circuit includes: The first current source is coupled to the supply voltage; The first power transistor is coupled in series with the first current source; A voltage balancing circuit, whose input is coupled to the first terminal of the first power transistor, and whose output is coupled to the dead-time pin; and The dead time generation circuit includes a second power transistor and a charging / discharging circuit. The first terminal of the second power transistor is coupled to the supply voltage, and the second terminal of the second power transistor is coupled to ground. The first terminal of the charging / discharging circuit is coupled to the dead time pin, and the second terminal of the charging / discharging circuit is coupled to the control terminal of the second power transistor.
2. The dead-time control circuit as described in claim 1, characterized in that, The charging and discharging circuit includes: A current mirror circuit, the first terminal of which is coupled to a dead-time pin; A second current source, the first terminal of which is coupled to the second terminal of a current mirror circuit, and the second terminal of which is coupled to ground; and The first capacitor has its first terminal coupled to the first terminal of the second current source, and its second terminal coupled to ground.
3. The dead-time control circuit as described in claim 2, characterized in that, The voltage balancing circuit includes: A third power transistor, its first terminal coupled to a first current source, its second terminal coupled to the first terminal of the first power transistor, and its control terminal coupled to the first terminal of the third power transistor; and The fourth power transistor is connected in series between the current mirror circuit and the dead time pin. Its first terminal is coupled to the first terminal of the current mirror circuit, its second terminal is coupled to the dead time pin, and its control terminal is coupled to the control terminal of the third power transistor.
4. The dead-time control circuit as described in claim 2, characterized in that, The current mirror circuit includes: The fifth power transistor has its first terminal coupled to the supply voltage, its second terminal coupled to the dead-time pin, and its control terminal coupled to the second terminal of the fifth power transistor; and The sixth power transistor has its first terminal coupled to the supply voltage, its second terminal coupled to the first capacitor, and its control terminal coupled to the control terminal of the fifth power transistor.
5. The dead-time control circuit as described in claim 2, characterized in that, The dead time generation circuit also includes a third current source, which is connected in series between the current mirror circuit and the second power transistor. The first end of the third current source is coupled to the supply voltage, and the second end of the third current source is coupled to the first end of the second power transistor.
6. The dead-time control circuit as described in claim 2, characterized in that, Both the first power transistor and the second power transistor are N-type metal-oxide-semiconductor field-effect transistors.
7. The dead-time control circuit as described in claim 4, characterized in that, Both the fifth and sixth power transistors are P-type metal-oxide-semiconductor field-effect transistors.
8. The dead-time control circuit as described in claim 1, characterized in that, The dead time control circuit includes a hysteresis comparator circuit. The input terminal of the hysteresis comparator circuit is coupled to the first terminal of the second power transistor, and the output terminal of the hysteresis comparator circuit outputs a dead time control signal.
9. A driving circuit, characterized in that, The drive circuit includes the dead time control circuit as described in any one of claims 1-8.
10. The driving circuit as described in claim 9, characterized in that, The driving circuit includes a dead time control circuit and a driving signal generation circuit. The output of the dead time control circuit is coupled to the driving signal generation circuit, and the output of the driving signal generation circuit is used to couple to the switching transistor of the bridge circuit.