A high-duty-cycle control system for a step-down DC-DC switching power supply

Abstract

The application discloses a high-duty-cycle control system of a step-down DC-DC switching power supply, which is additionally provided with a high-duty-cycle control system on the basis of a basic structure of the switching power supply and comprises an LDO, a diode D2 for charging a capacitor C1 by the LDO, an error amplifier, a current comparator, an OR gate, a pulse generator, an RS latch and an under-voltage lockout circuit for detecting a voltage VBS between the capacitor C1. The under-voltage lockout circuit detects the voltage VBS between the capacitor C1, when the voltage is insufficient, temporarily turns off a charging switch tube M1, charges the capacitor C1 for providing a stable voltage power supply for a driving circuit during the turn-off of the M1, restores the power supply voltage of the driving circuit, and then reopens the M1, so as to realize the high-duty-cycle conduction of the NMOS type charging switch tube.

Description

Technical Field

[0001] This invention relates to switching power supplies, and more particularly to a high duty cycle control system for a step-down DC-DC switching power supply, belonging to the field of integrated circuit power management chip design technology. Background Technology

[0002] In buck DC-DC switching power supply chips, some applications require the input voltage to be lower than the set output voltage. In such cases, the power supply needs to operate at 100% duty cycle, meaning the charging switch is constantly on, and the output voltage equals the input voltage. Low-voltage buck DC-DC switching power supply chips typically use all low-voltage components, with the charging switch being a 5V PMOS, making high duty cycle control relatively easy. However, in high-voltage buck DC-DC switching power supply chips, the charging switch generally uses a high-voltage NMOS device. The driving circuit and controller circuit of the charging switch are powered by two independent power supplies. When the charging switch is on for a long time, the power supply voltage of the driving circuit also continuously decreases. When the voltage drops below the required minimum operating voltage, it becomes impossible to maintain the normal conduction of the NMOS switch. Proper control is needed to achieve continuous and stable conduction of the NMOS switch in high duty cycle mode for extended periods. Summary of the Invention

[0003] The purpose of this invention is to provide a high duty cycle control system for a buck DC-DC switching power supply, which can help a buck DC-DC switching power supply using an NMOS charging switch to maintain a high duty cycle even when the input voltage is lower than the set output voltage.

[0004] To achieve the above objectives, the present invention adopts the following technical solution: a high duty cycle control system for a step-down DC-DC switching power supply. The basic structure of the step-down DC-DC switching power supply includes an NMOS charging switch M1, a driving circuit for driving the switch M1, a capacitor C1 providing a regulated power supply for the driving circuit, a freewheeling diode D1, an inductor L1, an output filter capacitor C2, and feedback proportional resistors R1 and R2. The gate of the NMOS charging switch M1 is connected to the output of the driving circuit, and the drain of the NMOS charging switch M1 is connected to the power supply VIN. The source and substrate of the NMOS charging switch M1, and the cathode of the freewheeling diode D1 are connected to the power supply VIN. One end of inductor L1 is connected to floating ground SW. Capacitor C1 and the drive circuit are connected across the floating power supply BOOT and floating ground SW. The voltage between the floating power supply BOOT and floating ground SW is VBS. The voltage of floating ground SW varies between power supply VIN and ground GND. The anode of freewheeling diode D1 is grounded to GND. The other end of inductor L1 is connected to one end of filter capacitor C2 and one end of resistor R1 and serves as the output voltage terminal VOUT of the switching power supply. The other end of filter capacitor C2 is grounded to GND. The other end of resistor R1 is connected to one end of resistor R2 and generates feedback voltage FB. The other end of resistor R2 is grounded to GND.

[0005] Its features include: an added high duty cycle control system, comprising an oscillator LDO, a diode D2 for charging capacitor C1 via the oscillator LDO, an error amplifier, a current comparator, an OR gate, a pulse generator, an RS latch, and an undervoltage lockout circuit for detecting the voltage VBS across capacitor C1. The undervoltage lockout circuit is connected between the floating power supply BOOT and the floating ground SW. The oscillator LDO is powered by power supply VIN. The output of the oscillator LDO is connected to the anode of diode D2, and the cathode of diode D2 is connected to the floating power supply BOOT. The output of the undervoltage lockout circuit is connected to one end of the OR gate and the input of the pulse generator, and the other end of the OR gate is connected to the output of the current comparator. The positive input of the current comparator is connected to the floating ground SW and is used to detect the current flowing through the NMOS charging switch M1, i.e., the inductor current IL. The negative input of the current comparator is connected to the output of the error amplifier. The positive input of the error amplifier is connected to the reference voltage VREF. The negative input of the error amplifier is connected to the feedback voltage FB generated by the voltage divider of resistors R1 and R2. The output of the OR gate is connected to the input R of the RS latch. The output of the pulse generator is connected to the input S of the RS latch. The output Q of the RS latch is connected to the input of the drive circuit. In the above circuit, the oscillator LDO, error amplifier, current comparator, OR gate, pulse generator, and RS latch are all existing technologies.

[0006] When the input power supply voltage VIN is lower than the set output voltage VOUT, the feedback voltage FB is always lower than the reference voltage VREF. The reference current at the negative input of the current comparator controlled by the error amplifier output is at its maximum current. The inductor current IL flowing through the NMOS charging switch M1 is always lower than the reference current at the negative input of the current comparator. The comparison result of the current comparator will not reset and trigger the RS latch to turn off the charging switch M1. The charging switch M1 remains on. Due to the continuous current consumption of the charge in capacitor C1 by the internal circuits including the drive circuit, undervoltage lockout circuit, and other auxiliary circuits, the voltage VBS across capacitor C1 gradually decreases. The undervoltage lockout circuit detects the voltage VBS across C1. The undervoltage lockout circuit detects that VBS is lower than the minimum supply voltage required for the drive circuit to operate normally. When VBSL is reached, a reset signal is issued. The reset signal is logically ORed with the result of the current comparator, and then the RS latch is reset and triggered, turning off the charging switch M1. The reset signal is simultaneously input to the pulse generator and prevents the pulse generator from generating a set signal. This set signal will set the RS latch and turn the charging switch M1 back on. After the charging switch M1 is turned off, the voltage at node SW drops to ground potential GND. The oscillator LDO charges capacitor C1 through diode D2. When the undervoltage lockout circuit detects that VBS rises above the minimum supply voltage VBSL required for normal operation of the drive circuit, the reset signal disappears, allowing the pulse generator to set and trigger the RS latch. The charging switch M1 returns to the on state. The periodic long-term conduction of the charging switch M1 is achieved through the high duty cycle control system.

[0007] Preferably, the undervoltage lockout circuit includes a constant current source I1, PMOS transistors PM1, PM2, PM3, and PM4, NMOS transistors NM1, NM2, and NM3, inverters INV1 and INV2, and resistor R3. The input terminal of the constant current source I1 is connected to the drain and gate of PMOS transistor PM1, the gate of PMOS transistor PM2, and the gate of PMOS transistor PM3. The source and substrate of PMOS transistor PM1, the source and substrate of PMOS transistor PM2, and the source and substrate of PMOS transistor PM3 are all connected to the power supply BOOT. The drain of PMOS transistor PM2 is connected to the substrate and source of PMOS transistor PM4. The gate of PMOS transistor PM4... The gate and drain of NMOS transistor NM1 and the gate of NMOS transistor NM2 are connected. The source and substrate of NMOS transistor NM1 are connected to one end of resistor R3 and the drain of NMOS transistor NM3. The drain of PMOS transistor PM3 is connected to the drain of NMOS transistor NM2 and serves as the output of the undervoltage lockout circuit. It is connected to one end of the OR gate and the input of the pulse generator, and is also connected to the input of inverter INV1. The output of inverter INV1 is connected to the input of inverter INV2. The output of inverter INV2 is connected to the gate of NMOS transistor NM3. The output of constant current source I1, the source and substrate of NMOS transistor NM3, the other end of resistor R3, and the source and substrate of NMOS transistor NM2 are all connected to floating ground SW.

[0008] Furthermore, the PMOS transistors PM1, PM2, and PM3 are current mirror images of each other, with a size ratio of PM1:PM2:PM3 = 1:2:1; the size ratio of the NMOS transistors NM1 and NM2 is NM1:NM2 = 1:1.

[0009] Advantages and significant effects of the present invention: Based on the basic structure of a switching power supply, the present invention adds a high duty cycle control system. The voltage VBS across C1 is detected by an undervoltage lockout circuit. When the voltage is insufficient, the charging switch M1 is briefly turned off. During the turn-off of M1, the capacitor C1, which provides a regulated power supply to the drive circuit, is charged to restore the power supply voltage of the drive circuit. Then M1 is turned on again to realize the high duty cycle conduction operation of the NMOS type charging switch. Attached Figure Description

[0010] Figure 1 This is the circuit diagram of the present invention;

[0011] Figure 2 yes Figure 1 One implementation of the undervoltage lockout circuit used in the paper;

[0012] Figure 3 yes Figure 1Voltage waveform during operation. Detailed Implementation

[0013] Figure 1 This is a control system proposed to achieve high duty cycle operation of NMOS charging switches, based on the existing control architecture of buck DC-DC switching power supplies. The switching power supply section includes an NMOS charging switch M1, a drive circuit, a capacitor C1 providing regulated power for the drive circuit (BOOT), a freewheeling diode D1, an inductor L1, an output filter capacitor C2, and feedback proportional resistors R1 and R2. When the input voltage VIN is lower than the set output voltage VOUT, the feedback voltage FB is correspondingly lower than the reference voltage VREF. The error amplifier output voltage is at its highest voltage state, and the inductor current corresponding to the flip point of the controlled current comparator is at its maximum current value ILIM. The current IL flowing through M1 is equal to the output current IOUT and is lower than ILIM. The current comparator output will not flip, so the latch will not be reset and M1 will not be turned off. At this time, M1 remains in the conducting state. As the internal circuit continuously consumes the charge stored in C1, the voltage VBS across capacitor C1 will gradually decrease. When the undervoltage lockout circuit detects that the VBS voltage has dropped to the minimum supply voltage VBSL required for the drive circuit to operate normally, it will send a reset signal. The reset signal will reset the RS latch and then turn off the charging switch M1. At the same time, it will prevent the pulse generator from generating a set signal, so the latch will not be set. After M1 is turned off, the voltage at node SW drops to GND, and then the LDO module will charge capacitor C1 through diode D2. When the undervoltage lockout circuit detects that the VBS voltage rises to a VBSH voltage higher than the VBSL voltage, it releases the reset signal and allows the pulse generator module to send a set pulse. After setting the latch, M1 is turned on again. The on-time Ton of the charging switch is determined by the undervoltage lockout circuit's flip-point voltages VBSH and VBSL, capacitor C1, and the discharge current Idis of capacitor C1. The on-time calculation formula is Ton = (VBSH - VBSL) * C1 / Idis. The off-time Toff of M1 is determined by the undervoltage lockout circuit's flip-point voltages VBSH and VBSL, capacitor C1, and the current Icharge from the LDO to capacitor C1. The off-time calculation formula is Toff = (VBSH - VBSL) * C1 / Icharge. The ratio of on-time to off-time is approximately the ratio of the charging current to the discharging current of capacitor C1. By ensuring that Icharge is much greater than Idis, a high duty cycle operating mode with a high ratio of on-time to off-time of the charging switch can be achieved.

[0014] Figure 2This is a specific implementation of the undervoltage lockout circuit used in this invention, including a constant current source I1, which is used to bias PMOS transistor PM1. The output of constant current source I1 is connected to SW, and the input is connected to the gate and drain of PMOS transistor PM1. The source and substrate of PM1 are connected to the power supply BOOT. The gates of PMOS transistors PM2 and PM3 are connected to the gate of PM1. The sources and substrates of PM2 and PM3 are connected to the power supply BOOT. The drain of PM2 is connected to the substrate and source of PM4. PMOS transistors PM1, PM2, and PM3 are current mirrors with a size ratio of PM1:PM2:PM3 = 1:2:1. The gate and drain of PM4 are connected and then connected to the gate and drain of NMOS transistor NM1. The width-to-length ratio of PM4 is selected based on the power supply voltage inversion point. The substrate and source of NM1 are connected and then connected to one end of resistor R3. The other end of resistor R3 is connected to SW. The gate of S-channel transistor NM2 is connected to the gate of NM1. The substrate and source of NM2 are connected to SW. The drain of NM2 is connected to the drain of PM3. The size ratio of NM1 to NM2 is NM1:NM2 = 1:1. The drains of PM3 and NM2 are connected to the input of inverter INV1. The output of INV1 is connected to the input of inverter INV2. The output of INV2 is connected to the gate of NM3. The drain of NM3 is connected to one end of resistor R3. The substrate and source of NM3 are connected to SW. The aspect ratio of NM3 needs to be large enough. When the logic output of INV2 is "high", NM3 operates in the deep linear region conduction state to ensure that the on-resistance is much smaller than R3. The drain voltage of PM3 and NM2 is used as the detection output result UVLO_READYb. UVLO_READYb is fed back to the input of inverter INV1. By controlling NM3, resistor R3 can be approximately short-circuited.

[0015] The working principle is as follows: When the power supply voltage VBS is low, the output result UVLO_READYb is logic "1", NM3 is in the linear region conduction state, resistor R3 is approximately short-circuited to SW, NM1 and NM2 are approximately mirror images, and the current of PM3 in the saturation region is IDS1, which is equal to the current value of the constant current source I1. As the VBS voltage rises, the gate voltages of NM1 and NM2 also rise. When the current of NM2 exceeds the current of PM3 IDS1, the output result UVLO_READYb flips to logic "0", indicating that the power supply voltage meets the requirements. At this time, the current flowing through NM1 is also IDS1, and the corresponding VBS flip point voltage is VBSH = VGS2 + VGS4_1, where VGS2 is the gate-source voltage difference required for the current of NM2 to flow through IDS1 in the saturation region, and VGS4_1 is the gate-source voltage difference required for the current of PM4 to flow through IDS1 in the saturation region. According to the IV formula of MOS device saturation region, I = 1 / 2 μC ox ·W / L·(V GS -V th) 2 The specific aspect ratios of NM2 and PM4 corresponding to the VBSH toggle point voltage can be determined. The smaller the aspect ratios of NM2 and PM4, the higher the corresponding toggle point voltage. After UVLO_READYb toggles to logic "0", NM3 is in the off-state. At this time, the source of NM1 is connected to SW through resistor R3. In this operating state, when the gate voltage of NM1 is VGS2, the current flowing through it is IDS2. IDS2 is less than IDS1 due to the series connection of resistor R3. As the VBS voltage decreases, the gate voltage of NM2 also decreases. When the gate voltages of NM1 and NM2 drop below VGS2, the NM2 current is lower than the PM3 current IDS. When the output UVLO_READYb flips to logic "1", it is considered that the power supply voltage BOOT is in an undervoltage state. The corresponding VBS flip point voltage is VBSL = VGS2 + VGS4_2, where VGS4_2 is the gate-source voltage difference required for PM4 to flow through IDS2 in the saturation region. Since IDS2 is less than IDS1, VGS4_2 is lower than VGS4_1. Therefore, hysteresis detection of BOOT voltage can be achieved. By adjusting the resistance value of resistor R3, the difference between IDS1 and IDS2 can be adjusted, and then the difference between VGS4_1 and VGS4_2 can be adjusted, thereby adjusting the hysteresis of voltage VBS detection.

[0016] Figure 3 A schematic diagram of the voltage waveform during the operation of the main circuit of this invention is given. The diagram shows four complete switching cycles. In the initial state, the output signal UVLO_READYb of the undervoltage lockout circuit is logic "0", the NMOS charging switch M1 is in the on state, the SW voltage is equal to the VIN voltage, and the supply voltage VBS of the M1 drive circuit gradually decreases. When VBS is lower than VBSL, the output signal UVLO_READYb of the undervoltage lockout module flips to logic "1", the switch M1 is turned off, the pulse generator module stops generating the set pulse signal, the SW voltage drops to the GND voltage, the LDO module charges the capacitor C1, and the VBS voltage gradually rises. When VBS exceeds VBSH, the output signal UVLO_READYb of the undervoltage lockout circuit flips to logic "0", the pulse generator generates the set pulse signal to restore the conduction of the switch M1. It can be seen that the conduction time Ton of M1 is determined by the time required for the voltage VBS of capacitor C1 to discharge from VBSH to VBSL, and the turn-off time Toff is determined by the time required for the voltage VBS of capacitor C1 to charge from VBSL to VBSH.

Claims

1. A high duty cycle control system for a buck DC-DC switching power supply, the basic structure of which includes an NMOS charging switch M1, a driving circuit for driving the switch M1, a capacitor C1 providing a regulated power supply for the driving circuit, a freewheeling diode D1, an inductor L1, an output filter capacitor C2, and feedback proportional resistors R1 and R2; the gate of the NMOS charging switch M1 is connected to the output of the driving circuit, the drain of the NMOS charging switch M1 is connected to the power supply VIN, and the source and substrate of the NMOS charging switch M1, the cathode of the freewheeling diode D1, and one end of the inductor L1 are connected to... The floating ground SW is connected, capacitor C1 and the drive circuit are connected across the floating power supply BOOT and the floating ground SW. The voltage between the floating power supply BOOT and the floating ground SW is VBS. The voltage of the floating ground SW varies between the power supply VIN and the ground GND. The anode of the freewheeling diode D1 is grounded to GND. The other end of the inductor L1 is connected to one end of the filter capacitor C2 and one end of the resistor R1 and serves as the output voltage terminal VOUT of the switching power supply. The other end of the filter capacitor C2 is grounded to GND. The other end of the resistor R1 is connected to one end of the resistor R2 and generates the feedback voltage FB. The other end of the resistor R2 is grounded to GND. Its features are: A high duty cycle control system is added, including an oscillator LDO, diode D2, error amplifier, current comparator, OR gate, pulse generator, RS latch, and an undervoltage lockout circuit for detecting the voltage VBS across capacitor C1. The undervoltage lockout circuit is connected between the floating power supply BOOT and the floating ground SW. The oscillator LDO is powered by power supply VIN. The output of the oscillator LDO is connected to the anode of diode D2, and the cathode of diode D2 is connected to the floating power supply BOOT. The output of the undervoltage lockout circuit is connected to one end of the OR gate and the input of the pulse generator. The other end of the OR gate is connected to the output of the current comparator. The positive input of the current comparator is connected to the floating ground SW and is used to detect the current flowing through the NMOS charging switch M1, i.e., the inductor current IL. The negative input of the current comparator is connected to the output of the error amplifier. The positive input of the error amplifier is connected to the reference voltage VREF. The negative input of the error amplifier is connected to the feedback voltage FB generated by the voltage division of resistors R1 and R2. The output of the OR gate is connected to the input R of the RS latch. The output of the pulse generator is connected to the input S of the RS latch. The output Q of the RS latch is connected to the input of the drive circuit. When the input power supply voltage VIN is lower than the set output voltage VOUT, the feedback voltage FB is always lower than the reference voltage VREF. The reference current at the negative input of the current comparator controlled by the error amplifier output is at its maximum current. The inductor current IL flowing through the NMOS charging switch M1 is always lower than the reference current at the negative input of the current comparator. The comparison result of the current comparator will not reset and trigger the RS latch to turn off the charging switch M1. The charging switch M1 remains on. Due to the continuous current consumption of the charge in capacitor C1 by the internal circuits including the drive circuit, undervoltage lockout circuit, and other auxiliary circuits, the voltage VBS across capacitor C1 gradually decreases. The undervoltage lockout circuit detects the voltage VBS across C1. The undervoltage lockout circuit detects that VBS is lower than the minimum supply voltage required for the drive circuit to operate normally. When VBSL is reached, a reset signal is issued. The reset signal is logically ORed with the result of the current comparator, and then the RS latch is reset and triggered, turning off the charging switch M1. The reset signal is simultaneously input to the pulse generator and prevents the pulse generator from generating a set signal. This set signal will set the RS latch and turn the charging switch M1 back on. After the charging switch M1 is turned off, the voltage at node SW drops to ground potential GND. The oscillator LDO charges capacitor C1 through diode D2. When the undervoltage lockout circuit detects that VBS rises above the minimum supply voltage VBSL required for normal operation of the drive circuit, the reset signal disappears, allowing the pulse generator to set and trigger the RS latch. The charging switch M1 returns to the conducting state. The periodic long-term conduction of the charging switch M1 is achieved through the high duty cycle control system.

2. The high duty cycle control system for the step-down DC-DC switching power supply according to claim 1, characterized in that: The undervoltage lockout circuit includes a constant current source I1, PMOS transistors PM1, PM2, PM3, and PM4, NMOS transistors NM1, NM2, and NM3, inverters INV1 and INV2, and resistor R3. The input of the constant current source I1 is connected to the drain and gate of PMOS transistor PM1, the gate of PMOS transistor PM2, and the gate of PMOS transistor PM3. The source and substrate of PMOS transistor PM1, the source and substrate of PMOS transistor PM2, and the source and substrate of PMOS transistor PM3 are all connected to the power supply BOOT. The drain of PMOS transistor PM2 is connected to the substrate and source of PMOS transistor PM4. The gate of PMOS transistor PM4 and... The drain is connected to the gate and drain of NMOS transistor NM1 and the gate of NMOS transistor NM2. The source and substrate of NMOS transistor NM1 are connected to one end of resistor R3 and the drain of NMOS transistor NM3. The drain of PMOS transistor PM3 is connected to the drain of NMOS transistor NM2 and serves as the output of the undervoltage lockout circuit. It is connected to one end of the OR gate and the input of the pulse generator, and is also connected to the input of inverter INV1. The output of inverter INV1 is connected to the input of inverter INV2. The output of inverter INV2 is connected to the gate of NMOS transistor NM3. The output of constant current source I1, the source and substrate of NMOS transistor NM3, the other end of resistor R3, and the source and substrate of NMOS transistor NM2 are all connected to floating ground SW.

3. The high duty cycle control system for the step-down DC-DC switching power supply according to claim 2, characterized in that: The PMOS transistors PM1, PM2, and PM3 are current mirror images of each other, and their size ratio is PM1:PM2:PM3=1:2:

1.

4. The high duty cycle control system for the step-down DC-DC switching power supply according to claim 2, characterized in that: The size ratio of the NMOS transistors NM1 and NMOS transistors NM2 is NM1:NM2=1:1.

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