Photovoltaic cell

Abstract

The utility model provides a photovoltaic cell, and relates to the field of photovoltaic technology. A photovoltaic cell includes a substrate having a first surface, the first surface including a first region, a second region, and a third region between the first region and the second region; a tunneling oxide layer, a first doped silicon-containing layer and a conductive layer are sequentially stacked on the first region; an intrinsic silicon-containing layer, a second doped silicon-containing layer and a conductive layer are sequentially stacked on the second region; a tunneling oxide layer, a first doped silicon-containing layer, an intrinsic silicon-containing layer, a second doped silicon-containing layer and a conductive layer are sequentially stacked on the third region, and the doping type of the first doped silicon-containing layer is opposite to that of the second doped silicon-containing layer; the conductive layer has a first discontinuous structure on the first sub-region, the conductive layer has a second discontinuous structure on the second sub-region, and the first sub-region includes at least one of a portion of the first region adjacent to the third region and at least a portion of the third region. The photovoltaic cell structure is high in production yield.

Description

Technical Field

[0001] This utility model relates to the field of photovoltaic technology, and in particular to a photovoltaic cell. Background Technology

[0002] The statements in this section are merely background information related to this utility model and do not necessarily constitute prior art.

[0003] Heterojunction (HJT) solar cells are mainly composed of a PN heterojunction of silicon and doped amorphous silicon. An intrinsic amorphous silicon passivation layer is embedded at the heterojunction interface. Then, a transparent conductive oxide (TCO) thin film is prepared on both sides of the silicon wafer.

[0004] In recent years, back contact (BC) cell technology has been used to improve the photoelectric conversion performance of heterojunction cells. Specifically, all the grid electrodes of the cell are moved to the back of the cell, reducing the shading of sunlight by the grid lines, thereby improving the absorption efficiency of incident light and achieving higher conversion efficiency, thus forming back contact heterojunction cells (HBC).

[0005] In the HBC battery structure, both the P-region and N-region are located on the back of the battery, and TCO needs to be prepared on the surface of both. Due to the height difference between the P-region and N-region, it is impossible to accurately control the TCO preparation process, which leads to a decrease in battery yield. Utility Model Content

[0006] The purpose of this invention is to provide a photovoltaic cell to solve the technical problem of low yield of existing photovoltaic cell structures.

[0007] To achieve the above objectives, this utility model provides the following technical solution:

[0008] In a first aspect, this utility model provides a method for preparing a photovoltaic cell, comprising:

[0009] A substrate is provided, the substrate having a first surface, the first surface including a first region, a second region, and a third region located between the first region and the second region;

[0010] A tunneling oxide layer and a first doped silicon-containing layer are stacked sequentially on the first region; an intrinsic silicon-containing layer and a second doped silicon-containing layer are stacked sequentially on the second region; the tunneling oxide layer, the first doped silicon-containing layer, the intrinsic silicon-containing layer, and the second doped silicon-containing layer are stacked sequentially on the third region; and a conductive layer is stacked on the first doped silicon-containing layer in the first region and on the second doped silicon-containing layers in the second and third regions.

[0011] The conductive layer is removed stepwise using an etching method, specifically the portion opposite to the first sub-region and the portion opposite to the second sub-region. The first sub-region includes at least one of the portion of the first region adjacent to the third region and at least a portion of the third region. The second sub-region is the portion of the second region adjacent to the third region.

[0012] According to at least one embodiment of the present invention, the stepwise removal of the portion of the conductive layer opposite to the first sub-region and the portion opposite to the second sub-region using an etching method includes:

[0013] The etching solution is applied and removed in stages using a printing process, specifically the portion of the conductive layer opposite to the first sub-region and the portion opposite to the second sub-region.

[0014] According to at least one embodiment of the present invention, the printing process includes one or more of screen printing, laser transfer printing, and stencil printing.

[0015] According to at least one embodiment of the present invention, a first screen is covered on the portion of the conductive layer opposite to the second region, wherein the cutout area of ​​the first screen is opposite to the second sub-region.

[0016] A second screen is applied to the portion of the conductive layer opposite to the second region and / or the third region, wherein the cutout area of ​​the second screen is opposite to the first sub-region.

[0017] According to at least one embodiment of the present invention, the etching solution includes one or more of sulfuric acid and phosphoric acid; and / or,

[0018] The pH value of the etching solution ranges from 0 to 3.

[0019] According to at least one embodiment of the present invention, the width of the first sub-region ranges from 0.5 μm to 200 μm; and / or,

[0020] The width of the second sub-region ranges from 0.5μm to 200μm.

[0021] According to at least one embodiment of the present invention, the tunneling oxide layer, the first doped silicon-containing layer, the intrinsic silicon-containing layer, the second doped silicon-containing layer, and the conductive layer are sequentially stacked on the third region, and the method further includes:

[0022] A dielectric layer is stacked on a third region, the dielectric layer being located between the first doped silicon-containing layer and the intrinsic silicon-containing layer.

[0023] According to at least one embodiment of the present invention, a tunneling oxide layer and a first doped silicon-containing layer are sequentially stacked on the first region, including:

[0024] The tunneling oxide layer, the first doped silicon-containing layer, and the dielectric layer are sequentially stacked on the first surface;

[0025] Remove the tunneling oxide layer, the first doped silicon-containing layer, and the dielectric layer from the second region.

[0026] According to at least one embodiment of the present invention, the substrate has a second surface opposite to the first surface, and removing the tunneling oxide layer, the first doped silicon-containing layer, and the dielectric layer on the second region includes:

[0027] The dielectric layer on the second region is removed by laser film opening, and the tunneling oxide layer and the first doped silicon-containing layer on the second region are removed by chemical etching.

[0028] A texturing process is used to form a texturing structure on the second region and the second surface of the substrate, respectively; or,

[0029] The dielectric layer, the tunneling oxide layer, and the first doped silicon-containing layer on the second region are removed by laser film opening.

[0030] A texturing process is used to form a texturing structure on the second region and the second surface of the substrate, respectively.

[0031] According to at least one embodiment of the present invention, after forming a textured structure on the second region and the second surface of the substrate, the method further includes:

[0032] A passivation layer and an antireflection layer are sequentially stacked on the textured surface of the second surface;

[0033] When the intrinsic silicon-containing layer, the second doped silicon-containing layer, and the conductive layer are sequentially stacked on the second region, the following are included:

[0034] The intrinsic silicon-containing layer, the second doped silicon-containing layer, and the conductive layer are sequentially stacked on the textured structure in the second region.

[0035] According to at least one embodiment of the present invention, when the intrinsic silicon-containing layer, the second doped silicon-containing layer, and the conductive layer are sequentially stacked on the textured structure of the second region, the method includes:

[0036] The intrinsic silicon-containing layer and the second doped silicon-containing layer are stacked sequentially on the textured structure in the second region, the dielectric layer in the third region, and the dielectric layer in the first region;

[0037] Remove the intrinsic silicon-containing layer, the second doped silicon-containing layer, and the dielectric layer from the first region.

[0038] According to at least one embodiment of the present invention, removing the intrinsic silicon-containing layer, the second doped silicon-containing layer, and the dielectric layer on the first region includes:

[0039] The intrinsic silicon-containing layer and the second doped silicon-containing layer on the first region are removed by laser film opening;

[0040] The dielectric layer on the first region is removed by alkaline washing.

[0041] According to at least one embodiment of the present invention, after removing the intrinsic silicon-containing layer, the second doped silicon-containing layer, and the dielectric layer on the first region, the preparation method further includes:

[0042] The conductive layer is stacked on the second doped silicon-containing layer in the second region, on the second doped silicon-containing layer in the third region, and on the first doped silicon-containing layer in the first region, and the conductive layer is a monolithic structure.

[0043] Secondly, the present invention also provides a photovoltaic cell, including a substrate, the substrate having a first surface, the first surface including a first region, a second region and a third region located between the first region and the second region;

[0044] The first region has a tunneling oxide layer, a first doped silicon-containing layer, and a conductive layer stacked sequentially thereon; the second region has an intrinsic silicon-containing layer, a second doped silicon-containing layer, and the conductive layer stacked sequentially thereon; the third region has the tunneling oxide layer, the first doped silicon-containing layer, the intrinsic silicon-containing layer, the second doped silicon-containing layer, and the conductive layer stacked sequentially thereon, wherein the doping types of the first doped silicon-containing layer and the second doped silicon-containing layer are opposite.

[0045] The conductive layer has a first discontinuity structure in a first sub-region and a second discontinuity structure in a second sub-region, wherein the first sub-region includes at least one of the portion of the first region adjacent to the third region and at least a portion of the third region; the second sub-region is the portion of the second region adjacent to the third region.

[0046] According to at least one embodiment of the present invention, the width of the first sub-region ranges from 0.5 μm to 200 μm; and / or,

[0047] The width of the second sub-region ranges from 0.5μm to 200μm.

[0048] According to at least one embodiment of the present invention, the portion of the second doped silicon-containing layer opposite to the third region forms a height difference above the portion of the second doped silicon-containing layer opposite to the second region, and the value of the height difference ranges from 0.5 μm to 8 μm.

[0049] According to at least one embodiment of the present invention, a stepped surface is formed between the portion of the second doped silicon-containing layer opposite to the third region and the portion of the second doped silicon-containing layer opposite to the second region, and a portion of the conductive layer is disposed on the stepped surface.

[0050] According to at least one embodiment of the present invention, the photovoltaic cell further includes a dielectric layer, which is stacked on the third region and located between the first doped silicon-containing layer and the intrinsic silicon-containing layer.

[0051] According to at least one embodiment of the present invention, the substrate is either a p-type substrate or an n-type substrate.

[0052] According to at least one embodiment of the present invention, one of the first doped silicon-containing layer and the second doped silicon-containing layer is a p-type doped silicon-containing layer and the other is an n-type doped silicon-containing layer.

[0053] According to at least one embodiment of the present invention, the substrate has a second surface opposite to the first surface, and a passivation layer and an antireflection layer are sequentially stacked on the second surface.

[0054] According to at least one embodiment of the present invention, the second region and the second surface of the substrate are respectively formed with a textured structure.

[0055] According to at least one embodiment of the present invention, the tunneling oxide layer is made of silicon oxide and has a thickness of 0.5 nm to 3 nm; and / or,

[0056] The first doped silicon-containing layer is made of n-type doped polycrystalline silicon with a thickness of 30 nm to 300 nm; and / or,

[0057] The dielectric layer is made of at least one of silicon oxide, silicon nitride, and silicon oxynitride; and / or,

[0058] The intrinsic silicon-containing layer is made of at least one of microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, or silicon carbide; and / or,

[0059] The second doped silicon-containing layer is made of at least one of p-type doped microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, or silicon carbide; and / or,

[0060] The conductive layer is made of at least one of transparent conductive metal oxides or transparent conductive metal nitrides.

[0061] In one or more technical solutions provided in the exemplary embodiments of this utility model, at least one of the following beneficial effects can be achieved.

[0062] The photovoltaic cell of this exemplary embodiment divides a first surface (back side) of a substrate into a first region, a second region, and a third region separating the two. One of the first and second regions can be a P-region, and the other can be an N-region. Specifically, a tunneling oxide layer, a first doped silicon-containing layer, and a conductive layer are sequentially stacked on the first region; an intrinsic silicon-containing layer, a second doped silicon-containing layer, and a conductive layer are sequentially stacked on the second region; and a tunneling oxide layer, a first doped silicon-containing layer, an intrinsic silicon-containing layer, a second doped silicon-containing layer, and a conductive layer are sequentially stacked on the third region. This inevitably creates a height difference between the P-region and the N-region. Since each region has a conductive layer, it is necessary to disconnect the conductive layer between the P-region and the N-region to prevent short circuits. This photovoltaic cell structure uses an etching method to remove the conductive layer near both sides of the third region, thereby separating the conductive layer between the P-region and the N-region. The two sides of the third region are also the positions of the first sub-region and the second sub-region. The first sub-region is a small portion of the first region adjacent to the third region, and the second sub-region is a small portion of the second region adjacent to the third region.

[0063] Compared to existing technologies that use paste etching to simultaneously etch the first, second, and third sub-regions, the simultaneous etching of these three regions results in uneven stress on the printing screen due to the height difference between the P and N regions and the different cell structures, making accurate printing precision impossible to control. However, the photovoltaic cell structure of this exemplary embodiment allows for simultaneous etching of the first and second sub-regions. Instead, one region is etched first, followed by the other, without etching the third region. This step-by-step etching overcomes the etching offset problem caused by the height difference between the P and N regions, extends the lifespan of the printing screen, and minimizes the defect rate of the photovoltaic cells.

[0064] In the photovoltaic cell of the exemplary embodiment of this utility model, a portion of the conductive layer is retained in the third region, which allows light inside the cell to pass from the high refractive index to the low refractive index, increasing the internal light reflectivity, thereby increasing the secondary absorption of light and improving the utilization rate of sunlight.

[0065] Furthermore, since the etched area does not include the third region, it is smaller than the etched area of ​​the prior art, and has less impact on the passivation layer below the conductive layer, thereby protecting the integrity of the passivation structure and reducing the impact on battery efficiency.

[0066] Compared to the existing technology that uses laser film-opening to disconnect the conductive layer between the P-region and N-region for insulation, the preparation method of the exemplary embodiment of this invention can use a slurry etching process, which can avoid laser damage to the battery and increase the photoelectric conversion efficiency of the battery to a certain extent. Attached Figure Description

[0067] The accompanying drawings illustrate exemplary embodiments of the present invention and, together with the description thereof, serve to explain the principles of the present invention. These drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification.

[0068] Figure 1 This is a schematic diagram of the photovoltaic cell preparation method according to an embodiment of the present invention;

[0069] Figures 2 to 9 This is a schematic cross-sectional view of the process structure after each step in the photovoltaic cell preparation method according to the embodiments of this utility model.

[0070] Reference numerals: 10, substrate; 11, first surface; 12, second surface; 11a, first textured surface; 12a, second textured surface;

[0071] 21. First doped silicon-containing layer; 22. Tunneling oxide layer; 23. Dielectric layer;

[0072] 31. Intrinsic silicon-containing layer; 32. Second-doped silicon-containing layer;

[0073] 41. Passivation layer; 42. Anti-reflection layer;

[0074] 50. Conductive layer;

[0075] 61. First electrode; 62. Second electrode. Detailed Implementation

[0076] To make the technical problems, technical solutions, and beneficial effects of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.

[0077] HBC cells can achieve a maximum photoelectric conversion efficiency of 27.1%. Both the P-region and N-region are located on the same side of the substrate, and both surfaces need to be covered with a conductive layer, such as a TCO layer. In the HBC cell fabrication process, the TCO layer needs to be broken at the interface between the P-region and N-region for insulation. Related technologies use laser grooving to break this interface, but this process damages the functional layer beneath the TCO layer, reducing the cell's photoelectric conversion efficiency. Alternatively, using etchant printing to break the TCO layer at the interface in one step can cause printing misalignment due to the height difference between the P-region and N-region.

[0078] To address the aforementioned issues, the photovoltaic cell fabrication method provided by the exemplary embodiment of this utility model employs a step-by-step etching method with etchant paste to form discontinuous structures in the adjacent boundary regions of the TCO layers in the P and N regions. This avoids printing misalignment caused by height differences and reduces the etched area to minimize the impact on the cell's photoelectric conversion efficiency.

[0079] It should be noted that the photovoltaic cell preparation method provided in the exemplary embodiment of this utility model is applicable not only to HBC cells, but also to other types of photovoltaic cells using BC cell technology.

[0080] Figure 1 This is a schematic diagram of the photovoltaic cell preparation method according to an embodiment of the present invention; Figures 2 to 9 This is a schematic cross-sectional view of the process structure after each step in the photovoltaic cell fabrication method according to the embodiments of this utility model. For example... Figure 1 As shown in the exemplary embodiment of this utility model, a method for preparing a photovoltaic cell is provided, which may include the following steps:

[0081] Step 101: Provide a substrate 10, the substrate 10 having a first surface 11 and a second surface 12 opposite to each other, the first surface 11 including a first region E1, a second region E2 and a third region E3 located between the first region E1 and the second region E2, such as Figure 2 As shown.

[0082] For example, the substrate 10 can be a silicon substrate, such as a p-type silicon substrate or an n-type silicon substrate. The following description uses an n-type silicon substrate as an example. The front side (light-receiving surface) of the substrate 10 is the second surface 12, and the back side is the first surface 11.

[0083] It should be noted that, Figure 2 The first surface 11 of the substrate 10 does not have only one set of first region E1, second region E2 and third region E3, but may have multiple sets of the above-mentioned regions.

[0084] For example, the first surface 11 may have a first region E1, a third region E3, a second region E2, a third region E3, a first region E1, a third region E3, and a second region E2 arranged sequentially; or, the first surface 11 may have a first region E1, a third region E3, a second region E2, a third region E3, a second region E2, a third region E3, and a first region E1 arranged sequentially, that is, each group of regions has a third region E3.

[0085] Step 102: A tunneling oxide layer 22, a first doped silicon-containing layer 21, and a conductive layer 50 are sequentially stacked on the first region E1; an intrinsic silicon-containing layer 31, a second doped silicon-containing layer 32, and a conductive layer 50 are sequentially stacked on the second region E2; and a tunneling oxide layer 22, a first doped silicon-containing layer 21, an intrinsic silicon-containing layer 31, a second doped silicon-containing layer 32, and a conductive layer 50 are sequentially stacked on the third region E3, forming a structure as shown in the figure. Figure 7 The structure shown.

[0086] Step 1021: Texturing / polishing is performed on the first surface 11 and the second surface 12 of the substrate 10 (silicon substrate) to form a tower base structure, such as... Figure 2 As shown.

[0087] In practical applications, a textured surface can be formed on both the first surface 11 and the second surface 12 of the substrate 10 through alkaline washing. Simultaneously, alkaline washing removes contaminants, impurities, and metal ions from the surface of the substrate 10, followed by polishing. The alkaline etching solution used for the alkaline washing can be potassium hydroxide, sodium hydroxide, etc. The tower base structure is the bottom structure remaining after the textured surface has been polished.

[0088] Step 1022: A tunneling oxide layer 22, a first doped silicon-containing layer 21, and a dielectric layer 23 are sequentially stacked on the first surface 11 to form a structure as shown in the figure. Figure 3 The structure shown.

[0089] A tunneling oxide layer 22, a first doped silicon-containing layer 21, and a dielectric layer 23 can be deposited sequentially on the substrate 10 over the entire area of ​​the first surface 11.

[0090] The deposition process can be carried out by any one of the following deposition methods or a combination of multiple deposition methods: vacuum evaporation, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0091] The following example illustrates the formation of an n-region (negative electrode region) in the first region E1, a p-region (positive electrode region) in the second region E2, and an intervening region between the p-region and the n-region in the third region E3.

[0092] For example, the tunneling oxide layer 22 is a silicon oxide layer with a thickness of 0.5 nm to 3.0 nm, such as 0.7 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, etc. By reasonably controlling the thickness of the tunneling oxide layer 22, the collection probability of majority carriers can be increased, thereby improving the photoelectric conversion efficiency of the battery.

[0093] For example, the material of the first doped silicon layer 21 is n-type doped polycrystalline silicon, and the thickness is 30nm to 300nm, such as 60nm, 70nm, 80nm, 100nm, 150nm, 200nm, 250nm, etc.

[0094] For example, the dielectric layer 23 is made of at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0095] Step 1023: Remove the tunneling oxide layer 22, the first doped silicon-containing layer 21, and the dielectric layer 23 on the second region E2 to form a structure as shown in the figure. Figure 4 The structure shown.

[0096] A combination of one or more methods, such as laser lift-off or chemical cleaning etching, is used to remove the tunneling oxide layer 22, the first doped silicon-containing layer 21, and the dielectric layer 23 on the second region E2.

[0097] For example, the dielectric layer 23 on the second region E2 is removed by laser film opening, and the tunneling oxide layer 22 and the first doped silicon-containing layer 21 on the second region E2 are removed by chemical etching; further, a textured structure is formed on the second region E2 and the second surface 12 of the substrate 10 by texturing.

[0098] Specifically, after removing the tunneling oxide layer 22 and the first doped silicon-containing layer 21 on the second region E2 by alkaline etching, a first textured structure 11a and a second textured structure 12a are formed on the exposed substrate 10 in the second region E2 and on the second surface 12, respectively, through texturing. These textured structures can be pyramidal in shape. The chemical etching can include alkaline solutions and acid solutions; the alkaline solution can be sodium hydroxide, and the acid solution can be hydrofluoric acid or nitric acid. The chemical reagent used in the texturing process can also be an alkaline solution.

[0099] In another optional embodiment, the dielectric layer 23, the tunneling oxide layer 22 and the first doped silicon-containing layer 21 on the second region E2 are removed by laser film opening; and a textured structure is formed on the second region E2 and the second surface 12 of the substrate 10 by texturing.

[0100] The specific process of laser film removal (laser ablation) involves emitting a laser beam from a laser source and using the laser to bombard the surface to remove the corresponding layer.

[0101] Step 1024a: An intrinsic silicon-containing layer 31 and a second doped silicon-containing layer 32 are sequentially stacked on the first textured structure 11a of the second region E2, the dielectric layer 23 of the third region E3, and the dielectric layer 23 of the first region E1, to form a structure as shown in the figure. Figure 5 The structure shown.

[0102] An intrinsic silicon-containing layer 31 is first deposited on the first textured structure 11a of the second region E2, the dielectric layer 23 of the third region E3, and the dielectric layer 23 of the first region E1 by chemical deposition, and then a second doped silicon-containing layer 32 is deposited.

[0103] For example, the intrinsic silicon-containing layer 31 is made of at least one of microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, or silicon carbide. For instance, the intrinsic silicon-containing layer 31 is a single layer with the same properties, or a multilayer or stack of several different properties, or a mixture of silicon-containing thin films, such as microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, or silicon carbide.

[0104] For example, the second doped silicon-containing layer 32 is at least one of p-type doped microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, or silicon carbide. For instance, it is a single layer with the same properties or a multilayer or stack of several types of silicon-containing thin films with different properties, such as boron-doped microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, or silicon carbide.

[0105] For example, the thickness of the second doped silicon-containing layer 32 is 30nm to 300nm, such as 60nm, 70nm, 80nm, 100nm, 150nm, 200nm, 250nm, etc.

[0106] Step 1024b: Passivation layer 41 and antireflection layer 42 are sequentially stacked on the textured surface of the second surface 12 to form a structure as shown in the figure. Figure 5 The structure shown.

[0107] A passivation layer 41 is first deposited on the textured surface (second textured surface 12a) of the second surface 12 by chemical deposition, followed by the deposition of an antireflection layer 42.

[0108] For example, the passivation layer 41 is one of the intrinsic silicon-containing layer 31, the second doped silicon-containing layer 32, or a combination of the intrinsic silicon-containing layer 31 and the second doped silicon-containing layer 32, wherein the thickness of the intrinsic silicon-containing layer 31 is 1 nm to 15 nm, and the thickness of the second doped silicon-containing layer 32 is 0 nm to 15 nm.

[0109] For example, the antireflection layer 42 is made of at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride, aluminum oxynitride, magnesium fluoride, lithium fluoride, ITO, and zinc oxide, and has a thickness of 40nm to 200nm, such as 60nm, 70nm, 80nm, 100nm, 150nm, 190nm, etc.

[0110] It should be noted that the passivation layer 41 formation step in this step can be carried out simultaneously with the formation of the intrinsic silicon-containing layer 31 and the second doped silicon-containing layer 32 in step 1024, thereby shortening the process flow and simplifying the operation.

[0111] Step 1025: Removing the intrinsic silicon-containing layer 31, the second doped silicon-containing layer 32, and the dielectric layer 23 on the first region E1 includes: removing the intrinsic silicon-containing layer 31 and the second doped silicon-containing layer 32 on the first region E1 by laser film opening; removing the dielectric layer 23 on the first region E1 by alkaline washing, forming as shown in the figure. Figure 6 The structure shown.

[0112] In practical applications, on the first region E1, the intrinsic silicon-containing layer 31 and the second doped silicon-containing layer 32 are first removed by laser film opening; then, the dielectric layer 23 is etched away by alkaline washing, such as by sodium hydroxide or potassium hydroxide solution, to expose the first doped silicon-containing layer 21.

[0113] Step 1026: A conductive layer 50 is stacked on the second doped silicon-containing layer 32 in the second region E2, the second doped silicon-containing layer 32 in the third region E3, and the first doped silicon-containing layer 21 in the first region E1, to form a conductive layer 50. Figure 7 The structure shown.

[0114] In practical applications, the structural surface formed on the first surface 11 of the substrate 10 in step 1025 is used to form an integrally molded conductive layer 50 by chemical deposition.

[0115] The conductive layer 50 is made of at least one of transparent conductive metal oxide or transparent conductive metal nitride.

[0116] Specifically, the conductive layer 50 is a TCO film layer, which is a multilayer or stacked layer or mixture of one or more doped metal oxides or nitrides. The metal oxides can be indium oxide, tin oxide, zinc oxide, cadmium oxide, or titanium nitride, and the metal nitrides can be titanium nitride. The doping elements can be indium, tin, calcium, aluminum, cadmium, zinc, cerium, or fluorine.

[0117] Step 103: Using an etching method, remove the portions of the conductive layer 50 opposite to the first sub-region E11 and the portions opposite to the second sub-region E22 in stages; wherein, the first sub-region E11 is the portion of the first region E1 adjacent to the third region E3; and the second sub-region E22 is the portion of the second region E2 adjacent to the third region E3, forming a layer as shown in the figure. Figure 8 The structure shown.

[0118] In practical applications, the first sub-region E11 is a portion of the first region E1, the width of which is approximately the same as the width of the third region E3, and this portion is adjacent to the third region E3; the second sub-region E22 is a portion of the second region E2, the width of which is approximately the same as the width of the third region E3, and this portion is adjacent to the third region E3; that is, the first sub-region E11 and the second sub-region E22 are located on both sides of the third region E3, respectively.

[0119] For example, the width of the first sub-region E11 ranges from 0.5μm to 200μm, such as 1μm, 5μm, 10μm, 50μm, 100μm, 130μm, 150μm, 170μm, 190μm, etc.

[0120] For example, the width of the second sub-region E22 ranges from 0.5μm to 200μm, such as 1μm, 5μm, 10μm, 50μm, 100μm, 130μm, 150μm, 170μm, 190μm, etc.

[0121] The etching method uses an etching solution to etch the conductive layer 50 to form a first discontinuity structure and a second discontinuity structure on both sides of the third region E3, so that the conductive layer 50 on the first region E1 is electrically insulated from the conductive layer 50 on the third region E3, and the conductive layer 50 on the second region E2 is electrically insulated from the conductive layer 50 on the third region E3. That is, the conductive layer 50 on the first region E1 is electrically insulated from the conductive layer 50 on the second region E2.

[0122] For example, the etching paste can be made of sulfuric acid, phosphoric acid, etc., with a pH value of 0 to 3.

[0123] For example, the printing process may be one or more of the following combined: screen printing, laser transfer printing, stencil printing, etc., which can achieve a similar graphic scheme.

[0124] Specifically, the etching method uses a printing process to apply etching paste to the first sub-region E11 or the second sub-region E22, thereby etching the corresponding conductive layer 50. In the step-by-step etching method, two screens can be used. First, the first screen is used to apply the etching paste to one sub-region, and then the second screen is used to apply the etching paste to the other sub-region.

[0125] Specifically, both the first and second screens have cutout areas. These cutout areas are aligned with the corresponding first sub-region E11 or second sub-region E22. An etching paste is applied to the first sub-region E11 or second sub-region E22 through the cutout areas using a squeegee, etching the corresponding conductive layer 50 to form an intermittent structure for electrical insulation. For example, the first and second screens can be the same or different, depending on the actual sub-region to be etched.

[0126] The order in which the conductive layers 50 of the first sub-region E11 and the second sub-region E22 are etched is not important.

[0127] In other embodiments, the first sub-region E11 may be the portion of the first region E1 adjacent to the third region E3, or it may be a part or all of the third region E3, or it may be a part of the third region E3 and the portion of the first region E1 adjacent to the third region E3; or it may be all of the third region E3 and the portion of the first region E1 adjacent to the third region E3.

[0128] Therefore, the step-by-step etching method avoids the problem of inaccurate printing precision control caused by the height difference between the first sub-region E1 and the second sub-region E2 in the synchronous etching method (which uses the same screen to print strong acid slurry on the first sub-region E11, the second sub-region E22, and the third sub-region E3 simultaneously). It also avoids the problem of uneven stress during synchronous printing due to height differences, resulting in a short screen lifespan.

[0129] Compared to laser grooving to disconnect the conductive layer 50 on the first region E1 and the second region E2, screen printing etching has less impact on the passivation structure beneath the conductive layer 50, and thus less impact on battery efficiency.

[0130] Furthermore, the step-by-step etching preserves the conductive layer 50 on the third region E3, and the smaller etching area protects the integrity of the passivation structure.

[0131] Meanwhile, retaining the conductive layer 50 in the third region E3 allows light inside the battery to pass from the high refractive index to the low refractive index, increasing the internal light reflectivity and thus increasing secondary absorption of light, thereby improving the utilization rate of sunlight. Retaining the dielectric layer 23 in the third region E3 also increases the internal light reflectivity of the battery, which is beneficial for improving the utilization rate of sunlight.

[0132] In some other embodiments, when the first sub-region E11 includes part or all of the third region E3, the portion of the conductive layer 50 opposite to the third region E3 is partially or completely etched away.

[0133] The portion of the second doped silicon-containing layer 32 opposite to the third region E3 forms a height difference above the portion of the second doped silicon-containing layer 32 opposite to the second region E2. The height difference ranges from 0.5 μm to 8 μm. For example, the height difference is 0.7 μm, 1 μm, 3 μm, 5 μm, 7 μm, etc.

[0134] As can be seen from the above, the portion of the second doped silicon-containing layer 32 opposite to the third region E3 and the portion of the second doped silicon-containing layer 32 opposite to the second region E2 form a stepped surface. This stepped surface is approximately perpendicular to the distribution direction from the first region E1 to the second region E2. However, the present invention uses a step-by-step etching method, and the coating area of ​​the etching paste avoids this stepped surface. The conductive layer 50 is deposited on this stepped surface during the formation process. Therefore, this stepped surface will retain a portion of the conductive layer 50.

[0135] Step 104: Metal electrodes are formed on the structures in the first region E1 and the second region E2, respectively, forming as shown in the figure. Figure 9 The structure shown.

[0136] In practical applications, a first electrode 61 is disposed on the conductive layer 50 in the first region E1; and a second electrode 62 is disposed on the conductive layer 50 in the second region E2.

[0137] Corresponding metal electrodes are fabricated on the first region E1 and the second region E2 by printing electrode paste. For example, one end of the first electrode 61 is located outside the conductive layer 50, and the other end is located inside the corresponding conductive layer 50; one end of the second electrode 62 is located outside the conductive layer 50, and the other end is located inside the corresponding conductive layer 50, thereby forming a photovoltaic cell.

[0138] For example, when the first doped silicon layer 21 is a boron-doped silicon layer, the first electrode 61 is a positive electrode, and correspondingly, the second electrode 62 is a negative electrode.

[0139] In some embodiments, when the first doped silicon layer 21 is a phosphorus-doped silicon layer, the first electrode 61 is a negative electrode, and correspondingly, the second electrode 62 is a positive electrode.

[0140] For example, the first electrode 61 and the second electrode 62 can be one or more stacks of silver electrode, silver alloy electrode, copper electrode, copper alloy electrode, nickel / copper / silver multilayer electrode.

[0141] like Figure 8 As shown, an exemplary embodiment of this utility model provides a photovoltaic cell, which is prepared by the photovoltaic cell preparation method described in the above embodiment.

[0142] like Figure 9 As shown, an exemplary embodiment of the present invention also provides a photovoltaic cell, including a substrate 10, the substrate 10 having a first surface 11, the first surface 11 including a first region E1, a second region E2 and a third region E3 located between the first region E1 and the second region E2.

[0143] A tunneling oxide layer 22, a first doped silicon-containing layer 21, and a conductive layer 50 are sequentially stacked on the first region E1; an intrinsic silicon-containing layer 31, a second doped silicon-containing layer 32, and a conductive layer 50 are sequentially stacked on the second region E2; and a tunneling oxide layer 22, a first doped silicon-containing layer 21, an intrinsic silicon-containing layer 31, a second doped silicon-containing layer 32, and a conductive layer 50 are sequentially stacked on the third region E3. The doping types of the first doped silicon-containing layer 21 and the second doped silicon-containing layer 32 are opposite.

[0144] The conductive layer 50 on the first region E1 has a first discontinuity structure on the first sub-region E11, and the conductive layer 50 on the second region E2 has a second discontinuity structure on the second sub-region E22. The first sub-region E11 includes at least one of the portion of the first region E1 adjacent to the third region E3 and at least one portion of the third region E3. The second sub-region E22 is the portion of the second region E2 adjacent to the third region E3.

[0145] The conductive layers on the first region E1 and the second region E2 form an electrical isolation between regions of opposite polarity by forming a first discontinuity structure on the first sub-region E11 and a second discontinuity structure on the second sub-region E22. This electrical isolation, compared to achieving electrical isolation through a complete discontinuity structure spanning the third region E3 on the conductive layer, overcomes the screen misalignment problem caused by the height difference between the third region E3 and the second region E2 when printing the etch paste. When the first sub-region E11 includes a portion of the third region E3 or does not include the third region E3, the corresponding portion of the conductive layer 50 and the third region E3 is preserved. This results in a smaller etched area when etching to form the discontinuity structure, thus protecting the integrity of the passivation structure beneath the conductive layer and minimizing the impact on battery efficiency.

[0146] In some implementations, the width of the first sub-region E11 ranges from 0.5 μm to 200 μm. For example, 1 μm, 5 μm, 10 μm, 50 μm, 100 μm, 130 μm, 150 μm, 170 μm, 190 μm, etc.

[0147] In some implementations, the width of the second sub-region E22 ranges from 0.5 μm to 200 μm. For example, 1 μm, 5 μm, 10 μm, 50 μm, 100 μm, 130 μm, 150 μm, 170 μm, 190 μm, etc.

[0148] In some embodiments, the portion of the second doped silicon-containing layer 32 opposite to the third region E3 forms a height difference that is higher than the portion of the second doped silicon-containing layer 32 opposite to the second region E2. The height difference ranges from 0.5 μm to 8 μm. For example, the height difference is 0.7 μm, 1 μm, 3 μm, 5 μm, 7 μm, etc.

[0149] In some embodiments, a stepped surface is formed between the portion of the second doped silicon-containing layer 32 opposite to the third region E3 and the portion of the second doped silicon-containing layer 32 opposite to the second region E2, and a portion of the conductive layer 50 is disposed on the stepped surface. The stepped surface is the side surface that is higher than the second region. In this way, it is not necessary to remove the conductive layer 50 on the stepped surface, reducing the process difficulty and improving the etching accuracy.

[0150] In some embodiments, the photovoltaic cell further includes a dielectric layer 23 stacked on the third region E3 and located between the first doped silicon-containing layer 21 and the intrinsic silicon-containing layer 31.

[0151] Retaining the dielectric layer 23 in the third region E3 can increase the internal light reflectivity of the battery, which is beneficial to improving the utilization rate of sunlight.

[0152] In some embodiments, the substrate 10 is either a p-type substrate 10 or an n-type substrate 10.

[0153] In some embodiments, one of the first doped silicon-containing layer 21 and the second doped silicon-containing layer 32 is a p-type doped silicon-containing layer and the other is an n-type doped silicon-containing layer.

[0154] In some embodiments, the substrate 10 has a second surface 12 opposite to the first surface 11, on which a passivation layer 41 and an antireflection layer 42 are stacked sequentially.

[0155] In some embodiments, the second region E2 and the second surface 12 of the substrate 10 are respectively formed with a textured structure.

[0156] In some embodiments, the tunneling oxide layer 22 is made of silicon oxide and has a thickness of 0.5 nm to 3 nm, such as 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm or 3 nm.

[0157] In some embodiments, the first doped silicon layer 21 is made of n-type doped polycrystalline silicon and has a thickness of 30nm to 300nm, such as 30nm, 100nm, 150nm, 200nm, 250nm or 300nm.

[0158] In some embodiments, the dielectric layer 23 is made of at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0159] In some embodiments, the intrinsic silicon-containing layer 31 is made of at least one of microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, or silicon carbide.

[0160] In some embodiments, the material of the second doped silicon-containing layer 32 is at least one of p-type doped microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide, or silicon carbide.

[0161] In some embodiments, the conductive layer 50 is made of at least one of transparent conductive metal oxide or transparent conductive metal nitride.

[0162] The technological advantages of the aforementioned photovoltaic cells compared to existing technologies are the same as the advantages of the aforementioned photovoltaic cell preparation methods, and will not be repeated here.

[0163] Those skilled in the art should understand that the above embodiments are merely for clearly illustrating the present invention and are not intended to limit the scope of the present invention. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present invention.

Claims

1. A photovoltaic cell, characterized in that, The substrate includes a substrate having a first surface, the first surface including a first region, a second region and a third region located between the first region and the second region; The first region has a tunneling oxide layer, a first doped silicon-containing layer, and a conductive layer stacked sequentially thereon; the second region has an intrinsic silicon-containing layer, a second doped silicon-containing layer, and the conductive layer stacked sequentially thereon; the third region has the tunneling oxide layer, the first doped silicon-containing layer, the intrinsic silicon-containing layer, the second doped silicon-containing layer, and the conductive layer stacked sequentially thereon, wherein the doping types of the first doped silicon-containing layer and the second doped silicon-containing layer are opposite. The conductive layer has a first discontinuity structure in a first sub-region and a second discontinuity structure in a second sub-region, wherein the first sub-region includes at least one of the portion of the first region adjacent to the third region and at least a portion of the third region; the second sub-region is the portion of the second region adjacent to the third region.

2. The photovoltaic cell according to claim 1, characterized in that, The width of the first sub-region ranges from 0.5 μm to 200 μm; and / or, The width of the second sub-region ranges from 0.5μm to 200μm.

3. The photovoltaic cell according to claim 1, characterized in that, The portion of the second doped silicon-containing layer opposite to the third region has a height difference that is higher than the portion of the second doped silicon-containing layer opposite to the second region, and the height difference ranges from 0.5 μm to 8 μm.

4. The photovoltaic cell according to claim 3, characterized in that, A stepped surface is formed between the portion of the second doped silicon-containing layer opposite to the third region and the portion of the second doped silicon-containing layer opposite to the second region, and a portion of the conductive layer is disposed on the stepped surface.

5. The photovoltaic cell according to claim 1, characterized in that, The photovoltaic cell further includes a dielectric layer, which is stacked on the third region and located between the first doped silicon-containing layer and the intrinsic silicon-containing layer.

6. The photovoltaic cell according to claim 1, characterized in that, The substrate is either a p-type substrate or an n-type substrate.

7. The photovoltaic cell according to claim 1, characterized in that, One of the first doped silicon-containing layer and the second doped silicon-containing layer is a p-type doped silicon-containing layer, and the other is an n-type doped silicon-containing layer.

8. The photovoltaic cell according to claim 1, characterized in that, The substrate has a second surface opposite to the first surface, on which a passivation layer and an antireflection layer are stacked sequentially.

9. The photovoltaic cell according to claim 8, characterized in that, The second region and the second surface of the substrate are respectively formed with a textured surface.

10. The photovoltaic cell according to claim 5, characterized in that, The tunneling oxide layer is made of silicon oxide and has a thickness of 0.5 nm to 3 nm; and / or, The first doped silicon-containing layer is made of n-type doped polycrystalline silicon with a thickness of 30 nm to 300 nm; and / or, The dielectric layer is made of one of silicon oxide, silicon nitride, and silicon oxynitride; and / or, The intrinsic silicon-containing layer is made of one of the following materials: microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide, or silicon carbide; and / or, The second doped silicon-containing layer is made of one of the following: p-type doped microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, or silicon carbide; and / or, The conductive layer is made of either a transparent conductive metal oxide or a transparent conductive metal nitride.

Images