Wafer test bench assembly and wafer test device
By setting an insulating cover in the wafer edge area and controlling the probe contact method, the path risk when the probe moves to the wafer edge is solved, thus achieving the effectiveness and accuracy of wafer inspection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- KAIHUI SEMICONDUCTOR EQUIPMENT (SHENZHEN) CO LTD
- Filing Date
- 2025-01-14
- Publication Date
- 2026-04-17
AI Technical Summary
When inspecting diodes on a wafer, there is a risk that the probe may form an unexpected path with the stage when it moves to the edge of the wafer, which may affect the accuracy of the inspection results.
An insulating cover is used to cover the edge area of the wafer, and the contact between the probe and the edge area of the wafer is controlled by a control module to ensure that the probe only contacts the insulating cover and avoids the formation of unnecessary current paths.
This effectively avoids accidental pathways between the probe and the stage, ensuring the effectiveness and accuracy of wafer inspection.
Smart Images
Figure CN224137325U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor device equipment technology, and more specifically, relates to a wafer test bench assembly and a wafer test device. Background Technology
[0002] After diode chips are formed on the wafer but before they are cut and shaped, electrical testing is required for each diode chip on the wafer before packaging. Specifically, electrical testing typically involves applying high voltage to the chip and using a voltage-current measurement method to detect the current flowing through the chip, thereby determining whether the chip's resistance is within the target range. This process tests the electrical performance of each diode chip and filters out defective chips from the wafer.
[0003] In related technologies, the aforementioned pressure-based current measurement method generally involves placing the die on a platform connected to the negative terminal of a power supply, and having a probe connected to the positive terminal contact the die surface. The current in the die is then detected at the instant the probe contacts the die.
[0004] However, due to the large number of diode chips on the wafer and the array of probes on the probe disk, after a probe finishes detecting a chip located at the edge of the wafer, the probe disk needs to be moved so that the probe can cover all the chips. When some probes move from above the chips to above the area on the wafer where the chips are formed (i.e., the edge area) and come into contact with the edge area, the charge carried by the probes may cause the reed relay to close. In other words, there is a risk of an accidental circuit being formed between the probes corresponding to the edge area and the stage, which ultimately affects the detection results. Summary of the Invention
[0005] The purpose of this application is to provide a wafer test bench assembly and a wafer test apparatus to solve the technical problem that diode chips are easily affected when subjected to voltage and current testing in the prior art.
[0006] To achieve the above objectives, the technical solution adopted in the first aspect of this application is to provide a wafer test station assembly, which includes:
[0007] A test stage, the upper surface of which is used to support a wafer to be tested, the test stage being made of a conductive material; an annular cover, which can be transferred and placed on the test stage or the wafer to cover the annular edge of the wafer and is insulated from the test stage.
[0008] Optionally, the upper surface of the test stage is formed with a support area for supporting the wafer and a non-support area surrounding the support area; the cover is placed in the non-support area and at least partially covers the edge area of the support area, and the portion of the cover that contacts the non-support area is insulated.
[0009] Optionally, the annular inner contour of the cover covering the edge region can be adapted to the edge contour of the grain region on the wafer.
[0010] Optionally, the cover includes a first plate and a second plate stacked sequentially from bottom to top in the height direction; the first plate is disposed around the bearing area, the second plate is capable of covering the edge area of the bearing area, and the annular inner contour of the second plate is adaptable to the edge contour of the grain area on the wafer.
[0011] Optionally, the first plate is insulated; and / or, the thickness of the first plate is greater than or equal to the thickness of the wafer.
[0012] Optionally, the first plate and the second plate are glued together.
[0013] Optionally, a negative pressure airway is formed in the test stage, and air holes communicating with the negative pressure airway are provided on the surface of the non-load-bearing area.
[0014] Optionally, the second plate is made of metal and has magnetic elements on the surface of the non-load-bearing area.
[0015] In a second aspect of this application, a wafer testing apparatus is provided, comprising a transfer component, a detection component, and the aforementioned wafer testing stage assembly; wherein, the transfer component is used to transfer a cover and place it on a non-load-bearing area of a testing stage; the detection component is used to perform pressure current measurement tests on each die in the die region of the wafer, and includes a tester, a power supply, a control module connected to the power supply and the tester, and a plurality of arrayed and parallel probes, wherein the probes and the testing stage are both electrically connected to the control module, and the probes and the testing stage are respectively connected to the positive and negative terminals of the power supply.
[0016] Optionally, it also includes a vision component electrically connected to the transfer component. The vision component is used to acquire the position coordinates of the cover on the test stage to correct the position error between the inner annular edge of the cover and the edge contour of the die region on the wafer, so that the transfer component adjusts the position coordinates of the cover on the test stage according to the position error.
[0017] The wafer testing station assembly and wafer testing apparatus provided in this application have at least the following beneficial effects:
[0018] During testing, a matching cover is used on the test stage to cover the edge area of the wafer, thus achieving mutual insulation between the edge area of the wafer and the test stage. In this way, when some probes move to the edge area of the wafer, the probes only contact the surface of the cover. At this time, even if the probes corresponding to the edge area of the wafer are still carrying charge, it can prevent the probes from accidentally forming a path with the test stage, thereby ensuring the effectiveness and accuracy of the testing of the die area on the wafer. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0020] Figure 1 This is a perspective view of a wafer test station assembly in some embodiments of this application;
[0021] Figure 2 This is a top view of the cover in some embodiments of this application;
[0022] Figure 3 This is a perspective view of the cover in some embodiments of this application;
[0023] Figure 4 This is a perspective view of a wafer testing apparatus in some embodiments of this application;
[0024] Figure 5 This is a schematic diagram of a chip in some embodiments of this application;
[0025] Figures 6 to 9 This is a cross-sectional view of the cover in different embodiments of this application. Detailed Implementation
[0026] To make the technical problems, technical solutions and beneficial effects to be solved by this application clearer, the following describes this application in further detail with reference to the accompanying drawings and embodiments.
[0027] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.
[0028] It should be noted that when a component is referred to as "fixed to" or "set on" another component, it can be directly on the other component or indirectly on that other component.
[0029] When a component is said to be "connected to" another component, it can be directly connected to the other component or indirectly connected to that other component.
[0030] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0031] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature.
[0032] In the description of this application, "multiple" means two or more, unless otherwise expressly and specifically defined.
[0033] Please refer to the following: Figures 1 to 9 The wafer test bench assembly and wafer test apparatus provided in the embodiments of this application will now be described.
[0034] Understandably, the test bench components are assembled within the test apparatus.
[0035] Understandably, reference Figure 5 Each die 621 in the die region 620 on the wafer 600 is a diode die 621, which has unidirectional conductivity; while the edge region 610 on the wafer 600 (that is, the blank area on the wafer 600 where no die 621 is formed) is a conductor.
[0036] Among them, reference Figures 1 to 3 , Figures 6 to 9 In a first aspect embodiment, the test stage assembly includes a test stage 100 and an annular cover 200. The test stage 100 is used to hold a wafer 600 to be tested and is made of a conductive material, such as a conductive metal material like copper. The cover 200 can be transferred and placed on the test stage 100 and can cover the edge region 610 of the wafer 600. Furthermore, the portion of the cover 200 covering the edge region 610 of the wafer 600 is insulated from the test stage 100.
[0037] Understandably, reference Figure 6 The cover 200 may simply be used to cover the edge region 610 of the wafer 600. In this embodiment, the cover 200 is made of PEEK material (i.e., polyetheretherketone); or, refer to Figures 7 to 9It can also be capable of simultaneously covering the edge area 610 of the test stage 100 and the chip 600.
[0038] refer to Figure 4 In the second aspect embodiment, the testing apparatus, in addition to being equipped with the aforementioned test stage assembly, also includes at least a transfer assembly 300 and a detection assembly 400. The transfer assembly 300 is used to transfer and place the cover 200 onto the test stage 100. Thus, on the one hand, the cover 200 can limit and fix the wafer 600 to the test stage 100; on the other hand, the cover 200 can insulate the edge region 610 of the wafer 600 from the test stage 100. The detection assembly 400 is used to apply pressure and measure current on the wafer 600 on the test stage 100.
[0039] Specifically, the detection assembly 400 includes a tester, a test power supply, a control module, and a probe disk, on which a plurality of probes 410 are arrayed. In specific applications, the tester is electrically connected to the test power supply, the control module, and the probe disk, and is used to detect the current magnitude on the probes 410; the test stage 100 is connected to the negative terminal of the test power supply, and each probe 410 is arranged in parallel and connected to the positive terminal of the power supply. Furthermore, a reed relay is connected between each probe 410 and the positive terminal of the test power supply. Further, the detection assembly 400 may also include a drive module, which is used to drive the probe disk to move so that the coverage area of the probe disk can completely cover the die region 620 on the wafer 600.
[0040] Throughout the electrical testing process of the wafer 600, the test stage 100 is always connected to the negative terminal of the test power supply. When the coverage area of the probe disk is completely located in the die region 620 on the wafer 600, the control module controls each probe 410 to connect to the positive terminal of the test power supply. At this time, each reed relay is in the closed state. When the probe disk moves to the edge region 610 on the wafer 600 where part of the coverage area is located, the control module controls each probe 410 located in the die region 620 to connect to the positive terminal of the test power supply, while each probe 410 located in the edge region 610 is not connected to the positive terminal of the test power supply. That is, the reed relay connected to the probe 410 located in the edge region 610 is in the open state.
[0041] During the electrical performance testing of wafer 600, each probe 410 moves up and down synchronously with the probe disk to approach or move away from the surface of wafer 600.
[0042] When the probe disk covers part or all of the die region 620 on the wafer 600, after the probe 410 contacts the surface of each die 621 on the wafer 600, the control module controls the reed relay to be closed so that the probe 410 located directly above the die region 620 is connected to the positive terminal of the test power supply. Since the test stage 100 is connected to the negative terminal of the test power supply, after the reed relay is closed, a circuit is formed between the probe 410, the die 621 and the test stage 100. At this time, the die 621 under test generates current, and the tester can obtain the electrical performance of the die 621 under test by detecting the current on each probe 410.
[0043] If the probe disk covers part of the edge region 610 on the wafer 600, since the edge region 610 of the wafer 600 is covered by the cover 200, after the probe 410 contacts the surface of the cover 200, the control module controls the reed relay to be in the open state so that the probe 410 located directly above the die region 620 is disconnected from the positive terminal of the test power supply. At this time, even if the test stage 100 is connected to the negative terminal of the test power supply, since the cover 200 covering the edge region 610 of the wafer 600 has the property of being insulated from the test stage 100, even if the probe 410 above the edge region 610 still carries a charge, the reed relay corresponding to the probe 410 above the edge region 610 will not be accidentally closed due to the charge of the probe 410, thus forming a circuit. Therefore, the effective detection area of the probe disk on the wafer 600 is limited to the die region 620 on the wafer 600, effectively ensuring the effectiveness and accuracy of the wafer 600 detection.
[0044] The following details the chip 600 test assembly according to the first aspect embodiment.
[0045] refer to Figure 1 In some embodiments, the upper surface of the test stage 100 is formed with a carrier region 110 for carrying the wafer 600 and a non-carrier region 120 surrounding the carrier region 110; a cover 200 is placed in the non-carrier region 120 and at least partially covers the edge region 610 of the carrier region 110, and the portion of the cover 200 in contact with the non-carrier region 120 is insulated.
[0046] refer to Figures 1 to 3 , Figures 6 to 9 Furthermore, the annular inner contour 200a of the cover edge region 610 on the cover 200 can be adapted to the edge contour of the die region 620 on the wafer 600. That is, the annular inner contour 200a on the cover 200 is serrated so that the contour of the cover 200 can accurately cover the edge contour of the die region 620 on the wafer 600, so as to avoid the probe 410 from contacting the edge region 610 on the wafer 600.
[0047] Specifically, the cover 200 may have at least the following implementations.
[0048] refer to Figure 8 In the first embodiment, the cover 200 is integrally formed from an insulating material, such as PEEK (polyether ether ketone), and the inner contour of the cross section on its annular side is stepped. The stepped annular inner contour 200a is used to abut against the peripheral wall of the wafer 600 so that the cover 200 and the wafer 600 are mutually constrained and fixed.
[0049] refer to Figure 9 In the second embodiment, the cover member 200 includes a first plate 210 and a second plate 220. In this embodiment, the first plate 210 and the second plate 220 are fixedly connected in the radial direction, and both the first plate 210 and the second plate 220 are annular. The second plate 220 covers the edge region 610 on the wafer 600, the first plate 210 is sleeved on the outside of the second plate 220, and the second plate 220 is made of an insulating material (e.g., PEEK). The thickness of the first plate 210 is greater than the sum of the thicknesses of the second plate 220 and the wafer 600.
[0050] refer to Figure 7 In the third embodiment, the cover member 200 also includes a first plate 210 and a second plate 220. The first plate 210 and the second plate 220 are stacked sequentially from bottom to top in the height direction. The first plate 210 surrounds the support region 110, and the second plate 220 can cover the edge region 610 of the support region 110. That is, the area of the second plate 220 is larger than the area of the first plate 210, and the annular inner contour 200a of the second plate 220 can be adapted to the edge contour of the die region 620 on the wafer 600. In this embodiment, the first plate 210 is made of an insulating material (e.g., PEEK material) and its thickness is adapted to the thickness of the wafer 600. The second plate 220 can be made of an insulating material or a conductive material, and is not limited thereto.
[0051] It is understood that in the second and third embodiments described above, the first plate 210 and the second plate 220 can be connected by adhesive bonding.
[0052] refer to Figure 1Based on the above embodiments, the test stage 100 can be configured as follows. Specifically, a negative pressure air channel 140 is formed in the test stage 100, which is connected to an external negative pressure air source. Air holes 130 communicating with the negative pressure air channel 140 are provided on the surface of the non-load-bearing area 120. By providing the negative pressure air channel 140, the cover 200 on the surface of the non-load-bearing area 120 can be firmly held in place to prevent displacement during the wafer 600 inspection process.
[0053] In other embodiments, the test stage 100 may also be configured as follows. Specifically, in the second embodiment of the cover 200, if the first plate 210 is made of metal, a magnetic attraction element may be provided on the surface of the non-load-bearing area 120; or, in the third embodiment of the cover 200, if the second plate 220 is made of metal, a magnetic attraction element may also be provided on the surface of the non-load-bearing area 120. This arrangement of the magnetic attraction element ensures that the cover 200 can be firmly attached to the surface of the test stage, thus preventing displacement during the wafer 600 inspection process.
[0054] refer to Figure 4 In the wafer testing apparatus of the second aspect embodiment, the testing apparatus further includes a vision component 500 electrically connected to the transfer component 300. In specific applications, the vision component 500 can be a CCD camera. The vision component 500 is mounted directly above the test stage 100 so as to acquire images directly facing the test stage 100.
[0055] Specifically, in the electrical performance testing process of the wafer 600, after the wafer 600 is transferred and placed on the test stage 100, its position is generally fixed. After the cover 200 is transferred to the test stage 100 and covers the edge area 610 of the wafer 600, the vision component 500 performs image acquisition facing the test stage 100 to obtain the position coordinates of the cover 200 on the test stage 100. Based on the position coordinates of the wafer 600 on the test stage 100, the cover 200 is calibrated. The positional error (e.g., lateral, longitudinal, or angular error) between the inner annular edge of the cover 200 and the edge contour of the die region 620 on the wafer 600 is used to adjust the position coordinates of the cover 200 on the test stage 100 according to the positional error between the cover 200 and the wafer 600. This ensures that the inner annular contour 200a of the cover 200 can be precisely matched with the contour of the die region 620 on the wafer 600, so that each die 621 can be tested by the probe 410 during electrical testing.
[0056] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A wafer test station assembly, comprising: include: A test stage, the upper surface of which is used to support the wafer to be tested, the test stage being made of a conductive material; The ring-shaped cover can be transported and placed on the test stage or the wafer to cover the ring edge of the wafer and can be insulated from the test stage.
2. The wafer test station assembly of claim 1, wherein: The upper surface of the test stage has a support area for supporting the wafer and a non-support area surrounding the support area; the cover is placed in the non-support area and at least partially covers the edge area of the support area, and the portion of the cover that contacts the non-support area is insulated.
3. The wafer test station assembly of claim 2, wherein: The annular inner contour of the cover covering the edge region can be adapted to the edge contour of the grain region on the wafer.
4. The wafer test station assembly of claim 3, wherein: The cover includes a first plate and a second plate stacked sequentially from bottom to top in the height direction; the first plate is disposed around the bearing area, the second plate is capable of covering the edge area of the bearing area, and the annular inner contour of the second plate is adaptable to the edge contour of the grain area on the wafer.
5. The wafer test station assembly of claim 4, wherein: The first plate is insulated; and / or, the thickness of the first plate is greater than or equal to the thickness of the wafer.
6. The wafer test station assembly of claim 4, wherein: The first plate and the second plate are glued together.
7. The wafer test station assembly of any of claims 2 to 6, wherein: A negative pressure airway is formed in the test stage, and air holes communicating with the negative pressure airway are provided on the surface of the non-load-bearing area.
8. The wafer test station assembly of any of claims 4 to 6, wherein: The second plate is made of metal and has magnetic elements on its surface in the non-load-bearing area.
9. A wafer testing apparatus, characterized by comprising: It includes at least a transfer component, a detection component, and a wafer test station component as described in any one of claims 3 to 8; The transfer component is used to transfer the cover and place it on the non-load-bearing area of the test platform; The detection component is used to perform pressure current measurement tests on each die in the die region on the wafer. It includes a tester, a power supply, a control module connected to the power supply and the tester, and a plurality of arrays of probes arranged in parallel. The probes and the test stage are both electrically connected to the control module, and the probes and the test stage are respectively connected to the positive and negative terminals of the power supply.
10. The wafer testing apparatus of claim 9, wherein: It also includes a vision component electrically connected to the transfer component, the vision component being used to acquire the position coordinates of the cover on the test stage to correct the position error between the inner annular edge of the cover and the edge contour of the grain region on the wafer, so that the transfer component adjusts the position coordinates of the cover on the test stage according to the position error.