Display panel and display device

Abstract

The utility model provides a display panel and a display device, and the display panel comprises a substrate, a gate layer, a first insulating layer, a source and drain electrode layer, a common electrode layer, a second insulating layer and a pixel electrode layer. The substrate is provided with a first face and a second face which are oppositely arranged. The gate layer is disposed on the first surface. The first insulating layer is arranged on the side, away from the substrate, of the gate layer. The source-drain layer is arranged on the side, away from the gate layer, of the first insulating layer. The common electrode layer is arranged on the side, away from the gate layer, of the first insulating layer and located on the side face of the source-drain layer. The second insulating layer is arranged on the side, away from the first insulating layer, of the source-drain electrode layer and the common electrode layer. The pixel electrode layer is arranged on the side, away from the first insulating layer, of the second insulating layer. Wherein the second insulating layer is provided with a first via hole and a second via hole, the pixel electrode layer is connected with the source and drain electrode layer through the first via hole, and the pixel electrode layer is connected with the common electrode layer through the second via hole. The display panel can improve the product stability and the display quality.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] A display screen is a component in electronic devices used to display images and text, typically consisting of three main parts: a display unit, a glass substrate, and driving circuitry. Display screens are widely used in televisions, computer monitors, mobile phones, tablets, e-readers, automotive displays, and other fields. They are crucial infrastructure for daily life and the modern electronic information industry. With technological advancements, display screens are also being applied to emerging fields such as wearable devices, smart homes, and medical devices, driving the development of related industries.

[0003] Current display screens have increasingly higher voltage requirements. Under normal display and reliability conditions, the circuits are prone to short circuits or open circuits, which affects the display quality.

[0004] Therefore, providing a display panel and display device that can prevent short circuits or open circuits has become a technical problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0005] This utility model provides a display panel and display device, which helps to prevent short circuits or open circuits in the circuit and improves the stability and display quality of the display panel.

[0006] In a first aspect, this utility model provides a display panel, comprising:

[0007] The substrate has a first surface and a second surface disposed opposite to each other;

[0008] A gate layer is disposed on the first surface;

[0009] A first insulating layer is disposed on the side of the gate layer away from the substrate;

[0010] The source and drain layers are disposed on the side of the first insulating layer away from the gate layer;

[0011] A common electrode layer is disposed on the side of the first insulating layer away from the gate layer and located on the side of the source and drain layers;

[0012] The second insulating layer is disposed on the side of the source / drain layer and the common electrode layer away from the first insulating layer;

[0013] A pixel electrode layer is disposed on the side of the second insulating layer away from the first insulating layer;

[0014] The second insulating layer is provided with a first via and a second via. The pixel electrode layer is connected to the source and drain electrode layers through the first via, and the pixel electrode layer is connected to the common electrode layer through the second via.

[0015] In some embodiments, the source-drain layer includes a source and a drain, and a semiconductor driving layer is disposed between the source and the drain.

[0016] In some embodiments, the common electrode layer is disposed near the drain, and the pixel electrode layer is connected to the drain through the second via.

[0017] In some embodiments, the common electrode layer is disposed near the source electrode, and the pixel electrode layer is connected to the source electrode through the second via.

[0018] In some embodiments, the common electrode layer is disposed on both sides of the source and drain, and the pixel electrode layer is connected to the source and drain respectively through the second via.

[0019] In some embodiments, a reference voltage layer is disposed between the first insulating layer and the substrate.

[0020] In some embodiments, a sub-common electrode layer is further included, which is on the same layer as the common electrode layer. The first insulating layer is provided with a third via, and the sub-common electrode layer is connected to the reference voltage through the third via.

[0021] In some embodiments, there is a gap between the sub-common electrode layer and the common electrode layer.

[0022] In some embodiments, the second insulating layer is a silicon nitride layer.

[0023] Secondly, this utility model provides a display device, including the display panel described above.

[0024] This utility model provides a display panel comprising a substrate, a gate layer, a first insulating layer, a source / drain layer, a common electrode layer, a second insulating layer, and a pixel electrode layer. The substrate has a first surface and a second surface disposed opposite to each other. The gate layer is disposed on the first surface. The first insulating layer is disposed on the side of the gate layer away from the substrate. The source / drain layer is disposed on the side of the first insulating layer away from the gate layer. The common electrode layer is disposed on the side of the first insulating layer away from the gate layer and located on the side of the source / drain layer. The second insulating layer is disposed on the side of the source / drain layer and the common electrode layer away from the first insulating layer. The pixel electrode layer is disposed on the side of the second insulating layer away from the first insulating layer. The second insulating layer has a first via and a second via. The pixel electrode layer is connected to the source / drain layer through the first via and to the common electrode layer through the second via. This application's display panel increases the via overlap area of ​​the pixel electrodes in the pixel region, reduces capacitance resistance, and improves display stability without affecting the transmittance of the display area. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the first structure of the display panel provided by this utility model;

[0026] Figure 2 This is a schematic diagram of a second structure of the display panel provided by this utility model;

[0027] Figure 3 A schematic diagram of a third structure of the display panel provided by this utility model;

[0028] Figure 4 This is a schematic diagram of a display device provided by this utility model. Detailed Implementation

[0029] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0030] Furthermore, the terms "first," "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order. The terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0031] Please see Figures 1 to 3This application discloses a display panel 100, including a substrate 10, a gate layer 20, a first insulating layer 30, a source / drain layer 40, a common electrode layer 50, a second insulating layer 60, and a pixel electrode layer 70. The substrate 10 has a first surface and a second surface disposed opposite to each other. The gate layer 20 is disposed on the first surface. The first insulating layer 30 is disposed on the side of the gate layer 20 away from the substrate 10. The source / drain layer 40 is disposed on the side of the first insulating layer 30 away from the gate layer 20. The common electrode layer 50 is disposed on the side of the first insulating layer 30 away from the gate layer 20 and is located on the side of the source / drain layer 40. The second insulating layer 60 is disposed on the side of the source / drain layer 40 and the common electrode layer 50 away from the first insulating layer 30. The pixel electrode layer 70 is disposed on the side of the second insulating layer 60 away from the first insulating layer 30. The second insulating layer 60 is provided with a first via 101 and a second via 102. The pixel electrode layer 70 is connected to the source and drain layer 40 through the first via 101 and to the common electrode layer 50 through the second via 102.

[0032] It should be noted that the first surface 10a of the substrate 10 is the upper surface, and the second surface 10b of the substrate 10 is the lower surface. Of course, the positions of the first surface 10a and the second surface 10b can be interchanged as needed. Unless otherwise specified in the embodiments of this application, the first surface 10a is assumed to be the upper surface.

[0033] The substrate 10 can be a glass substrate or a flexible substrate, with a thickness between 0.1 mm and 1 mm. The gate layer 20 can be made of a metallic material, such as aluminum, molybdenum, or copper, with a thickness of 50 nm to 500 nm. The first insulating layer 30 can be made of silicon oxide or silicon nitride, with a thickness of 100 nm to 1000 nm. The source-drain layer 40 can include a source 41 and a drain, made of a metallic material, such as aluminum, molybdenum, or copper, with a thickness of 100 nm to 1000 nm. The common electrode layer 50 can be made of a transparent conductive material, such as indium tin oxide or zinc oxide, with a thickness of 50 nm to 500 nm. The second insulating layer 60 can be made of silicon nitride, with a thickness of 100 nm to 1000 nm. The pixel electrode layer 70 can be made of a transparent conductive material, such as indium tin oxide or zinc oxide, with a thickness of 50 nm to 500 nm. The diameters of the first via 101 and the second via 102 can be between 1 μm and 10 μm.

[0034] This technical solution sets the common electrode layer 50 and the source / drain layer 40 on the same layer, and connects the pixel electrode layer 70 and the common electrode layer 50 through vias in the second insulating layer 60. This increases the via overlap area of ​​the pixel electrodes in the pixel area without affecting the transmittance of the display area, reduces capacitance resistance, and improves display stability. It also reduces line impedance. Furthermore, the co-layering of the common electrode layer 50 and the source / drain layer 40 optimizes the panel structure and reduces the risk of interlayer short circuits. The first via 101 and the second via 102 ensure a reliable connection between the pixel electrode layer 70, the source / drain layer 40, and the common electrode layer 50, improving the stability and reliability of the display panel 100. Compared with existing technologies, this solution simplifies the panel structure, effectively reduces the likelihood of short circuits or open circuits in the display panel 100, and improves the stability and reliability of signal transmission.

[0035] Furthermore, this application also proposes that the source-drain layer 40 includes a source 41 and a drain 42, and a semiconductor driving layer 80 is disposed between the source 41 and the drain 42.

[0036] Specifically, the semiconductor driving layer 80 can be made of amorphous silicon, low-temperature polycrystalline silicon, or oxide semiconductor materials. Among these, indium gallium zinc oxide (IGaZN) is preferred. The thickness of the semiconductor driving layer 80 ranges from 30 to 100 nanometers. As a preferred embodiment, the semiconductor driving layer 80 is formed by chemical vapor deposition. Furthermore, the semiconductor driving layer 80 can have a channel structure, with a channel length preferably of 3-10 micrometers. Thus, the semiconductor driving layer 80 can effectively control the current conduction between the source 41 and the drain 42.

[0037] This technical solution, by placing a semiconductor driving layer 80 between the source 41 and drain 42, can precisely control the switching state of pixel units in the display panel 100. The semiconductor driving layer 80, as an active layer, forms a conductive channel under gate voltage control, thereby regulating the current between the source and drain. This structure avoids short circuits or open circuits caused by voltage fluctuations, improving the operational stability of the display panel 100. Furthermore, by optimizing the material and structural parameters of the semiconductor driving layer 80, the response speed and energy efficiency of the display panel 100 can be further improved.

[0038] Furthermore, this application also proposes that the display panel 100 includes a substrate 10, a gate layer 20, a first insulating layer 30, a source-drain layer 40, a common electrode layer 50, a second insulating layer 60, and a pixel electrode layer 70. The source-drain layer 40 includes a source electrode 41 and a drain electrode, and a semiconductor driving layer 80 is disposed between the source electrode 41 and the drain electrode. The common electrode layer 50 is disposed near the drain electrode, and the pixel electrode layer 70 is connected to the drain electrode through a second via 102.

[0039] The specific implementation methods for placing the common electrode layer 50 close to the drain include, but are not limited to: direct contact between the common electrode layer 50 and the drain through a conductive material; connection between the common electrode layer 50 and the drain through a metal bridging structure; and forming an ohmic contact between the common electrode layer 50 and the drain through a doped semiconductor material. The second via 102 can be filled with a conductive material such as copper, aluminum, or ITO to achieve electrical connection.

[0040] This technical solution places the common electrode layer 50 near the drain, allowing the pixel electrode layer 70 to be directly connected to the drain via the second via 102. This connection method reduces the signal transmission path length and lowers the line impedance, effectively avoiding signal attenuation and voltage drop problems caused by excessively long lines. Simultaneously, this structure simplifies the manufacturing process and improves the reliability of the panel. Specifically, the shortened distance between the common electrode and the drain reduces parasitic capacitance effects, improving the response speed of the display panel 100.

[0041] Furthermore, this application also proposes that the common electrode layer 50 is disposed on the side close to the source electrode 41, and the pixel electrode layer 70 is connected to the source electrode 41 through the second via 102.

[0042] Specifically, the common electrode layer 50 is arranged adjacent to the source electrode 41, and the two are isolated by a second insulating layer 60. A second via 102 penetrates the second insulating layer 60, enabling the pixel electrode layer 70 to form an electrical connection with the source electrode 41. In a preferred embodiment, the common electrode layer 50 may partially cover the upper surface of the source electrode 41, and the second via 102 may be formed in the overlapping area by an etching process. Alternatively, the common electrode layer 50 may be arranged parallel to the source electrode 41, and the connection may be achieved through a laterally extending conductive structure. During manufacturing, photolithography and etching processes can be used to precisely control the position and size of the second via 102 to ensure reliable connection.

[0043] Therefore, this technical solution optimizes the charge transport path by placing the common electrode layer 50 on the source electrode 41 side and establishing a direct connection between the pixel electrode and the source electrode 41. Specifically, when the common electrode layer 50 is adjacent to the source electrode 41, the signal transmission distance is shortened, which helps to reduce line impedance. At the same time, this layout can reduce interference during signal transmission and improve display stability. Compared with the prior art, this solution effectively improves signal transmission quality while maintaining structural simplicity, providing a feasible technical means to solve the problem of short circuits or open circuits in the display panel 100.

[0044] Furthermore, this application also proposes that the common electrode layer 50 is disposed on both sides of the source electrode 41 and the drain electrode, and the pixel electrode layer 70 is connected to the source electrode 41 and the drain electrode respectively through the second via 102.

[0045] Specifically, the common electrode layer 50 can be disposed on both sides of the source electrode 41 and the drain electrode, forming a symmetrical distribution structure. In a preferred embodiment, the common electrode layer 50 may include two independent parts, located on the sides of the source electrode 41 and the drain electrode, respectively. The pixel electrode layer 70 is connected to the source electrode 41 and the drain electrode through second vias 102, wherein two second vias 102 can be provided, corresponding to the positions of the source electrode 41 and the drain electrode, respectively. Thus, the pixel electrode layer 70 can simultaneously form an electrical connection with both the source electrode 41 and the drain electrode.

[0046] To address this, this technical solution places the common electrode layer 50 on both sides of the source electrode 41 and the drain electrode, allowing the pixel electrode layer 70 to connect to both the source electrode 41 and the drain electrode simultaneously. Specifically, when the display panel 100 is operating, the pixel electrode layer 70 forms electrical connections with the source electrode 41 and the drain electrode respectively through the second via 102, thereby balancing the potential difference between the source electrode 41 and the drain electrode and reducing the risk of short circuits or open circuits. Furthermore, since the common electrode layer 50 is placed on both sides of the source electrode 41 and the drain electrode, it can effectively disperse the current density and reduce the occurrence of local overheating. Compared with the prior art, this solution can improve the reliability of the display panel 100 and reduce display defects caused by short circuits or open circuits.

[0047] Furthermore, this application also proposes that a reference voltage layer 90 be disposed between the first insulating layer 30 and the substrate 10.

[0048] Specifically, the reference voltage layer 90 can be made of a metallic material, such as conductive materials like aluminum, copper, or molybdenum. This layer is formed on the first surface of the substrate 10 by sputtering or vapor deposition. In a preferred embodiment, the thickness of the reference voltage layer 90 ranges from 100 to 500 nanometers. A buffer layer, made of silicon oxide or silicon nitride, can be selectively disposed between the reference voltage layer 90 and the substrate 10. The reference voltage layer 90 can be connected to an external driving circuit to obtain a stable reference voltage signal.

[0049] Furthermore, this application also proposes to provide a sub-common electrode layer 51 in the display panel 100, wherein the sub-common electrode layer 51 is on the same layer as the common electrode layer, and the first insulating layer 30 is provided with a third via 103, wherein the sub-common electrode layer 51 is connected to the reference voltage through the third via 103.

[0050] Specifically, the sub-common electrode layer 51 can be fabricated using the same conductive material as the common electrode layer, such as indium tin oxide or a metallic material. A certain distance can be maintained between the sub-common electrode layer 51 and the common electrode layer, forming a gap with a width ranging from 1 to 10 micrometers. The diameter of the third via 103 can be set to 2-20 micrometers and formed using photolithography. The reference voltage layer 90 can be disposed between the substrate 10 and the first insulating layer 30, fabricated using a metallic material, with a thickness of 50-500 nanometers. As a preferred embodiment, the sub-common electrode layer 51 can be designed as a strip structure, arranged parallel to one or both sides of the common electrode layer.

[0051] Furthermore, this application also proposes that there is a gap between the sub-common electrode layer 51 and the common electrode layer.

[0052] Specifically, the gaps can be set to an interval of 1-10 micrometers, which can be formed by photolithography. As a preferred embodiment, the gap width can be controlled within the range of 3-5 micrometers, achieved using a dry etching process. Furthermore, the gap shape can be a straight line, a wavy line, or a sawtooth pattern, with the sawtooth structure effectively increasing the surface area of ​​the electrode edges. During manufacturing, the size and shape of the gaps can be controlled by adjusting the mask pattern design.

[0053] Furthermore, this application also proposes that the second insulating layer 60 is a silicon nitride layer.

[0054] Silicon nitride (SiN) layers are inorganic insulating materials formed through chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes, exhibiting high dielectric strength, excellent thermal stability, and chemical inertness. In practice, the thickness of the SiN layer can be controlled within the range of 100-500 nanometers, and a dense, pinhole-free thin film structure can be obtained by adjusting the deposition parameters. Alternatively, the insulating layer can employ a composite stack structure of SiN and silicon oxide, where SiN acts as the main insulating layer and silicon oxide serves as a buffer layer to improve interfacial properties. In another embodiment, an appropriate amount of carbon can be incorporated into the SiN layer to form silicon carbide nitride, thereby adjusting the dielectric constant and stress characteristics.

[0055] This technical solution effectively solves the short-circuit problem caused by insulation layer defects in the display panel 100 by using silicon nitride as the second insulating layer 60. The high breakdown field strength of silicon nitride material can withstand the high voltage difference between the pixel electrode layer 70 and the underlying conductive layer, and its dense microstructure prevents the diffusion and migration of metal ions. Compared to conventional organic insulating materials, the silicon nitride layer maintains dimensional stability during high-temperature processing, avoiding cracking problems caused by thermal expansion coefficient mismatch. This insulating layer forms a good interface contact with the upper and lower electrode layers, ensuring the electrical connection reliability of the via structure, thereby improving the yield and lifespan of the display panel 100.

[0056] Please see Figure 4 , Figure 4 This is a schematic diagram of a display device provided by the present invention. The present invention provides a display device 1000, including a backlight substrate 200 and the aforementioned liquid crystal display panel 100.

[0057] The backlight substrate 200 is disposed on the back of the display panel and is used to provide the light source required for the display. The backlight substrate typically includes components such as a light source, a light guide plate, a reflective sheet, a diffuser sheet, and a brightness enhancement film, which can produce uniform and bright backlight to ensure that the display device has a good display effect.

[0058] The display device 1000 can be a television set, computer monitor, mobile phone, tablet computer, or other electronic device with display functions. By employing the display panel of the present invention, the display device can have higher display quality, faster response speed, and longer service life.

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized by, include: The substrate has a first surface and a second surface disposed opposite to each other; A gate layer is disposed on the first surface; A first insulating layer is disposed on the side of the gate layer away from the substrate; The source and drain layers are disposed on the side of the first insulating layer away from the gate layer; A common electrode layer is disposed on the side of the first insulating layer away from the gate layer and located on the side of the source and drain layers; The second insulating layer is disposed on the side of the source / drain layer and the common electrode layer away from the first insulating layer; A pixel electrode layer is disposed on the side of the second insulating layer away from the first insulating layer; The second insulating layer is provided with a first via and a second via. The pixel electrode layer is connected to the source and drain electrode layers through the first via, and the pixel electrode layer is connected to the common electrode layer through the second via.

2. The display panel of claim 1, wherein, The source-drain layer includes a source and a drain, and a semiconductor driving layer is disposed between the source and the drain.

3. The display panel of claim 2, wherein, The common electrode layer is disposed on the side close to the drain electrode, and the pixel electrode layer is connected to the drain electrode through the second via.

4. The display panel of claim 2, wherein, The common electrode layer is disposed on the side close to the source electrode, and the pixel electrode layer is connected to the source electrode through the second via.

5. The display panel of claim 2, wherein, The common electrode layer is disposed on both sides of the source and drain, and the pixel electrode layer is connected to the source and drain respectively through the second via.

6. The display panel of claim 1, wherein, A reference voltage layer is disposed between the first insulating layer and the substrate.

7. The display panel of claim 6, wherein, It also includes a sub-common electrode layer, which is on the same layer as the common electrode layer. The first insulating layer is provided with a third via, and the sub-common electrode layer is connected to the reference voltage through the third via.

8. The display panel of claim 7, wherein, There is a gap between the sub-common electrode layer and the common electrode layer.

9. The display panel of claim 1, wherein, The second insulating layer is a silicon nitride layer.

10. A display device, characterized by comprising: Includes the display panel as described in any one of claims 1 to 9.

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