Gradient-doped separated trench gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor)

Abstract

The utility model provides a gradient-doped separated trench gate silicon carbide VDMOS. The gradient-doped separated trench gate silicon carbide VDMOS comprises a drift layer connected to a silicon carbide substrate; the first N-type region is connected to the drift layer; the lower side surface of the second N-type region is connected to the upper side surface of the first N-type region; the lower side surface of the P-type well region is connected to the upper side surface of the second N-type region; an N-type source region is arranged in the P-type well region; the insulating medium layer sequentially penetrates through the N-type source region, the P-type well region, the second N-type region and the first N-type region, and the lower side surface of the insulating medium layer is connected to the upper side surface of the drift layer; a second gate metal layer and a groove are arranged in the insulating dielectric layer, and the second gate metal layer is located below the groove; the first gate metal layer is arranged in the groove; the source metal layer is respectively connected with the P-type well region and the N-type source region; the drain metal layer is connected to the lower side surface of the silicon carbide substrate; under the condition of not influencing the on resistance of the device, the voltage endurance capability of the device is improved, the gate-drain capacitance of the device is reduced, the switching speed of the device is improved, and the switching loss of the device is reduced.

Description

Technical Field

[0001] This invention relates to a gradient-doped discrete trench gate silicon carbide VDMOS. Background Technology

[0002] Silicon carbide VDMOS is a typical example of silicon carbide power devices, widely used in electric vehicles, aerospace, power conversion, and other fields. For silicon carbide power VDMOS, the performance requirements vary across different applications, but generally include lower on-resistance, faster switching speed, higher reliability (including gate reliability and drain voltage surge reliability), and lower body diode conduction loss. Utility Model Content

[0003] The technical problem to be solved by this utility model is to provide a gradient-doped discrete trench gate silicon carbide VDMOS, which improves the device's withstand voltage capability without affecting the device's on-resistance, reduces the device's gate-drain capacitance, improves the device's switching speed, and reduces the device's switching losses.

[0004] In a first aspect, this utility model provides a gradient-doped discrete trench gate silicon carbide VDMOS, comprising:

[0005] silicon carbide substrate;

[0006] A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate;

[0007] A first N-type region, the lower side of which is connected to the upper side of the drift layer;

[0008] The second N-type region has its lower side surface connected to the upper side surface of the first N-type region;

[0009] A P-type well region, the lower side of which is connected to the upper side of the second N-type region; an N-type source region is provided within the P-type well region;

[0010] An insulating dielectric layer is provided, which sequentially passes through the N-type source region, the P-type well region, the second N-type region, and the first N-type region. The lower side of the insulating dielectric layer is connected to the upper side of the drift layer. A second gate metal layer and a trench are provided in the insulating dielectric layer, and the second gate metal layer is located below the trench.

[0011] A first gate metal layer is disposed within the trench;

[0012] A source metal layer, wherein the source metal layer is connected to the P-type well region and the N-type source region respectively;

[0013] And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.

[0014] The advantages of this utility model are:

[0015] I. This utility model constructs a first gate metal layer and a second gate metal layer inside the device, which can effectively reduce the resistivity inside the device and reduce the on-resistance of the device.

[0016] Second, this utility model constructs a first N-type region and a second N-type region on the upper part of the drift layer to achieve gradient doping; this allows the voltage from the device drain to be distributed in the first N-type region and the second N-type region when the device is turned off, thereby improving the device's withstand voltage; and the doping concentration of the first N-type region and the second N-type region is higher than that of the drift layer, which can distribute the current to the edge of the device and avoid current concentration inside the device.

[0017] Third, the first gate metal layer and the second gate metal layer of this utility model can partially shield the gate drain capacitance (i.e., Miller capacitance), thereby reducing the Miller capacitance of the device and improving the switching speed of the device.

[0018] IV. The P-type well region of this invention forms an ohmic contact with the source metal layer, eliminating the need for additional P-type source region processing and reducing process costs.

[0019] V. This utility model adopts a multi-epitaxy process, which can reduce the difficulty of the process, improve the quality of the gate structure of the device, reduce the defect density, and improve the reliability of the device. Attached Figure Description

[0020] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0021] Figure 1 This is a schematic diagram of a gradient-doped discrete trench gate silicon carbide VDMOS according to the present invention.

[0022] Figure 2 This is a cross-sectional view of the process of a gradient-doped discrete trench gate silicon carbide VDMOS according to the present invention. Figure 1 .

[0023] Figure 3 This is a cross-sectional view of the process of a gradient-doped discrete trench gate silicon carbide VDMOS according to the present invention. Figure 2 .

[0024] Figure 4 This is a cross-sectional view of the process of a gradient-doped discrete trench gate silicon carbide VDMOS according to the present invention. Figure 3 .

[0025] Figure 5This is a cross-sectional view of the process of a gradient-doped discrete trench gate silicon carbide VDMOS according to the present invention. Figure 4 .

[0026] Figure 6 This is a cross-sectional view of the process of a gradient-doped discrete trench gate silicon carbide VDMOS according to the present invention. Figure 5 .

[0027] Figure 7 This is a cross-sectional view of the process of a gradient-doped discrete trench gate silicon carbide VDMOS according to the present invention. Figure 6 .

[0028] Figure 8 This is a cross-sectional view of the process of a gradient-doped discrete trench gate silicon carbide VDMOS according to the present invention. Figure 7 .

[0029] Figure 9 This is a cross-sectional view of the process of a gradient-doped discrete trench gate silicon carbide VDMOS according to the present invention. Figure 8 .

[0030] Figure 10 This is a cross-sectional view of the process of a gradient-doped discrete trench gate silicon carbide VDMOS according to the present invention. Figure 9 .

[0031] Figure 11 This is a cross-sectional view of the process of a gradient-doped discrete trench gate silicon carbide VDMOS according to the present invention. Figure 10 .

[0032] Figure 12 This is a cross-sectional view of the process of a gradient-doped discrete trench gate silicon carbide VDMOS according to the present invention. Figure 10 one.

[0033] Figure 13 This is a cross-sectional view of the process of a gradient-doped discrete trench gate silicon carbide VDMOS according to the present invention. Figure 10 two.

[0034] Figure 14 This is a cross-sectional view of the process of a gradient-doped discrete trench gate silicon carbide VDMOS according to the present invention. Figure 10 three.

[0035] Figure 15 This is a cross-sectional view of the process of a gradient-doped discrete trench gate silicon carbide VDMOS according to the present invention. Figure 10 Four. Detailed Implementation

[0036] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0038] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0039] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0040] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0041] like Figure 1 As shown, this application embodiment provides a gradient-doped discrete trench gate silicon carbide VDMOS, comprising:

[0042] Silicon carbide substrate 101;

[0043] A drift layer 102, the lower side of which is connected to the upper side of the silicon carbide substrate 101;

[0044] A first N-type region 103, the lower side of the first N-type region 103 is connected to the upper side of the drift layer 102;

[0045] The second N-type region 104, the lower side of the second N-type region 104 is connected to the upper side of the first N-type region 103;

[0046] P-type well region 105, the lower side of which is connected to the upper side of the second N-type region 104; N-type source region 1051 is provided in the P-type well region 105;

[0047] An insulating dielectric layer 106 is provided, which sequentially passes through the N-type source region 1051, the P-type well region 105, the second N-type region 104, and the first N-type region 103. The lower side of the insulating dielectric layer 106 is connected to the upper side of the drift layer 102. A second gate metal layer 1061 and a trench 1062 are provided in the insulating dielectric layer 106, and the second gate metal layer 1061 is located below the trench 1062.

[0048] A first gate metal layer 107 is disposed within the trench 1062;

[0049] Source metal layer 108, which is connected to the P-type well region 105 and the N-type source region 1051 respectively;

[0050] And a drain metal layer 109, which is connected to the lower side of the silicon carbide substrate 101.

[0051] In this embodiment, preferably, the bottom of the trench 1062 and the upper side of the second N-type region 104 are located on the same plane.

[0052] In this embodiment, preferably, the thickness of the second gate metal layer 1061 is 2-6 μm.

[0053] In this embodiment, preferably, the doping concentration of the first N-type region 103 is greater than the doping concentration of the drift layer 102; the doping concentration of the second N-type region 104 is greater than the doping concentration of the first N-type region 103; and the doping concentration of the P-type well region 105 is greater than the doping concentration of the second N-type region 104.

[0054] In this embodiment, preferably, the thickness of the first N-type region 103 is greater than or equal to the thickness of the second N-type region 104.

[0055] In this embodiment, preferably, the distance between the upper side of the second gate metal layer 1061 and the lower side of the first gate metal layer 107 is less than the distance between the lower side of the second gate metal layer 1061 and the upper side of the drift layer 102.

[0056] like Figures 1 to 15 As shown, the above-mentioned method for fabricating silicon carbide VDMOS includes the following steps:

[0057] Step 1: Epitaxial growth is performed on the side of a silicon carbide substrate 101 having a drain metal layer 109 to form a drift layer 102;

[0058] Step 2: Epitaxial growth is performed on the drift layer 102 to form the first N-type region 103;

[0059] Step 3: Epitaxial growth is performed on the first N-type region 103 to form the second N-type region 104;

[0060] Step 4: Form a barrier layer 110 on the second N-type region 104, etch the barrier layer 110 to form a via, and perform ion implantation to form a P-type trap region 105. The ion implantation energy is 70-230 keV.

[0061] Step 5: Remove the original barrier layer 110, form a barrier layer 110 on the second N-type region 104, etch the barrier layer 110 to form a via, and perform ion implantation to form an N-type source region 1051. The ion implantation energy is 70-170 keV.

[0062] Step 6: Remove the original barrier layer 110, re-form the barrier layer 110, etch the barrier layer 110 to form a via, etch the second N-type region 104 and the first N-type region 103 up to the upper side of the drift layer 102, and deposit to form the first insulating region 1063.

[0063] Step 7: Remove the original barrier layer 110, re-form the barrier layer 110, etch the barrier layer 110 to form a via, etch the first insulating region 1063, deposit metal, and form the second gate metal layer 1061.

[0064] Step 8: Remove the original barrier layer 110, re-form the barrier layer 110, etch the barrier layer 110 to form a via, and deposit to form a second insulating region 1064. The insulating dielectric layer 106 includes a first insulating region 1063 and a second insulating region 1064.

[0065] Step 9: Remove the original barrier layer 110, re-form the barrier layer 110, etch the barrier layer 110 to form a via, etch the second insulating region 1064 to form a trench 1062, deposit metal to form the first gate metal layer 107.

[0066] Step 10: Remove the original barrier layer 110, reform the barrier layer 110, etch the barrier layer 110 to form a via, and etch the second N-type region 104 to the upper side of the P-type well region 105, deposit metal to form the source metal layer 108, remove the barrier layer 110, and complete the fabrication.

[0067] In another embodiment of this invention, the doping concentration of the N-type silicon carbide substrate 101 is 1-5e18cm. -3 The doping concentration of the N-type drift layer 102 is 1-5e16cm. -3 The doping concentration of the first N-type region 103 is 1-5e17cm. -3 The doping concentration of the second N-type region 104 is 1-3e18cm. -3 The doping concentration of the P-type well region 105 is 0.8-1.2e19 cm⁻¹. -3 The doping concentration of the N-type source region 1051 is 1-5e18cm. -3 The insulating dielectric layer 106 can be made of one or a combination of silicon dioxide, aluminum nitride, and hafnium dioxide;

[0068] The doping concentration of the N-type silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer 109, thereby reducing the overall on-resistance of the device. The doping concentration of the N-type drift layer 102 is a trade-off between the reverse breakdown voltage and the on-resistance of the device. The first N-type region 103 and the second N-type region 104 are designed to form a concentration gradient with the N-type drift layer 102, thereby achieving a trapezoidal distribution of the drain positive voltage in the N-type drift layer 102, the first N-type region 103, and the second N-type region 104, thus improving the breakdown voltage capability of the device.

[0069] The doping concentration of the P-type well region 105 serves two purposes: first, it forms the P-type turn-off region from the N-type source region 1051 to the second N-type region 104, enabling turn-off and withstand voltage under zero gate voltage conditions; second, it forms a low-resistance ohmic contact with the source metal layer 108, forming a parasitic diode of the device, which completes freewheeling when the device is not conducting. The N-type source region 1051 is to ensure ohmic contact with the source metal layer 108 and to provide electrons when the device is conducting and forming a conductive channel.

[0070] The thickness of the N-type silicon carbide substrate 101 is 500-800 nm to ensure support for subsequent device fabrication. The thickness of the N-type drift layer 102 is 10-15 μm, adjusted within this range according to different requirements for device breakdown voltage. The thickness of the first N-type region 103 is 3-6 μm, and the thickness of the second N-type region 104 is 1-3 μm to form a concentration gradient and improve the device's breakdown voltage. The lower side of the insulating dielectric layer 106 is flush with the lower side of the first N-type region 103, and the distance between the lower side of the second gate metal layer 1061 and the insulating dielectric layer 106 is 2 μm. This is to improve the resistance to drain voltage surges of the second gate metal layer 1061. The thickness of the second gate metal layer 1061 is 2-6 μm. The lower side of the second gate metal layer 1061 is 1 μm higher than the upper side of the first N-type region 103. This is to enable the first gate metal layer 107 to control the second gate metal layer 1061. The lower side of the first gate metal layer 107 of the device is flush with the lower side of the P-type well region 105 to ensure the gate control capability of the device. The thickness of the P-type well region 105 is 500 nm, the thickness of the N-type source region 1051 is 300 nm, and the thickness of the source metal layer 108 is 200 nm.

[0071] A first gate metal layer 107 and a second gate metal layer 1061 are constructed inside the device. The first gate metal layer 107 effectively controls the inversion of the P-type well region 105 of the device to form a conductive channel. The second gate metal layer 1061 can increase the electron concentration, thereby reducing the on-resistance of the device. There is a 2μm thick insulating dielectric between the second gate metal layer 1061 and the drift layer 102, which can effectively suppress the gate-drain capacitance (Müller capacitance). Reducing the Miller capacitance of the device can effectively improve the switching speed of the device.

[0072] A first N-type region 103 and a second N-type region 104 are constructed on the upper part of the N-type drift layer 102 inside the device to achieve gradient doping. The functions are twofold: first, when the device is turned off, the voltage from the drain of the device is distributed in a trapezoidal pattern across the N-type drift layer 102, the first N-type region 103 and the second N-type region 104 to improve the breakdown voltage of the device; second, the doping concentration of the first N-type region 103 and the second N-type region 104 is higher than that of the N-type drift layer 102, which can distribute the current towards the edge of the device and avoid current concentration inside the device.

[0073] The P-type well region 105 constructed by the device can form an ohmic contact with the source metal layer 108, eliminating the need for additional P-type source region processing and reducing process costs.

[0074] The device structure employs a multi-epitaxy process, which reduces the difficulty of thick epitaxy, improves the quality of the device gate structure, reduces defect density, and enhances device reliability.

[0075] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A gradient doped separate-trench-gate silicon carbide VDMOS, characterized in that: include: silicon carbide substrate; A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; A first N-type region, the lower side of which is connected to the upper side of the drift layer; The second N-type region has its lower side surface connected to the upper side surface of the first N-type region; A P-type well region, the lower side of which is connected to the upper side of the second N-type region; an N-type source region is provided within the P-type well region; An insulating dielectric layer is provided, which sequentially passes through the N-type source region, the P-type well region, the second N-type region, and the first N-type region. The lower side of the insulating dielectric layer is connected to the upper side of the drift layer. A second gate metal layer and a trench are provided in the insulating dielectric layer, and the second gate metal layer is located below the trench. A first gate metal layer is disposed within the trench; A source metal layer, wherein the source metal layer is connected to the P-type well region and the N-type source region respectively; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.

2. A graded-doped, separate-trench- gate SiC VDMOS according to claim 1, wherein: The bottom of the trench is on the same plane as the upper side of the second N-type region.

3. A graded-doped, separate-trench- gate SiC VDMOS according to claim 1, wherein: The thickness of the second gate metal layer is 2-6 μm.

4. The gradient doped separate trench gate silicon carbide VDMOS of claim 1, wherein: The doping concentration of the first N-type region is greater than the doping concentration of the drift layer; the doping concentration of the second N-type region is greater than the doping concentration of the first N-type region; and the doping concentration of the P-type well region is greater than the doping concentration of the second N-type region.

5. The gradient-doped discrete trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The thickness of the first N-type region is greater than or equal to the thickness of the second N-type region.

6. A graded-doped, separate-trench- gate SiC VDMOS according to claim 1, wherein: The distance between the upper side of the second gate metal layer and the lower side of the first gate metal layer is less than the distance between the lower side of the second gate metal layer and the upper side of the drift layer.

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