Display panel and display device

Abstract

The embodiment of the utility model provides a display panel and a display device. The display panel includes: a gate layer; the silicon island is arranged on the gate layer; the data line layer is arranged on the silicon island; the first insulating layer is arranged on the data line layer; the first insulating layer is arranged on the data line layer, the first electrode layer is arranged on the first insulating layer, the first electrode layer is connected with the data line layer through a first bridging hole and connected with the gate layer through a second bridging hole, and the first insulating layer isolates the first electrode layer from the data line layer at the second bridging hole. According to the large-size display panel, through the specific stacked structure and the specific connection mode, the problem that normal display cannot be achieved due to the fact that loads are too large in an existing large-size display panel is effectively solved, and the display quality and stability are improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] As display products become larger and display frequencies increase, the load on liquid crystal displays (LCDs) continues to rise. When the size reaches a certain point, the driving capability of integrated circuits (ICs) can no longer meet the requirements for normal display. Although the load can be reduced by adding planarization layer materials, this method is too costly and greatly reduces the product's market competitiveness. Utility Model Content

[0003] This invention provides a display panel and display device that helps reduce the load on the display screen.

[0004] In a first aspect, this utility model provides a display panel, comprising:

[0005] Gate layer;

[0006] A silicon island, wherein the silicon island is disposed on the gate layer;

[0007] A data line layer, wherein the data line layer is disposed on the silicon island;

[0008] A first insulating layer is disposed on the data line layer;

[0009] A first electrode layer is disposed on the first insulating layer and connected to the data line layer through a first bridging hole and to the gate layer through a second bridging hole. The first insulating layer isolates the first electrode layer from the data line layer at the second bridging hole.

[0010] A second insulating layer is disposed on the first electrode layer.

[0011] In some embodiments, the display panel further includes a second electrode layer; the second electrode layer is disposed on the second insulating layer.

[0012] In some embodiments, the second insulating layer is made of a silicon nitride compound.

[0013] In some embodiments, the orthogonal projection of the second electrode layer onto the gate layer is misaligned with both the first bridging via and the second bridging via.

[0014] In some embodiments, a planarization layer is further disposed on the first insulating layer.

[0015] In some embodiments, the material used for planarization layer sampling is a resin-based material.

[0016] In some embodiments, the first insulating layer is made of a silicon nitride compound.

[0017] In some embodiments, the first bridging hole and the second bridging hole are misaligned in their orthogonal projections onto the gate layer.

[0018] In some embodiments, the bottom angles of both the first bridging hole and the second bridging hole are greater than 90 degrees.

[0019] Secondly, the present invention provides a display device, comprising: a backlight substrate and the display panel described above; the backlight substrate is disposed on the side of the substrate facing away from the auxiliary layer.

[0020] The display panel provided by this invention adjusts the film formation order of the first electrode layer and the second electrode layer, so that while the first electrode layer bridges the gate layer and the data line layer, a second insulating layer protects the first electrode layer. This reduces the load on the display panel and prevents the first electrode layer from failing to bridge the gate layer and data line layer due to water absorption. Through a specific stacking structure and connection method, this invention effectively solves the problem of abnormal display due to excessive load in existing large-size display panels, improving display quality and stability. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the first structure of the display panel provided by this utility model;

[0022] Figure 2 This is a schematic diagram of the second structure of the display panel provided by this utility model;

[0023] Figure 3 This is a schematic diagram of a display device provided by this utility model. Detailed Implementation

[0024] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0025] Furthermore, the terms "first," "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order. The terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0026] Please see Figure 1 , Figure 1 This is a schematic diagram of the first structure of the display panel provided by this utility model. The display panel includes a gate layer 101, a silicon island 102, a data line layer 103, a first insulating layer 104, and a first electrode layer 105.

[0027] The gate layer 101 is disposed at the bottom of the display panel, serving as the base layer of the display panel. The gate layer 101 is typically made of conductive materials, such as aluminum, copper, molybdenum, or their alloys, and is used to form the gate lines in the display panel.

[0028] Silicon island 102 is disposed on gate layer 101. Silicon island 102 is typically made of amorphous silicon, polycrystalline silicon, or oxide semiconductor material and is used to form the active layer of thin-film transistors in the display panel. A gate insulating layer may be disposed between silicon island 102 and gate layer 101 to isolate gate layer 101 and silicon island 102.

[0029] A data line layer 103 is disposed on the silicon island 102. The data line layer 103 is typically made of conductive materials, such as aluminum, copper, molybdenum, or their alloys, and is used to form data lines in the display panel. A contact layer may be disposed between the data line layer 103 and the silicon island 102 to ensure a good electrical connection.

[0030] A first insulating layer 104 is disposed on the data line layer 103. The first insulating layer 104 isolates the data line layer 103 from the first electrode layer 105, preventing short circuits between them. The first insulating layer 104 can be made of a silicon nitride compound material. Silicon nitride compounds have good insulation properties, thermal stability, and mechanical strength, effectively isolating the data line layer 103 from the first electrode layer 105 and preventing short circuits between them. Simultaneously, silicon nitride compounds also have good optical transparency, not affecting the light transmittance of the display panel. Furthermore, silicon nitride compounds have good moisture resistance and chemical stability, maintaining stable performance during the manufacturing and use of the display panel and extending its lifespan.

[0031] The first electrode layer 105 is disposed on the first insulating layer 104. The first electrode layer 105 is typically made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and is used to form pixel electrodes in the display panel. The first electrode layer 105 is connected to the data line layer 103 through a first bridging hole 108 and to the gate layer 101 through a second bridging hole 109. The first insulating layer 104 isolates the first electrode layer 105 and the data line layer 103 at the second bridging hole 109 to prevent short circuits between them.

[0032] The first bridging hole 108 is a through hole formed in the first insulating layer 104, used to connect the first electrode layer 105 and the data line layer 103. The shape of the first bridging hole 108 can be circular, elliptical, or polygonal, and its size can be designed according to the specific requirements of the display panel.

[0033] The second bridging via 109 is a through-hole formed in the first insulating layer 104, silicon island 102, data line layer 103, and other possible insulating layers, used to connect the first electrode layer 105 and the gate layer 101. The shape of the second bridging via 109 can be circular, elliptical, or polygonal, and its size can be designed according to the specific requirements of the display panel.

[0034] In this case, the bottom angle A of both the first bridging hole 108 and the second bridging hole 109 is greater than 90 degrees. The bottom angle A of the first bridging hole 108 and the second bridging hole 109 refers to the angle between the sidewall of the bridging hole and the bottom plane. When the bottom angle A is greater than 90 degrees, the bridging hole takes on an inverted conical or inverted trapezoidal shape, with the bottom opening smaller than the top opening.

[0035] This design has the following advantages: First, bridging holes with a bottom angle A greater than 90 degrees facilitate the filling of subsequent metal layers, reduce the risk of metal layer breakage in the bridging holes, and improve the reliability of the display panel; second, bridging holes with a bottom angle A greater than 90 degrees can reduce the impact of bridging holes on the underlying circuitry, reduce parasitic capacitance, and improve the response speed of the display panel; finally, bridging holes with a bottom angle A greater than 90 degrees can reduce stress concentration around the bridging holes, improving the mechanical strength and durability of the display panel.

[0036] The second insulating layer 106 is disposed on the first electrode layer 105. The second insulating layer 106 is used to isolate the first electrode layer 105 and the second electrode layer 107 to prevent short circuits between them. In addition, the second insulating layer 106 can also serve as a protective layer to protect the first electrode layer 105, improve the high temperature and high humidity reliability of the first electrode layer 105, prevent the first electrode layer 105 from absorbing water, which could lead to failure of the gate layer 101 and the data line layer 103, thereby improving the reliability of the product.

[0037] In this embodiment, the second insulating layer 106 is made of silicon nitride. Silicon nitride has good insulation properties, thermal stability, and mechanical strength, which can effectively isolate the first electrode layer 105 and the second electrode layer 107, preventing short circuits between them. At the same time, silicon nitride also has good optical transparency and will not affect the light transmittance of the display panel.

[0038] Traditional film deposition methods reduce load by adding a planarization layer. However, due to the limitations of via placement, the gate layer and data line layer must be bridged through the top first electrode layer. The material of this first electrode layer is prone to moisture absorption, which can easily cause bridging failure during high-temperature and high-humidity reliability verification. Furthermore, since the first electrode layer is on the top layer, the touch performance of the product will also be affected.

[0039] In this invention, the first electrode layer 105 is protected by the second insulating layer 106, which reduces the load on the display panel 10 and prevents the first electrode layer 105 from bridging the gate layer 101 and the data line layer 103 due to water absorption. This invention, through a specific stacking structure and connection method, effectively solves the problem of abnormal display due to excessive load in existing large-size display panels, thus improving display quality and stability.

[0040] Please continue reading. Figure 1 The display panel provided by this utility model also includes a second electrode layer 107.

[0041] The second electrode layer 107 is disposed on the second insulating layer 106. The second electrode layer 107 is typically made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and is used to form the common electrode in the display panel. The second electrode layer 107 and the first electrode layer 105 together form an electric field, driving the liquid crystal molecules to rotate and realize the display function.

[0042] Furthermore, the orthographic projection of the second electrode layer 107 onto the gate layer 101 is misaligned with both the first bridging via 108 and the second bridging via 109. This design avoids overlap between the second electrode layer 107 and the first and second bridging vias 108 and 109, reducing parasitic capacitance and improving the response speed and display quality of the display panel. In addition, the misalignment of the first and second bridging vias 108 and 109 increases the wiring flexibility of the display panel, facilitating circuit layout optimization and improving the integration and performance of the display panel.

[0043] Based on the technical solution of this utility model, it is necessary to change the film formation sequence of the first electrode layer 105 and the subsequent film layers. The specific film formation sequence is as follows: gate layer 101 (GATE) → silicon island 102 (Island) → data line layer 103 (SD) → first contact hole 108 (Contact1) → first electrode layer 105 (PITO) → second contact hole 109 (Contact2) → second electrode layer 107 (VITO).

[0044] Furthermore, this invention utilizes a first insulating layer 104 instead of a planarization layer, and the first insulating layer 104 is made of a silicon nitride compound material. While reducing the load, the capacitance between the data line layer 103 and the second electrode layer 107 is maximized, thus reducing costs.

[0045] Please see Figure 2 , Figure 2 This is a schematic diagram of a second structure of the display panel provided by this utility model. In the display panel of this embodiment, a planarization layer 110 is also provided on the first insulating layer 104.

[0046] A planarization layer 110 is disposed on the first insulating layer 104 to planarize the surface of the display panel and reduce the impact of surface unevenness on subsequent processes and display effects. The planarization layer 110 can be made of resin-based materials, such as acrylic resin, epoxy resin, or polyimide, which have good planarization effect and optical transparency.

[0047] In this embodiment, the planarization layer 110 is made of a resin-based material. Resin-based materials have good flowability and self-planarization properties, effectively filling in the unevenness of the display panel surface to form a smooth surface. Simultaneously, resin-based materials also possess good optical transparency and heat resistance, ensuring they do not affect the light transmittance and stability of the display panel.

[0048] Based on this utility model Figure 2 The technical solution shown requires changing the deposition sequence of the first electrode layer 105 and subsequent film layers. The specific deposition sequence is as follows: Gate layer 101 (GATE) → Silicon island 102 (Island) → Data line layer 103 (SD) → First contact hole 108 (Contact1) → Planarization layer 110 (PLN) → First electrode layer 105 (PITO) → Second contact hole 109 (Contact2) → Second electrode layer 107 (VITO) or Gate layer 101 (GATE) → Silicon island 102 (Island) → Data line layer 103 (SD) → Planarization layer 110 (PLN) → First contact hole 108 (Contact1) → First electrode layer 105 (PITO) → Second contact hole 109 (Contact2) → Second electrode layer 107 (VITO).

[0049] Please see Figure 3 , Figure 3 This is a schematic diagram of a display device provided by the present invention. The present invention provides a display device, including a backlight substrate and the aforementioned display panel.

[0050] The backlight substrate is located on the back of the display panel and is used to provide the light source required for the display. The backlight substrate typically includes components such as a light source, a light guide plate, a reflective sheet, a diffuser sheet, and a brightness enhancement film, which can produce uniform and bright backlight to ensure that the display device has a good display effect.

[0051] Furthermore, the backlight substrate 20 can be manufactured from various materials, such as an aluminum substrate or a glass substrate. Multiple LED light sources can be disposed on the backlight substrate 20 to provide uniform backlight illumination.

[0052] The display device can be a television set, computer monitor, mobile phone, tablet computer, or other electronic device with display functionality. By employing the display panel of this invention, the display device can have higher display quality, faster response speed, and longer service life.

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized by, include: Gate layer; A silicon island, wherein the silicon island is disposed on the gate layer; A data line layer, wherein the data line layer is disposed on the silicon island; A first insulating layer is disposed on the data line layer; A first electrode layer is disposed on the first insulating layer and connected to the data line layer through a first bridging hole and to the gate layer through a second bridging hole. The first insulating layer isolates the first electrode layer from the data line layer at the second bridging hole. A second insulating layer is disposed on the first electrode layer.

2. The display panel of claim 1, wherein, The display panel further includes a second electrode layer; the second electrode layer is disposed on the second insulating layer.

3. The display panel of claim 2, wherein, The second insulating layer is made of silicon nitride compound.

4. The display panel of claim 2, wherein, The orthogonal projection of the second electrode layer onto the gate layer is misaligned with both the first bridging hole and the second bridging hole.

5. The display panel of any one of claims 1 to 4, wherein, A planarization layer is also provided on the first insulating layer.

6. The display panel of claim 5, wherein, The material used for sampling the planarization layer is a resin-based material.

7. The display panel of claim 1, wherein, The first insulating layer is made of silicon nitride compound.

8. The display panel according to claim 1, characterized in that, The first bridging hole and the second bridging hole are misaligned in their orthogonal projections on the gate layer.

9. The display panel of claim 1, wherein, The bottom angles of both the first bridging hole and the second bridging hole are greater than 90 degrees.

10. A display device, characterized by comprising: include: Backlight substrate and display panel according to any one of claims 1 to 9; The backlight substrate is disposed on the back of the display panel.

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