Chip assembly

Abstract

The utility model discloses a chip assembly. The chip assembly comprises an SOT23 packaging substrate; a medium layer is arranged on an SOT23 packaging substrate, a memory chip and a logic chip are arranged on the outer surface of the medium layer, a phase change block is filled between the memory chip and the logic chip, a thermosensitive component is arranged in the medium layer, a power supply module is distributed at the edge of the medium layer in a surrounding manner, and a micro heat pipe array is integrated in the medium layer to form a vertical heat dissipation area. Water is filled inside; the micro heat pipe array absorbs heat, and the phase change block generates phase change between the memory chip and the logic chip and absorbs or releases a large amount of latent heat, so that the thermal impedance is dynamically adjusted; compared with the prior art, the heat dissipation efficiency of the chip is improved, and the temperature of the chip is kept stable.

Description

Technical Field

[0001] This utility model relates to an SOT23 package, and more particularly to a chip assembly. Background Technology

[0002] The SOT23 (Small Outline Transistor) package is a surface-mount package widely used in consumer electronics, communication devices, and other fields. It is favored for its miniaturization, low power consumption, and multi-pin design. This package is particularly suitable for devices requiring high-density integration and miniaturized design, such as smartphones, tablets, and wearable devices.

[0003] Existing heat dissipation designs are inefficient under high load conditions, making it difficult to effectively dissipate the heat generated by the chip, resulting in excessively high chip temperatures that affect performance and lifespan. Summary of the Invention

[0004] This invention overcomes the shortcomings of the prior art and provides a chip component.

[0005] To achieve the above objectives, the technical solution adopted by this utility model is as follows: a chip assembly, comprising: an SOT23 package substrate; an interposer fixed on the SOT23 package substrate; a memory chip and a logic chip fixed on the outer surface of the interposer; a phase change block filled between the memory chip and the logic chip; and a plurality of power modules distributed around the edge of the interposer.

[0006] The intermediate layer integrates a micro heat pipe array to form a vertical heat dissipation area;

[0007] The logic chip has a thermal component, which is encapsulated in an independent chamber within the interlayer. The chamber wall is made of multilayer graphene composite material for electromagnetic shielding and heat dissipation.

[0008] The memory chip and the logic chip are spaced apart to form a heat dissipation channel, and the power module is equipped with independent heat dissipation fins to form thermal isolation from the heat dissipation channel.

[0009] In a preferred embodiment of this invention, the heat dissipation channel is filled with a thermal interface material.

[0010] In a preferred embodiment of the present invention, the logic chip further includes a heat-generating component and a non-sensitive component. The heat-generating component is fixed on the outer surface of the interposer layer and spaced apart from the memory chip. The non-sensitive component is fixed on the outer surface of the interposer layer and located between the heat-generating component and the memory chip, thereby reducing the heat transferred to the memory chip.

[0011] In a preferred embodiment of this invention, the power module is spaced apart from the intermediate layer, and an aerogel material is filled between the power module and the intermediate layer to achieve thermal insulation.

[0012] In a preferred embodiment of this invention, the phase change block is a paraffin-based composite material, the melting point of which matches the chip's operating temperature range.

[0013] In a preferred embodiment of this invention, the surface of the heat pipe array is covered with a nano-scale hydrophilic coating to enhance capillary action and improve heat dissipation performance.

[0014] In a preferred embodiment of this invention, the surface of the power module is covered with a selective emission coating to enhance its infrared radiation heat dissipation capability.

[0015] In a preferred embodiment of the present invention, the chip assembly further includes an SOT23 package housing, the package housing being made of epoxy resin material.

[0016] In a preferred embodiment of this utility model, the SOT23 package substrate has a length of 250-253mm and a width of 59-61mm.

[0017] In a preferred embodiment of this invention, the SOT23 package shell material is copper or iron-nickel.

[0018] This utility model solves the defects existing in the background technology, and has the following beneficial effects:

[0019] (1) By setting an SOT23 package substrate; an interposer layer is set on the SOT23 package substrate, a memory chip and a logic chip are set on the outer surface of the interposer layer, a phase change block is filled between the memory chip and the logic chip, a thermal component is set in the interposer layer, a power module is distributed around the edge of the interposer layer, a micro heat pipe array is integrated inside the interposer layer to form a vertical heat dissipation area, and water is filled inside; the micro heat pipe array absorbs heat, and the phase change block between the memory chip and the logic chip undergoes a phase change, absorbing or releasing a large amount of latent heat, thereby dynamically adjusting the thermal resistance; compared with the prior art, the chip heat dissipation efficiency is improved and the chip temperature is kept stable.

[0020] (2) By encapsulating the thermal components in an independent chamber within an intermediate layer, the chamber wall is made of multilayer graphene composite material; it can conduct heat and provide electromagnetic shielding; compared with existing technologies, it effectively protects the thermal components from external electromagnetic interference.

[0021] (3) The power module is equipped with independent heat dissipation fins, which are made of copper, and aerogel material is filled between the power module and the interlayer. The heat dissipation fins dissipate heat to the surrounding environment through air convection. The aerogel material uses its ultra-low thermal conductivity to achieve thermal isolation, reduce heat transfer, and ensure that the power module and chipset are in a suitable temperature environment. Compared with the existing technology, the heat dissipation efficiency is further improved. Attached Figure Description

[0022] The present invention will be further described below with reference to the accompanying drawings and embodiments;

[0023] Figure 1 This is a structural diagram of the SOT23 package substrate of this utility model;

[0024] Figure 2 This is a structural diagram of a preferred embodiment of the present invention;

[0025] In the figure: 1. SOT23 package substrate; 2. Intermediate layer; 21. Micro heat pipe array; 22. Thermistor; 3. Memory chip; 4. Logic chip; 41. Non-sensitive component; 42. Heat-generating component; 5. Phase change block; 6. Power module. Detailed Implementation

[0026] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. These drawings are simplified schematic diagrams, which are only used to illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0027] like Figure 1 , Figure 2 As shown, a chip assembly includes:

[0028] SOT23 package substrate 1; an interposer layer 2 fixed on the SOT23 package substrate 1; a memory chip 3 and a logic chip 4 fixed on the outer surface of the interposer layer 2; and a phase change block 5 filled between the memory chip 3 and the logic chip 4.

[0029] Multiple power modules 6 are distributed around the edge of the intermediate layer 2;

[0030] The intermediate layer 2 has a micro heat pipe array 21 integrated inside, forming a vertical heat dissipation area;

[0031] The logic chip 4 has a thermal component 22, which is encapsulated in an independent chamber within the intermediary layer 2. The chamber wall is made of multilayer graphene composite material, which has both electromagnetic shielding and efficient heat dissipation functions.

[0032] Used for dynamically adjusting thermal resistance;

[0033] The power module 6 is equipped with independent heat dissipation fins, which form thermal isolation with the heat dissipation channel.

[0034] Specifically, a standard SOT23 package lead frame (such as a single-island structure) is used, and a multi-layer wiring structure is formed through etching. The substrate size is controlled within the range of 250-253mm in length and 59-61mm in width. An interposer layer 2 is fixed on top of the substrate. The material of the interposer layer 2 is silicon-based or ceramic substrate, and a micro heat pipe array 21 (diameter 10-50μm) is integrated inside. Vertical heat dissipation areas are formed through photolithography and electroplating processes. The thermistor 22 is a temperature sensor, which is packaged in the cavity and electrically connected by gold wire bonding. The cavity is also filled with an inert gas (argon) to prevent oxidation.

[0035] More specifically, an independent chamber is created within the intermediate layer 2. The chamber walls are grown with multilayer graphene (3-5 layers) using chemical vapor deposition (CVD), which provides both electromagnetic shielding (shielding effectiveness ≥30dB) and thermal conductivity (thermal conductivity >1500W / m·K).

[0036] Furthermore, the surface of the heat pipe array is covered with a nano-scale hydrophilic coating to enhance capillary action and improve heat dissipation performance.

[0037] Specifically, the surface is coated with a nano-scale hydrophilic coating of titanium dioxide. A heat pipe channel is pre-fabricated inside the intermediate layer 2, filled with water or ethanol to achieve efficient heat conduction. Because the heat pipe is filled with water or ethanol, the water or ethanol evaporates at the heating end and condenses back at the non-heating end, circulating and carrying away heat. The nano-scale hydrophilic coating covering the heat pipe surface enhances capillary action and improves the circulation efficiency of the working fluid.

[0038] Multilayer graphene composite materials have excellent electromagnetic shielding performance and high thermal conductivity, which can effectively shield external electromagnetic interference and conduct heat quickly, ensuring the stable working environment of the thermal component 22.

[0039] Heat sinks are mounted on the surface of power module 6 and are made of copper, while heat dissipation channels are located between memory chip 3 and logic chip 4.

[0040] Furthermore, the memory chip 3 and the logic chip 4 are spaced apart to form a heat dissipation channel, which is filled with a thermal interface material.

[0041] Specifically, the memory chip 3 (NAND Flash) and the logic chip 4 (MCU) are spaced 50-100μm apart to form a heat dissipation channel, and the thermal interface material is thermally conductive silicone grease to reduce contact thermal resistance.

[0042] Furthermore, the logic chip 4 also has a heat-generating component 42 and a non-sensitive component 41. The heat-generating component 42 is fixed on the outer surface of the interposer layer 2 and spaced apart from the memory chip 3. The non-sensitive component 41 is fixed on the outer surface of the interposer layer 2 and located between the heat-generating component 42 and the memory chip 3, in order to reduce the heat transferred to the memory chip 3.

[0043] The heat-generating component 323 can be a high-power transistor, a high-power resistor, or other such component. Therefore, the heat-generating component 42323 generates a large amount of heat during operation. Specifically, the non-sensitive component 41 is a resistor or capacitor, which is arranged between the logic chip 4 and the memory chip 3 and fixed with epoxy resin to reduce heat transfer.

[0044] Furthermore, the power module 6 is spaced apart from the intermediary layer 2, and an aerogel material is filled between the power module 6 and the intermediary layer 2 to achieve thermal isolation. Specifically, the aerogel material has ultra-low thermal conductivity, and its porous structure reduces heat conduction between the power module 6 and the intermediary layer 2, thereby achieving thermal isolation.

[0045] Furthermore, the phase change block 5 is a paraffin-based composite material, whose melting point matches the chip's operating temperature range;

[0046] Specifically, the phase change block 5 is made of paraffin-based composite material with a melting point that matches the high-temperature range of the chip's operating temperature (here, the melting point is 50-70℃). When the chip is working, a phase change occurs, absorbing or releasing a large amount of latent heat, thereby dynamically adjusting the thermal resistance and maintaining the chip temperature stability.

[0047] Furthermore, the surface of the power module 6 is covered with a selective emission coating to enhance infrared radiation heat dissipation capabilities. Specifically, the selective emission coating is aluminum oxide (Al2O3).

[0048] Furthermore, the chip assembly also includes an SOT23 package housing made of epoxy resin. Specifically, epoxy resin has a low coefficient of thermal expansion, which can reduce the impact of thermal stress on the chip.

[0049] Based on the preferred embodiments of this utility model described above, those skilled in the art can make various changes and modifications without departing from the technical concept of this utility model. The technical scope of this utility model is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A chip assembly, characterized by include: SOT23 package substrate (1), an intermediary layer (2) fixed on the SOT23 package substrate (1), a memory chip (3) and a logic chip (4) fixed on the outer surface of the intermediary layer (2), a phase change block (5) filled between the memory chip (3) and the logic chip (4), and a plurality of power modules (6) distributed around the edge of the intermediary layer (2). The intermediate layer (2) integrates a micro heat pipe array (21) to form a vertical heat dissipation area; The logic chip (4) has a thermal component (22), which is encapsulated in an independent chamber within the intermediary layer (2). The chamber wall is made of multilayer graphene composite material for electromagnetic shielding and heat dissipation. The memory chip (3) and the logic chip (4) are spaced apart to form a heat dissipation channel, and the power module (6) is equipped with heat dissipation fins to form thermal isolation with the heat dissipation channel.

2. A chip assembly according to claim 1, characterized in that: The heat dissipation channel is filled with thermal interface material.

3. The chip assembly of claim 1, wherein: The logic chip (4) also has a heat-generating component (42) and a non-sensitive component (41). The heat-generating component (42) is fixed on the outer surface of the interposer (2) and spaced apart from the memory chip (3). The non-sensitive component (41) is fixed on the outer surface of the interposer (2) and located between the heat-generating component (42) and the memory chip (3) to reduce the heat transferred to the memory chip (3).

4. A chip assembly according to claim 3, characterized in that: The power module (6) is spaced apart from the intermediate layer (2), and the space between the power module (6) and the intermediate layer (2) is filled with aerogel material.

5. The chip assembly of claim 3, wherein: The phase change block (5) is a paraffin-based composite material.

6. The chip assembly of claim 3, wherein: The surface of the micro heat pipe array (21) is covered with a nanoscale hydrophilic coating to enhance capillary action.

7. The chip assembly of claim 3, wherein: The power module (6) is covered with a selective emission coating to enhance infrared radiation heat dissipation.

8. The chip assembly of claim 1, wherein: The SOT23 package substrate (1) is also provided with an SOT23 package shell, which is made of epoxy resin material.

9. The chip assembly of claim 1, wherein: The SOT23 package substrate (1) has a length of 250-253 mm and a width of 59-61 mm.

10. The chip assembly of claim 8, wherein: The SOT23 package housing material is copper or iron-nickel.

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