Operation panel alarm processing system supporting independent dimming

Abstract

The utility model relates to an operation panel alarm processing system supporting independent dimming. A circuit board of the operation panel alarm processing system comprises an embedded MCU, a CAN communication circuit, a first group of chips, a second group of chips and a plurality of indicating lamp control circuits, wherein the first group of chips and the second group of chips are composed of a plurality of shift register chips. The embedded MCU comprises a CAN controller, an SPI controller and a PWM controller. The indicator light control circuit comprises an indicator light and two Darlington tubes. The CAN controller obtains a dimming instruction level and corresponding indicator light on-off and brightness information, adjusts the duty ratio of PWM1 and PWM2 signals through the PWM controller so as to control the output level of a QnA pin and the output level of a Qn pin respectively, achieves grouping control through sharing SCLK signals and utilizing CS1 and CS2, and achieves the dimming control through the cascade design of the SPI controller and the shift register chip set. The state and brightness of each indicating lamp can be independently and accurately controlled, occupation of MCU pins is remarkably reduced, sailors can find alarm information in the early stage, and losses caused by the fact that the alarm information is not processed in time are reduced.

Description

Technical Field

[0001] This utility model relates to the technical field of marine electronic circuit design and control, specifically to an alarm processing system for an operating panel that supports independent dimming. Background Technology

[0002] An alarm control panel is a device used to monitor and manage alarm status, typically found in industrial control, security systems, and fire protection systems. It integrates alarm display, operation buttons, and status indicators. Different colored lights indicate the operating status of the equipment or system; flashing or solid-on alarm indicators suggest an anomaly has been detected. Some alarm control panels have built-in buzzers or are linked to external alarms, providing both audible and visual alerts to help operators quickly identify and handle alarm events.

[0003] The navigation alarm control panel, as a specific application of the alarm control panel in the navigation control system, receives navigation system data via a CAN fieldbus to monitor and alarm related equipment and parameters of the navigation system. To adapt to the requirements of the corresponding operating environment, the navigation alarm control panel should have network or local dimming capabilities. The dimming command is ultimately implemented by modulating a PWM signal output to control the brightness of the indicator lights within the control panel. A 0% PWM signal duty cycle represents maximum brightness; a 100% PWM signal duty cycle represents off.

[0004] When a vessel is navigating at night or in certain specific modes, if an abnormal data alarm occurs when the alarm control panel is dimly lit, the corresponding indicator light may illuminate or flash, but the dimness may prevent the crew from noticing the alarm in time, thus missing the optimal response time and potentially jeopardizing navigational safety. In other words, if the navigation alarm control panel is dimmed to a low level (not the highest level) when an abnormal data alarm is triggered, even if the corresponding indicator light illuminates or flashes due to the alarm, the dimness will make it difficult to detect the alarm information in time, delaying the best opportunity to handle the alarm and causing serious losses and impacts.

[0005] In view of this, there is an urgent need for an alarm processing system with an operating panel that supports independent dimming, which can be used to monitor navigation data in real time, highlight alarm information, and provide audible and visual alarm status. Utility Model Content

[0006] To address the current problem that navigation alarm control panels lack independent dimming functionality for indicator lights, making it difficult to detect alarm information in a timely manner, this invention provides an alarm processing system for control panels that supports independent dimming. This system can independently control the flat brightness, high brightness, and off state of each indicator light. Each indicator light can be independently adjusted for brightness or turned off according to actual needs without affecting the status of other indicator lights, greatly improving the system's flexibility and response speed.

[0007] The technical solution of this utility model is as follows:

[0008] An alarm processing system for an alarm control panel supporting independent dimming includes a circuit board mounted on the alarm control panel. The circuit board includes an embedded MCU and a CAN communication circuit. The system is characterized in that the circuit board further includes a first group of chips composed of multiple shift register chips, a second group of chips, and multiple indicator light control circuits. The embedded MCU includes a CAN controller, an SPI controller, and a PWM controller. The indicator light control circuit includes one indicator light and two Darlington transistors.

[0009] The CAN communication circuit is connected to the CAN controller in the embedded MCU. The CAN communication circuit acquires CAN fieldbus messages and sends them to the CAN controller. The CAN controller receives the CAN fieldbus messages and parses them according to the communication protocol to obtain the dimming command level, alarm high brightness level, indicator light on / off information, and brightness information.

[0010] In the first group of chips, the NOE input pin of each shift register chip is connected to the PWM1 pin of the PWM controller, and the multiple parallel output pins of each shift register chip in the first group of chips are labeled as QnA pins, which are used to control the flat light display of the indicator light; in the second group of chips, the NOE input pin of each shift register chip is connected to the PWM2 pin of the PWM controller, and the multiple parallel output pins of each shift register chip in the second group of chips are labeled as Qn pins, which are used to control the bright light display of the indicator light.

[0011] The MOSI pin of the SPI controller is connected to the serial data input pin of the first shift register chip in the first group of chips and the first shift register chip in the second group of chips, respectively. Starting from the first shift register chip in each group of chips, the serial data input pin of each subsequent shift register chip is cascaded to the serial data output pin of the adjacent preceding shift register chip. The SCLK pin of the SPI controller is connected to the shift register clock input pin of each shift register chip in the first group of chips and the second group of chips, respectively. The CS1 pin of the SPI controller is connected to the memory register input pin of each shift register chip in the first group of chips. The CS2 pin of the SPI controller is connected to the memory register input pin of each shift register chip in the second group of chips.

[0012] The embedded MCU pre-generates a composite dimming data frame based on the indicator light on / off information and brightness information, and writes it to the SPI controller. The SPI controller sends the flat light data stream in the composite dimming data frame to each shift register chip in the first group of chips through the MOSI and SCLK pins, and synchronously latches the flat light data of each shift register chip in the first group of chips into its respective internal storage register through the CS1 pin. At the same time, it sends the high brightness data stream in the composite dimming data frame to each shift register chip in the second group of chips through the MOSI and SCLK pins, and synchronously latches the high brightness data of each shift register chip in the second group of chips into its respective internal storage register through the CS2 pin. The PWM controller adjusts the duty cycle of the PWM1 signal output by the PWM1 pin according to the dimming command level and combines it with the storage register to control the output level of the QnA pin to control the flat light display of the indicator light, and adjusts the duty cycle of the PWM2 signal output by the PWM2 pin according to the alarm high brightness level and combines it with the storage register to control the output level of the Qn pin to control the high brightness display of the indicator light.

[0013] In the indicator light control circuit, the negative terminal of each indicator light is connected to the collector of two Darlington transistors. The base of one Darlington transistor is connected to any QnA pin of a shift register chip in the first group of chips, and the base of the other Darlington transistor is connected to any Qn pin of a shift register chip in the second group of chips. The emitters of both Darlington transistors are grounded. The on and off states of the corresponding Darlington transistors are controlled by the output levels of the QnA and Qn pins, thereby achieving independent adjustment of the indicator light's flat brightness, high brightness, and off state.

[0014] Preferably, when the output level of the QnA pin of the first group of chips is low or high resistance, the Darlington transistor connected to it is turned off. At this time, the indicator light is controlled by the Qn pin of the second group of chips. The PWM controller adjusts the duty cycle of the PWM2 signal output by the PWM2 pin according to the alarm high brightness level to control the output level of the Qn pin, so that the indicator light is bright when an alarm occurs.

[0015] When the output level of the Qn pin of the second group of chips is low or high resistance, the Darlington transistor connected to it is turned off. At this time, the indicator light is controlled by the QnA pin of the first group of chips. The PWM controller adjusts the duty cycle of the PWM1 signal output by the PWM1 pin according to the dimming command level to control the output level of the QnA pin, so as to realize the flat light display of the indicator light.

[0016] When the output levels of the QnA pin of the first chip and the Qn pin of the second chip are both low or high, both Darlington transistors are turned off, and the indicator light is off.

[0017] Preferably, the device also includes a buzzer, a relay, and a power supply. The buzzer is connected to the GPIO pin of the embedded MCU and the power supply, respectively, and the relay is connected to the GPIO pin of the embedded MCU and an external alarm device, respectively.

[0018] Preferably, the buzzer and relay are connected to the GPIO pin of the embedded MCU via a transistor. The positive terminals of the buzzer and relay are connected to the power supply, the negative terminals of the buzzer and relay are connected to the collector of the transistor, the base of the transistor is connected to the GPIO pin of the embedded MCU, and the emitter of the transistor is grounded.

[0019] Preferably, the indicator light control circuit further includes a button, the button being connected to the GPIO pin of the embedded MCU, and the indicator light being disposed on the button and connected to the button.

[0020] Preferably, the buttons include an OK button, a Mute button, and a Test button.

[0021] Preferably, the number of shift register chips in the first group of chips is equal to the number of shift register chips in the second group of chips.

[0022] Preferably, the transistor is an NPN bipolar transistor, and the base of the transistor is connected to the GPIO pin of the embedded MCU through a current-limiting resistor.

[0023] Preferably, the frequencies of the PWM1 signal and the PWM2 signal are both within the range defined by a preset first frequency threshold and a second frequency threshold, and the duty cycle resolution of the PWM1 signal and the PWM2 signal is greater than or equal to the preset resolution threshold.

[0024] Preferably, the shift register chip is a 74HC595 chip.

[0025] The technical effects of this utility model are as follows:

[0026] This utility model provides an alarm processing system for an alarm control panel that supports independent dimming. The system includes a circuit board mounted on the alarm control panel. The circuit board comprises an embedded MCU, a CAN communication circuit, a first group of chips composed of multiple shift register chips, a second group of chips, and multiple indicator light control circuits. The embedded MCU includes a CAN controller, an SPI controller, and a PWM controller. The indicator light control circuit includes one indicator light and two Darlington transistors. The CAN communication circuit is connected to the CAN controller in the embedded MCU to acquire CAN fieldbus messages and send them to the CAN controller. The CAN controller receives the CAN fieldbus messages and parses them according to the communication protocol to obtain the dimming command level and the alarm high-brightness level. The NOE input pin of each shift register chip in the first group of chips is connected to the PWM1 pin of the PWM controller, and the multiple parallel output pins of each shift register chip in the first group of chips are labeled as QnA pins for controlling the parallel output of the indicator light. The first-stage indicator light display enables all flat-light control channels to synchronously respond to the PWM1 dimming signal, achieving uniform brightness changes across the entire group of indicator lights. This eliminates brightness differences caused by traditional discrete control and, by establishing a unified flat-light control network identifier, clearly distinguishes the high-brightness control circuit during PCB layout, reducing wiring error rates. In the second-stage chip group, the NOE input pin of each shift register chip is connected to the PWM2 pin of the PWM controller. Multiple parallel output pins of each shift register chip in the second-stage chip group are designated as Qn pins, used to control the high-brightness display of the indicator lights. This allows the alarm high-brightness signal to operate independently of the flat-light system and can be forced to full brightness in emergencies, forming an independent high-brightness control physical channel completely isolated from the flat-light circuit, avoiding false triggering caused by signal coupling. By adjusting the duty cycle of the PWM1 and PWM2 signals through the PWM controller, the output levels of the QnA and Qn pins can be controlled separately, thereby achieving precise control of the flat-light and high-brightness brightness of the indicator lights.

[0027] The MOSI pins of the SPI controller are connected to the serial data input pins (DS input pins) of the first shift register chip in the first group of chips and the first shift register chip in the second group of chips, respectively, realizing dual data stream transmission and synchronous updating of flat and highlighted data. Starting from the first shift register chip in each group of chips, the DS input pins of each subsequent shift register chip are cascaded to the serial data output pins (QP output pins) of the adjacent preceding shift register chip. By adopting the cascading method, the number of I / Os directly connected to the MCU is effectively reduced, thereby simplifying circuit design and wiring complexity, and greatly improving the flexibility and scalability of hardware design. The SCLK pin of the SPI controller is connected to the shift register clock input pin (SH_CP pin) of each shift register chip in the first and second groups of chips, respectively. The CS1 pin is connected to the storage register input pin (ST_CP pin) of each shift register chip in the first group of chips, and the CS2 pin is connected to the ST_CP pin of each shift register chip in the second group of chips. By controlling the first and second groups of chips through the CS1 and CS2 signals respectively, independent control of flat and high-brightness displays is achieved, enabling the system to handle two different display requirements simultaneously (such as flat brightness adjustment and alarm high-brightness flashing). The use of a shared SCLK signal ensures the consistency of data transmission. At the same time, the independent control of the two groups of chips through independent CS1 and CS2 signals improves the system's flexibility and scalability. By multiplexing the SCLK signal and using CS1 and CS2 to achieve group control, the number of MCU pins used is reduced, optimizing the utilization of hardware resources. Furthermore, since the latching operation of each chip is controlled by an independent CS signal, data conflicts or inconsistent state updates are avoided, further enhancing the stability and reliability of the system.

[0028] In the indicator light control circuit, the negative terminal of each indicator light is connected to the collectors of two Darlington transistors. The base of one Darlington transistor is connected to any QnA pin of a shift register chip in the first group of chips, and the base of the other Darlington transistor is connected to any Qn pin of a shift register chip in the second group of chips. The emitters of both Darlington transistors are grounded. The output levels of the QnA and Qn pins control the on / off state of the corresponding Darlington transistors, enabling independent adjustment of the indicator light's flat brightness, high brightness, and off state. By controlling the levels of the QnA and Qn pins respectively, the flat brightness and high brightness of the indicator light can be independently controlled, allowing each indicator light to be independently adjusted for brightness or turned off according to actual needs, greatly improving the system's flexibility and response speed. Simultaneously, The use of Darlington transistors enhances the circuit's driving capability and reliability, ensuring stable operation even under high load conditions. This design allows the alarm system to provide not only prominent visual warnings (bright flashing) in emergencies but also soft yet clear indications (flat display) during normal operation. This helps improve the overall user experience and ensures that important information is delivered promptly and effectively. Furthermore, since all shift register chips (such as the 74HC595 chip) share the same clock signal (SCLK) and latch signal (CS), the data input and latching actions of all chips are synchronized. Therefore, when sending a series of data frames, it ensures that the data is correctly allocated to each target register and the output status is updated at the same time, avoiding display confusion or errors caused by asynchrony.

[0029] This invention enables independent control of the flat brightness, high brightness, and off state of each indicator light, supporting any brightness level adjustment from completely off to maximum brightness. Through PWM signals (PWM1 and PWM2) combined with a shift register chip, precise control of indicator light brightness is achieved to meet visual needs in different scenarios. Each indicator light can independently perform functions such as high-brightness flashing, flat brightness display, or off alarm based on alarm information, without affecting the status of other indicator lights. It supports configurable alarm brightness levels, allowing dynamic adjustment of alarm brightness according to actual needs, ensuring a prominent visual warning in emergency situations. The system receives external commands and parses dimming levels and alarm information via a CAN communication circuit, ensuring real-time response to changes in the external environment or user needs. By sharing the SCLK signal and utilizing… CS1 and CS2 enable group control, and the cascaded design of the SPI controller and shift register chipset allows multiple 74HC595 chips to be controlled using only three MCU pins (MOSI, SCLK, CS), significantly reducing MCU pin usage and achieving efficient data transmission and synchronous updates, thus optimizing hardware resource utilization. By organically combining technologies such as CAN communication, PWM control, SPI data transmission, shift register cascading, and Darlington transistor driving, the status and brightness of each indicator light can be controlled independently and precisely, while possessing strong compatibility and scalability, making it suitable for various complex application scenarios.

[0030] This utility model features an alarm processing system with an independently dimming control panel. When an alarm for abnormal data occurs, multiple indicator lights on the alarm control panel can simultaneously exhibit high-brightness flashing, neutral brightness, and off states, with individual control independent of each other. Simultaneously, an internal buzzer sounds, triggering a relay output signal for linkage with an external alarm, enabling crew members to detect alarm information early and respond promptly. Configurable alarm brightness levels allow for gentle adjustment to the highest brightness within a specified time. Preferably, a 74HC595 chipset is used, allowing for cascading connections for I / O expansion schemes; theoretically, there is no upper limit to the number of buttons and indicator lights on the alarm control panel. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a preferred structure for the alarm processing system of the control panel that supports independent dimming according to this utility model.

[0032] Figure 2 This is a schematic diagram of the indicator light dimming control of this utility model. Detailed Implementation

[0033] To better understand the content of this utility model, it will be described in detail with reference to the accompanying drawings and embodiments.

[0034] This utility model relates to an alarm processing system with an alarm control panel that supports independent dimming. The alarm control panel is deployed in the ship's bridge area and has dimming functionality. It includes a circuit board mounted on the alarm control panel, which comprises an embedded MCU, a CAN communication circuit, a first group of chips and a second group of chips consisting of multiple shift register chips (preferably 74HC595 shift register output latch chip, referred to as 74HC595 chip), multiple indicator light control circuits, relays, and a buzzer, etc. The embedded MCU includes built-in functions such as a CAN controller, an SPI controller, and a PWM controller. The indicator light control circuit includes one indicator light and two Darlington transistors (preferably ULN2803 Darlington transistor chip), supporting both network and local dimming modes. When a data anomaly alarm occurs, the corresponding indicator light on the alarm control panel will flash brightly, the buzzer will sound, and a relay output signal will be triggered for linkage with an external alarm device. After the alarm, the corresponding indicator light should remain in the alarm state until personnel confirm the alarm is triggered, regardless of whether the data returns to normal. This state will continue until the "Confirm" or "Silence" button is pressed. When the "Silence" button on the alarm control panel is pressed or an external silence signal is input, the corresponding indicator light will continue to flash brightly, the buzzer will turn off, and the relay output will show an open circuit signal. When the "Confirm / Test" button on the alarm control panel is pressed or an external confirmation signal is input, the corresponding indicator light will continue to flash brightly, the buzzer will turn off, and the relay output will show an open circuit signal. Afterwards, the corresponding indicator light displays at a flat brightness, restoring the brightness when dimmed, the buzzer goes out, and the relay outputs an open-circuit signal; when the alarm information disappears, the corresponding indicator light goes out. When an alarm occurs, all indicator lights on the control panel can individually achieve high-brightness flashing, flat light, and extinguishing alarm functions without affecting the status of other indicator lights. It also has configurable alarm high-brightness levels. Each indicator light is jointly controlled by two Darlington transistors. By controlling the base level signals QnA and Qn of the Darlington transistors, the high-brightness, flat light, and extinguishing alarm functions are realized, enabling crew members to detect alarm information early and respond to alarm information in a timely manner.

[0035] Specifically, such as Figure 1 As shown, the system includes a circuit board mounted on the alarm operation board. The circuit board includes an embedded MCU, a CAN communication circuit, a first set of chips (composed of multiple shift register chips U1), a second set of chips (composed of multiple shift register chips U2), and multiple indicator light control circuits. The embedded MCU includes a CAN controller, an SPI controller, and a PWM controller. The indicator light control circuit includes an indicator light (K1, K2, ... or KN) and two Darlington transistors.

[0036] The CAN communication circuit is connected to the CAN controller in the embedded MCU. The CAN communication circuit acquires CAN fieldbus messages in real time (such as alarm information when data is abnormal) and sends them to the CAN controller. The CAN controller in the embedded MCU realizes CAN fieldbus communication through isolation circuits and transceiver chips and other peripheral devices. It receives CAN fieldbus messages in real time and parses them according to the communication protocol to obtain the dimming command level, alarm high brightness level, indicator light on / off information and brightness information. Combined with the user's button operation status, it determines the position and number of the corresponding flat light indicator light and the corresponding high brightness indicator light on the alarm operation board.

[0037] Each shift register chip in the first group of chips (preferably a 74HC595 chip, such as...) Figure 1 The NOE input pin (also known as the output enable pin NOE) of the first group of chips (represented by U1) is connected to the PWM1 pin of the PWM controller. Multiple parallel output pins of each shift register chip in the first group of chips are labeled as QnA pins (i.e., the multiple parallel output pins of each shift register chip are sequentially labeled Q1A, Q2A...QnA). Its SPI data stream is a flat light data stream, used to control the flat light display of the indicator light. That is, the PWM1 pin of the PWM controller is connected to the output enable pin NOE of each 74HC595 chip in the first group of chips. Through the output enable pin NOE of the first group of chips combined with the internal storage registers of the 74HC595 chip, the PWM signal with the parallel output pin network labeled QnA of the first group of chips is realized. Its SPI data stream is a flat light data stream, used for the flat light display of the indicator light. Preferably, when the output level signal of the QnA pin of the first group of chips is low or high resistance, i.e., when QnA = 0, the Darlington transistor connected to it is turned off. At this time, the indicator light is controlled solely by the Qn pin of the second group of chips. The PWM controller adjusts the duty cycle of the PWM2 signal output by the PWM2 pin according to the alarm high brightness level to control the output level of the Qn pin, so that the indicator light is brightly lit when an alarm occurs. When the output level signal of the Qn pin of the second group of chips is low or high resistance, i.e., when Qn = 0, the Darlington transistor connected to it is turned off. At this time, the indicator light is controlled solely by the QnA pin of the first group of chips. The PWM controller adjusts the duty cycle of the PWM1 signal output by the PWM1 pin according to the dimming command level to control the output level of the QnA pin. Its SPI data stream is a flat light data stream, used for flat light display of the indicator light brightness.

[0038] Each shift register chip in the second group of chips (preferably a 74HC595 chip, such as...) Figure 1The NOE input pins (represented by U2 in the diagram) are all connected to the PWM2 pin of the PWM controller. Multiple parallel output pins of each shift register chip in the second group of chips are labeled Qn (i.e., the multiple parallel output pins of each shift register chip are sequentially labeled Q1, Q2...Qn) to control the high-brightness display of the indicator lights. Specifically, the PWM2 pin of the PWM controller is connected to the NOE output enable pin of each 74HC595 chip in the second group of chips. Through the NOE output enable pins of the second group of chips combined with the internal memory registers of the 74HC595 chip, the PWM signal labeled Qn on the parallel output pin network of the second group of chips is realized. Its SPI data stream is a high-brightness data stream used for the high-brightness alarm display of the indicator lights. If the duty cycle of the PWM2 signal is 0% or connected to signal ground, the high-brightness alarm level of the indicator lights is the highest. In this chip design, the number of shift register chips in the first group is equal to the number of shift register chips in the second group. The QP pin of the last shift register chip in both groups is connected to a 10kΩ pull-up resistor to the power supply voltage VCC. This ensures that the QP pin remains high when there is no valid signal transmission, thus avoiding possible floating states (i.e., uncertain voltage levels) and improving signal stability and reliability. Furthermore, the frequencies of both PWM1 and PWM2 signals are within the range defined by a preset first and second frequency threshold. The duty cycle resolution of both PWM1 and PWM2 signals is greater than or equal to a preset resolution threshold, i.e., both frequencies are 1kHz ± 10%, and the duty cycle resolution is ≥ 8 bits.

[0039] It should be noted that the 74HC595 chip is a combination of an 8-bit shift register and a memory register. Changes in the NOE output enable pin only affect the link between the chip's memory register and the output pin; they do not affect the latching of data into the memory register by the internal shift register. The 74HC595 chip's function is to latch serial data input into the memory register and, simultaneously, control the link between the chip's internal memory register and the chip's output pin through changes in the NOE output enable pin signal. The internal storage registers and output pins of the chip are linked through the output enable pin NOE. This invention preferably uses the 74HC595 shift register output latch chip, but it is not the only one. Since the 74HC595 chip has two functions: latching and output enable, other chips with independent functions can also be used. That is, separate chips can be found for each function. For example, the parallel bus data input can be latched using the D-type flip-flop inside the 74HC273 latch chip, and the PWM signal can be connected to the output enable pin NOE of the 74HC244 output enable chip to achieve the same high-brightness flashing, flat-brightness, and off-light alarm functions. Furthermore, the 74HC273 and 74HC244 chips are also preferred, but not the only ones.

[0040] The MOSI pins of the SPI controller are connected to the serial data input pins (DS input pins) of the first 74HC595 shift register chip in the first and second groups of chips, respectively. Starting from the first 74HC595 shift register chip in each group, the DS input pins of each subsequent 74HC595 shift register chip are sequentially cascaded to the serial data output pins (QP output pins) of the adjacent preceding 74HC595 shift register chip, thus enabling the cascading of multiple 74HC595 chips; SPI controller The SCLK pin of the SPI controller is connected to the shift register clock input pin (i.e., SH_CP pin) of each shift register chip in the first and second groups of chips, respectively. The CS1 pin of the SPI controller is connected to the ST_CP pin (store register input signal) of each shift register chip in the first group of chips, and is used for dimming control logic. The CS2 pin of the SPI controller is connected to the store register input pin (i.e., ST_CP pin) of each 74HC595 shift register chip in the second group of chips, and is used for alarm high-brightness control logic. The embedded MCU pre-generates a composite dimming data frame based on the indicator light's on / off information and brightness information, and writes it to the SPI controller. The SPI controller sends two sets of data streams: First, it sends the flat light data stream from the composite dimming data frame to each shift register chip in the first group of chips via the MOSI and SCLK pins, and simultaneously latches the flat light data of each shift register chip in the first group of chips into its internal storage register via the CS1 pin. Second, it sends the high-brightness data stream from the composite dimming data frame to each shift register chip in the second group of chips via the MOSI and SCLK pins, and simultaneously latches the high-brightness data of each shift register chip in the second group of chips into its internal storage register via the CS2 pin. The PWM controller adjusts the duty cycle of the PWM1 signal output from the PWM1 pin according to the dimming command level and, in conjunction with the storage register, controls the output level of the QnA pin to control the flat light display of the indicator light. Third, it adjusts the duty cycle of the PWM2 signal output from the PWM2 pin according to the alarm high-brightness level and, in conjunction with the storage register, controls the output level of the Qn pin to control the high-brightness display of the indicator light.

[0041] When both the flat and high-brightness data streams are latched in the chip's memory register and their corresponding bits are 0, regardless of changes in the PWM1 and PWM2 signals, the chip's parallel output pins QnA and Qn will be in a low-level or high-resistance state, causing the subsequent Darlington transistor to turn off and the corresponding indicator light to turn off. When the flat and high-brightness data streams are latched in the chip's memory register and their corresponding bits are "0" and "1" respectively, regardless of changes in the PWM1 signal, the chip's output pin QnA will remain in a low-level or high-resistance state, causing the subsequent Darlington transistor to turn off. In this case, the indicator light is controlled independently by another set of chip output pins Qn. By changing the PWM2 signal, the chip's output pin Qn can switch between a high-level and high-resistance state, causing the subsequent Darlington transistor to turn on or off, thus enabling the indicator light to display a high-brightness alarm. In this case, the on / off state of the indicator light is determined by the SPI data stream, while the alarm brightness level is controlled by the PWM2 signal.

[0042] Similarly, when the flat light data stream and the bright light data stream are latched into the corresponding bits of the chip's memory register, which are "1" and "0" respectively, regardless of the changes in the PWM2 signal, the chip's output pin Qn will be in a low-level or high-resistance state, causing the Darlington transistor in the subsequent stage to turn off. At this time, the indicator light is controlled independently by another set of chip output pins QnA. Through changes in the PWM1 signal, the chip's output pin QnA can switch between a high-level and high-resistance state, causing the Darlington transistor in the subsequent stage to turn on or off, thus enabling the indicator light to achieve a flat light display. The on / off state of the indicator light is also determined by the SPI data stream, and the dimming level is controlled by the PWM1 signal.

[0043] Each indicator light is jointly controlled by two NPN Darlington transistors. By controlling the base level signals QnA and Qn of the Darlington transistors, high-brightness, level-brightness, and extinguishing alarm functions are achieved. During an alarm, all indicator lights on the alarm control panel can individually achieve high-brightness flashing, level-brightness, and extinguishing alarm functions without affecting the status of other indicator lights. It also features configurable alarm high-brightness levels. In the indicator light control circuit, the negative terminal of one indicator light is connected to the collector of both Darlington transistors. The base of one Darlington transistor is connected to the QnA pin, and the base of the other Darlington transistor is connected to the Qn pin. The emitters of both Darlington transistors are grounded. The on / off state of the corresponding Darlington transistor is controlled by the output levels of the QnA and Qn pins. All indicator lights on the alarm control panel can be independently adjusted for level-brightness, high-brightness, and extinguishing. Preferably, the indicator light control circuit also includes buttons. These buttons are connected to the GPIO pins of the embedded MCU to implement button functions such as "confirm," "mute," and "test." Indicator lights are mounted on the buttons and connected to them to form a single unit, creating an illuminated button. The embedded MCU controls the operating states of both the indicator light and the buzzer based on the signals generated by the button presses. More preferably, the buttons include function keys such as an confirm button, a mute button, and a test button. When the system detects an alarm signal, the indicator light flashes brightly, and the buzzer sounds. When the mute button is pressed, the indicator light remains brightly flashing, and the buzzer stops sounding. When either the confirm or test button is pressed, the indicator light returns to a flat display, and the buzzer stops sounding. When the alarm message disappears, the indicator light turns off. Furthermore, the buttons also include a dimming + button and a dimming - button. When the dimming control mode is switched to local, the brightness is adjusted using the dimming + button and the dimming - button.

[0044] Among them, such as Figure 1As shown, U1 is a 74HC595 chip in the first group of chips, and U2 is a 74HC595 chip in the second group of chips; U3 and U4 are Darlington transistor array chips (i.e., many Darlington transistors in multiple indicator light control circuits are integrated in the form of an array, preferably using ULN2803 Darlington transistor array chips, each of which contains 8 NPN Darlington transistors; of course, other types of Darlington transistor array chips containing other numbers of NPN Darlington transistors can also be used, such as ULN2003 Darlington...). The first and second groups of chips each have 8 parallel output pins, designated QA, QB, QC, QD, QE, QF, QG, and QH. The 8 parallel output pins of U1 are labeled QnA, i.e., Q1A, Q2A, Q3A, Q4A, Q5A, Q6A, Q7A, and Q8A respectively; the 8 parallel output pins of U2 are labeled Qn, i.e., Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8 respectively. Taking the ULN2803 Darlington transistor array chip as an example, an indicator light K1 can be controlled by two NPN Darlington transistors in U3, two NPN Darlington transistors in U4, or one NPN Darlington transistor in U3 and one NPN Darlington transistor in U4. When indicator light K1 is jointly controlled by two NPN Darlington transistors in U3, the negative terminal of indicator light K1 is connected to the load connection points (L1 and L2) corresponding to the collector output terminals (such as 1C and 2C) of the two Darlington transistors in U3; the base input terminal (1B) of one of the two Darlington transistors is connected to the Q1A pin of U1 in the first group of chips, and the base input terminal (2B) of the other Darlington transistor is connected to the Q1 pin of U2 in the second group of chips; the same applies when indicator light K1 is jointly controlled by two NPN Darlington transistors in U4, which will not be elaborated here.

[0045] When indicator light K1 is jointly controlled by one NPN Darlington transistor in U3 and one NPN Darlington transistor in U4, such as Figure 1 As shown, the negative terminal of indicator light K1 is connected to the load connection point (L1) corresponding to the collector output terminal (e.g., 1C) of a Darlington transistor in U3; and is also connected to the load connection point (L1) corresponding to the collector output terminal (e.g., 1C) of a Darlington transistor in U4; the base input terminal (1B) of a Darlington transistor in U3 is connected to the Q1A pin of U1 in the first group of chips, and the base input terminal (1B) of a Darlington transistor in U4 is connected to the Q1 pin of U2 in the second group of chips.

[0046] Preferably, the device further includes a buzzer, a relay, and a power supply. The buzzer is connected to the GPIO pin of the embedded MCU and the power supply, respectively. The relay is connected to the GPIO pin of the embedded MCU and an external alarm device, respectively. When the embedded MCU receives an alarm signal, it simultaneously triggers the buzzer to sound and the relay to close (i.e., triggers the relay to output a closing signal) to activate the external alarm device. This allows crew members to detect alarm information early, providing sufficient time to respond to and process the alarm, reducing losses caused by untimely alarm processing. More preferably, the buzzer and relay are connected to the GPIO pin of the embedded MCU via transistors. The positive terminals of both the buzzer and relay are connected to the power supply, and the negative terminals of both are connected to the collector of the transistor (preferably an NPN bipolar transistor). The base of the transistor is connected to the GPIO pin of the embedded MCU via a current-limiting resistor (10kΩ), and the emitter of the transistor is grounded.

[0047] like Figure 2 As shown, when the output level signal of the QnA pin of the first group of chips is low or high resistance (i.e., when QnA = 0), the Darlington transistor connected to it is turned off. At this time, the indicator light is controlled solely by the Qn pin of the second group of chips. The PWM controller adjusts the duty cycle of the PWM2 signal output from the PWM2 pin according to the alarm brightness level to control the output level of the Qn pin, thus achieving a high-brightness indicator light display when an alarm occurs. When the output level signal of the Qn pin of the second group of chips is low or high resistance (i.e., when Qn = 0), the Darlington transistor connected to it is turned off. At this time, the indicator light is controlled solely by the QnA pin of the first group of chips. The PWM controller adjusts the duty cycle of the PWM1 signal output from the PWM1 pin according to the dimming command level to control the output level of the QnA pin, thus achieving a flat brightness indicator light display.

[0048] Each indicator light is controlled by a combination of network-identified signals QnA and Qn. The QnA signal is controlled by the PWM1 signal from the 74HC595 chip's internal memory register and the NOE pin, while the Qn signal is controlled by the PWM2 signal from the 74HC595 chip's internal memory register and the NOE pin. By cleverly utilizing the PWM signal connected to the 74HC595 chip's NOE enable pin, two PWM signals (PWM1 and PWM2) are used to individually control the brightness, level, and off status of all indicator lights on the alarm control board. The alarm brightness level is configurable.

[0049] This utility model provides an alarm processing system for an operating board that supports independent dimming. By parsing CAN fieldbus network messages, it obtains the dimming command level, the corresponding indicator light on / off status, and brightness information. Using the dimming command level and configurable alarm high brightness level, it sets the duty cycles of PWM1 and PWM2. Through the SPI controller, it sends two sets of data streams to realize the functions of high-brightness flashing, leveling, and turning off of the corresponding indicator lights without affecting the status display of other indicator lights. At the same time, when an alarm is triggered, the internal buzzer sounds and triggers a relay to output a closed signal for linkage with an external alarm device. This allows crew members to detect alarm information early, giving them sufficient time to respond to and handle the alarm information, reducing losses caused by untimely alarm information processing.

[0050] It should be noted that the specific embodiments described above enable those skilled in the art to more fully understand the present invention, but do not limit the present invention in any way. Therefore, although the present invention has been described in detail with reference to the accompanying drawings and embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the present invention. In short, all technical solutions and improvements that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the present invention patent.

Claims

1. An operating panel alarm processing system supporting independent dimming, comprising a circuit board arranged in an alarm operating panel, the circuit board comprising an embedded MCU and a CAN communication circuit, characterized in that, The circuit board also includes a first group of chips composed of multiple shift register chips, a second group of chips, and multiple indicator light control circuits; the embedded MCU includes a CAN controller, an SPI controller, and a PWM controller; the indicator light control circuit includes one indicator light and two Darlington transistors; the CAN communication circuit is connected to the CAN controller in the embedded MCU. In the first group of chips, the NOE input pin of each shift register chip is connected to the PWM1 pin of the PWM controller, and the multiple parallel output pins of each shift register chip in the first group of chips are all labeled as QnA pins; in the second group of chips, the NOE input pin of each shift register chip is connected to the PWM2 pin of the PWM controller, and the multiple parallel output pins of each shift register chip in the second group of chips are all labeled as Qn pins; The MOSI pins of the SPI controller are connected to the serial data input pins of the first shift register chip in the first group of chips and the first shift register chip in the second group of chips, respectively. Starting from the first shift register chip in each group of chips, the serial data input pins of each subsequent shift register chip are sequentially cascaded to the serial data output pin of the adjacent preceding shift register chip. The SCLK pin of the SPI controller is connected to the shift register clock input pin of each shift register chip in the first group of chips and the second group of chips, respectively. The CS1 pin of the SPI controller is connected to the storage register input pin of each shift register chip in the first group of chips. The CS2 pin of the SPI controller is connected to the storage register input pin of each shift register chip in the second group of chips. The SPI controller sends the flat light data stream in the composite dimming data frame to each shift register chip in the first group of chips through the MOSI and SCLK pins, and simultaneously latches the flat light data of each shift register chip in the first group of chips into its internal storage register through the CS1 pin; at the same time, it sends the bright light data stream in the composite dimming data frame to each shift register chip in the second group of chips through the MOSI and SCLK pins, and simultaneously latches the bright light data of each shift register chip in the second group of chips into its internal storage register through the CS2 pin. The PWM controller adjusts the duty cycle of the PWM1 signal output from the PWM1 pin according to the dimming command level and combines it with the storage register to control the output level of the QnA pin. It also adjusts the duty cycle of the PWM2 signal output from the PWM2 pin according to the alarm high brightness level and combines it with the storage register to control the output level of the Qn pin. In the indicator light control circuit, the negative terminal of one indicator light is connected to the collector of two Darlington transistors. The base of one Darlington transistor in the indicator light control circuit is connected to any QnA pin of a shift register chip in the first group of chips, and the base of the other Darlington transistor is connected to any Qn pin of a shift register chip in the second group of chips. The emitters of both Darlington transistors are grounded.

2. The operating panel alarm processing system supporting independent dimming according to claim 1, wherein When the output level of the QnA pin of the first group of chips is low or high resistance, the Darlington transistor connected to it is turned off. At this time, the indicator light is controlled by the Qn pin of the second group of chips. The PWM controller adjusts the duty cycle of the PWM2 signal output by the PWM2 pin according to the alarm high brightness level to control the output level of the Qn pin. When the output level of the Qn pin of the second group of chips is low or high resistance, the Darlington transistor connected to it is turned off. At this time, the indicator light is controlled by the QnA pin of the first group of chips. The PWM controller adjusts the duty cycle of the PWM1 signal output by the PWM1 pin according to the dimming command level to control the output level of the QnA pin. When the output levels of the QnA pin of the first chip and the Qn pin of the second chip are both low or high, both Darlington transistors are turned off, and the indicator light is off.

3. The operating panel alarm processing system supporting independent dimming according to claim 1, wherein It also includes a buzzer, a relay, and a power supply. The buzzer is connected to the GPIO pin of the embedded MCU and the power supply, respectively. The relay is connected to the GPIO pin of the embedded MCU and an external alarm device, respectively.

4. The operating panel alarm processing system supporting independent dimming according to claim 3, wherein The buzzer and relay are connected to the GPIO pin of the embedded MCU via a transistor. The positive terminals of the buzzer and relay are connected to the power supply, the negative terminals of the buzzer and relay are connected to the collector of the transistor, the base of the transistor is connected to the GPIO pin of the embedded MCU, and the emitter of the transistor is grounded.

5. The operating panel alarm processing system of claim 3, wherein, The indicator light control circuit also includes a button, which is connected to the GPIO pin of the embedded MCU, and the indicator light is mounted on the button and connected to the button.

6. The operating panel alarm processing system of claim 5, wherein, The buttons include an OK button, a Mute button, and a Test button.

7. The operating panel alarm processing system of claim 1, wherein, The number of shift register chips in the first group of chips is equal to the number of shift register chips in the second group of chips.

8. The operating panel alarm processing system of claim 4, wherein, The transistor is an NPN bipolar transistor, and the base of the transistor is connected to the GPIO pin of the embedded MCU through a current-limiting resistor.

9. The operating panel alarm processing system of claim 1, wherein, The frequencies of the PWM1 signal and the PWM2 signal are both within the range defined by the preset first frequency threshold and the second frequency threshold, and the duty cycle resolution of the PWM1 signal and the PWM2 signal is greater than or equal to the preset resolution threshold.

10. The operating panel alarm processing system of claim 1, wherein, The shift register chip is a 74HC595 chip.

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