MOSFET device
By setting a Schottky metal layer at the bottom corner of the trench in a SiC MOSFET device to form a Schottky barrier diode, the problems of easy breakdown of the gate oxide layer and high switching loss are solved, achieving high withstand voltage, low turn-on voltage and low loss, thus replacing an additional diode.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- XIAMEN XINERGY MICROELECTRONICS CO LTD
- Filing Date
- 2025-04-30
- Publication Date
- 2026-04-21
AI Technical Summary
Existing SiC MOSFET devices have concentrated electric fields at the bottom corner of the trench, which makes the gate oxide layer prone to breakdown and failure. In addition, the built-in body diode has a high turn-on voltage and large switching losses, which affects high-frequency applications. The additional diode increases the cost.
A fully covered Schottky metal layer is set at the bottom corner of the trench to form a Schottky barrier diode (SBD), which replaces the built-in diode and improves the voltage withstand and switching loss of the gate oxide layer.
It improves the device's withstand voltage and reduces the turn-on voltage and switching losses, replacing an additional diode and saving costs.
Smart Images
Figure CN224154560U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor power device technology, and in particular to a MOSFET device. Background Technology
[0002] A silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) is a MOSFET manufactured using silicon carbide (SiC) semiconductor material. Compared to traditional silicon (Si) MOSFETs, SiC MOSFETs have lower on-resistance, lower switching losses, and higher high-temperature performance, making them increasingly outstanding in high-temperature, high-frequency, and high-voltage applications.
[0003] Existing SiC MOSFETs come in two types: planar and trench. Trench MOSFETs have smaller cell sizes, offering an advantage in area saving. However, the electric field is concentrated at the bottom corner of the trench in trench-type SiC MOSFETs, making the gate oxide layer at the corner prone to breakdown failure. Furthermore, SiC MOSFETs require an anti-parallel diode for freewheeling in practical applications. The built-in body diode of SiC MOSFETs has a high turn-on voltage and high switching losses, affecting the device's switching frequency. Therefore, SiC MOSFETs require an additional diode for freewheeling to maintain a high-frequency, low-loss application environment, leading to increased costs.
[0004] It should be noted that the information disclosed in this background section is intended only to enhance the understanding of the overall background of this utility model, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Utility Model Content
[0005] To address the challenges of existing technologies, this invention provides a novel MOSFET device comprising a substrate, a P-well region, an N-source region, and a Schottky metal layer. The P-well region is disposed on the substrate, and the N-source region is disposed on the P-well region. A trench is formed between the N-source region, the P-well region, and the substrate. The trench has sidewalls and a bottom wall, with the sidewalls connecting to the bottom wall and forming a corner. The Schottky metal layer is located within the trench and covers the sidewalls, bottom wall, and corner of the trench. The upper surface of the Schottky metal layer is lower than that of the P-well region.
[0006] Furthermore, the MOSFET device also includes a silicon oxide layer that covers the Schottky metal layer, with the upper surface of the silicon oxide layer being lower than the P-well region.
[0007] Furthermore, the MOSFET device also includes a gate oxide layer and a polysilicon layer, the polysilicon layer being disposed on the silicon oxide layer, and the gate oxide layer connecting the Schottky metal layer, the polysilicon layer, the substrate, the P-well region, and the N-source region.
[0008] Furthermore, the MOSFET device also includes an interlayer dielectric layer, a contact hole, a front metal layer, and a back metal layer. The interlayer dielectric layer covers the gate oxide layer. The contact hole extends downward from the upper surface of the interlayer dielectric layer to the P-well region. The front metal layer is disposed on the interlayer dielectric layer and connects to the contact hole. The back metal layer is disposed on the lower surface of the substrate.
[0009] Furthermore, the depth of the trench ranges from 2 to 3 μm.
[0010] Furthermore, the substrate material includes silicon carbide.
[0011] The present invention provides a MOSFET device that, by setting a fully covered Schottky metal layer at the bottom corner of the trench, forms a Schottky barrier diode (SBD) with the substrate. This effectively improves the problem of easy breakdown failure of the gate oxide layer at the bottom corner of the trench in MOSFET devices, and has the characteristics of high withstand voltage, low turn-on voltage and low switching loss. It can be used as a freewheeling diode to replace an additional diode.
[0012] Other features and beneficial effects of this invention will be set forth in the following description, and some of the technical features and beneficial effects may be apparent from the description or learned by practicing this invention. Attached Figure Description
[0013] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, some of the drawings in the following description are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0014] Figure 1 This is a schematic flowchart of a method for manufacturing a MOSFET device according to an embodiment of the present invention;
[0015] Figures 2 to 9 This is a schematic diagram of the structure of a MOSFET device at each stage of the manufacturing process according to an embodiment of the present invention;
[0016] Figure 10 This is a schematic diagram of the structure of a MOSFET device provided in an embodiment of the present invention.
[0017] Figure label:
[0018] 100 - Substrate; 110 - Trench; 111 - Sidewall; 112 - Bottom wall; 120 - Schottky metal layer; 130 - Silicon oxide layer; 140 - Gate oxide layer; 150 - Polysilicon layer; 160 - P-well region; 170 - N-source region; 180 - Interlayer dielectric layer; 190 - Contact hole; 200 - Front metal layer; 210 - Back metal layer. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. The technical features designed in the different embodiments of this utility model described below can be combined with each other as long as they do not conflict with each other. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the protection scope of this utility model.
[0020] In the description of this utility model, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, unless otherwise stated, "a plurality of" means two or more. Additionally, the term "comprising" and any variations thereof mean "at least comprising."
[0021] Please see Figures 1 to 9 . Figure 1 This is a schematic flowchart illustrating a method for manufacturing a MOSFET device according to an embodiment of the present invention. Figures 2 to 9 This is a schematic diagram of the structure of a MOSFET device at each stage of the manufacturing process according to an embodiment of the present invention.
[0022] As shown in the figure, a method for manufacturing a MOSFET device according to an embodiment of the present invention includes the following steps:
[0023] S100: A trench 110 is etched on the substrate 100. The trench 110 has sidewalls 111 and a bottom wall 112. The sidewalls 111 connect to the bottom wall 112 and form a corner. The material of the substrate 100 may include silicon carbide.
[0024] S200: A Schottky metal layer 120 is disposed within the trench 110, the Schottky metal layer 120 covering the sidewalls 111, bottom wall 112, and corners of the trench 110. The material of the Schottky metal layer 120 may include platinum (Pt), gold (Au), palladium (Pd), etc.
[0025] S300: A silicon oxide layer 130 is formed on the surface of the Schottky metal layer 120. The silicon oxide layer 130 is located within the trench 110. The silicon oxide layer 130 is etched, and the upper surface of the etched silicon oxide layer 130 is lower than the junction depth of the preset P-well region 160. The thickness of the etched silicon oxide layer 130 corresponds to the height of the Schottky metal layer 120. The Schottky metal layer 120 cannot exceed the junction depth of the P-well region 160; otherwise, an inversion layer cannot be formed, a conductive channel cannot be formed, and the device cannot be switched on or off.
[0026] S400: Remove the Schottky metal layer 120 that is not covered by the silicon oxide layer 130.
[0027] Furthermore, the manufacturing method of a MOSFET device may also include the following steps:
[0028] S500: A gate oxide layer 140 and a polysilicon layer 150 are disposed in the trench 110. The gate oxide layer 140 is connected to the substrate 100, and the polysilicon layer 150 is connected to the gate oxide layer 140.
[0029] S600: A P-well region 160 and an N-source region 170 are formed within the substrate 100 via ion implantation, with the P-well region 160 connected to the N-source region 170. The P-well region 160 is higher than the Schottky metal layer 120. In other words, the Schottky metal layer 120 cannot cover the sidewalls beyond the depth of the P-well region 160; otherwise, it will affect the formation of the inversion layer in the P-well region 160, preventing the formation of a conductive channel and thus rendering the device unable to switch on or off.
[0030] S700: An interlayer dielectric layer 180, a contact hole 190, a front metal layer 200, and a back metal layer 210 are provided. The interlayer dielectric layer 180 covers the gate oxide layer 140. The contact hole 190 extends downward from the upper surface of the interlayer dielectric layer 180 to the P-well region 160. The front metal layer 200 is disposed on the interlayer dielectric layer 180 and connects to the contact hole 190. The back metal layer 210 is disposed on the lower surface of the substrate 100.
[0031] Combination Figures 2 to 9 Let's look at it firstly, as Figure 2As shown, a silicon carbide substrate 100 is provided, and trenches 110 are formed on the substrate 100. The depth of the trenches 110 can be in the range of 2~3μm.
[0032] like Figure 3 As shown, a Schottky metal layer 120 is formed within trench 110 by metal sputtering. The Schottky metal layer 120 covers the sidewalls 111, bottom wall 112, and corners of trench 110, thereby forming a Schottky barrier diode (SBD) with the substrate 100. This effectively improves the problem of easy breakdown failure of the gate oxide layer 140 at the bottom corner of trench 110 in MOSFET devices, and has the characteristics of high withstand voltage, low turn-on voltage, and low switching loss, making it suitable as a freewheeling diode to replace an additional diode. Conversely, if the Schottky metal layer 120 is only formed at the bottom of the trench (i.e., only covering the bottom wall 112), the concentrated electric field at the corner will break down the exposed gate oxide layer 140 at the corner. If the Schottky metal layer 120 is only formed on the sidewall 111, the exposed gate oxide layer 140 at the bottom of trench 110 will also be broken down by the concentrated electric field, failing to effectively protect the device.
[0033] like Figure 4 As shown, a silicon oxide layer 130 is grown on the surface of the Schottky metal layer 120 by chemical vapor deposition.
[0034] like Figure 5 As shown, the silicon oxide layer 130 is etched. The etching depth of the silicon oxide layer 130 ranges from 1.5 to 2.5 μm. The thickness of the etched silicon oxide layer 130 can be retained at approximately 0.5 μm.
[0035] like Figure 6 As shown, the etched silicon oxide layer 130 is used as a barrier layer, and the Schottky metal layer 120 not covered by the silicon oxide layer 130 is removed by wet etching.
[0036] like Figure 7 As shown, a gate oxide layer 140 and a polysilicon layer 150 are disposed in the trench 110, and then the polysilicon layer 150 is etched back.
[0037] like Figure 8 As shown, a P-well region 160 and an N-source region 170 are formed in the substrate 100 by ion implantation.
[0038] like Figure 9 As shown, an interlayer dielectric layer 180, a contact hole 190, a front metal layer 200, and a back metal layer 210 are formed. The interlayer dielectric layer 180 covers the gate oxide layer 140. The contact hole 190 extends downward from the upper surface of the interlayer dielectric layer 180 to the P-well region 160. The front metal layer 200 is disposed on the interlayer dielectric layer 180 and connects to the contact hole 190. The back metal layer 210 is disposed on the lower surface of the substrate 100.
[0039] Finally, the Schottky metal layer 120 and the front metal layer 200 are connected to the source, the polysilicon layer 150 is connected to the gate, and the back metal layer 210 is connected to the drain.
[0040] Please see Figure 10 , Figure 10 This is a schematic diagram of the structure of a MOSFET device provided in an embodiment of the present invention. Figure 10 The MOSFET device shown can be fabricated using the manufacturing method described above. As shown, the MOSFET device includes a substrate 100, a P-well region 160, an N-source region 170, and a Schottky metal layer 120.
[0041] A P-well region 160 is disposed on the substrate 100, and an N-source region 170 is disposed on the P-well region 160. A trench 110 is formed between the N-source region 170, the P-well region 160, and the substrate 100. The trench 110 has sidewalls 111 and a bottom wall 112, with the sidewalls 111 connecting to the bottom wall 112 and forming a corner. A Schottky metal layer 120 is located within the trench 110, covering the sidewalls 111, the bottom wall 112, and the corner of the trench 110. The upper surface of the Schottky metal layer 120 is lower than the P-well region 160. That is, the Schottky metal layer 120 covering the sidewalls 111 cannot exceed the depth of the P-well region 160. If it does, it will affect the formation of an inversion layer in the P-well region 160, preventing the formation of a conductive channel and causing the device to fail to switch on or off. By providing a fully covered Schottky metal layer 120 at the bottom corner of trench 110, a Schottky barrier diode (SBD) is formed between the Schottky metal layer 120 and the substrate 100. This effectively improves the problem of easy breakdown failure of the gate oxide layer 140 at the bottom corner of trench 110 in MOSFET devices. Furthermore, it features high breakdown voltage, low turn-on voltage, and low switching losses, and can be used as a freewheeling diode to replace an additional diode.
[0042] Furthermore, the MOSFET device also includes a silicon oxide layer 130, which covers the Schottky metal layer 120, and the upper surface of the silicon oxide layer 130 is lower than the P-well region 160. The depth of the trench 110 can be in the range of 2~3 μm.
[0043] Furthermore, the MOSFET device also includes a gate oxide layer 140 and a polysilicon layer 150. The polysilicon layer 150 is disposed on the silicon oxide layer 140, and the gate oxide layer 140 connects the Schottky metal layer 120, the polysilicon layer 150, the substrate 100, the P-well region 160, and the N-source region 170.
[0044] Furthermore, the MOSFET device also includes an interlayer dielectric layer 180, a contact hole 190, a front metal layer 200, and a back metal layer 210. The interlayer dielectric layer 180 covers the gate oxide layer 140. The contact hole 190 extends downward from the upper surface of the interlayer dielectric layer 180 to the P-well region 160. The front metal layer 200 is disposed on the interlayer dielectric layer 180 and connects to the contact hole 190. The back metal layer 210 is disposed on the lower surface of the substrate 100.
[0045] In summary, the MOSFET device provided by this utility model, by setting a fully covered Schottky metal layer 120 at the bottom corner of the trench 110, forms a Schottky barrier diode (SBD) with the substrate 100. This effectively improves the problem of easy breakdown failure of the gate oxide layer 140 at the bottom corner of the trench 110 in the MOSFET device, and has the characteristics of high withstand voltage, low turn-on voltage and low switching loss. It can be used as a freewheeling diode to replace an additional diode.
[0046] Furthermore, those skilled in the art should understand that although many problems exist in the prior art, each embodiment or technical solution of this utility model can be improved in only one or a few aspects, without necessarily solving all the technical problems listed in the prior art or background art simultaneously. Those skilled in the art should understand that any content not mentioned in a claim should not be construed as a limitation on that claim.
[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.
Claims
1. A MOSFET device, characterized in that: The MOSFET device includes: Substrate; A P-well region is disposed on the substrate; The N-source region is located on the P-well region; A trench is formed between the N-source region, the P-well region, and the substrate. The trench has sidewalls and a bottom wall, and the sidewalls connect to the bottom wall and form a corner. A Schottky metal layer is located within the trench, covering the sidewalls, bottom wall, and corners of the trench, with the upper surface of the Schottky metal layer being lower than the P-well region.
2. The MOSFET device of claim 1, wherein: The MOSFET device further includes a silicon oxide layer that covers the Schottky metal layer, with the upper surface of the silicon oxide layer being lower than the P-well region.
3. The MOSFET device of claim 2, wherein: The MOSFET device further includes a gate oxide layer and a polysilicon layer, the polysilicon layer being disposed on the silicon oxide layer, and the gate oxide layer connecting the Schottky metal layer, the polysilicon layer, the substrate, the P-well region, and the N-source region.
4. The MOSFET device of claim 3, wherein: The MOSFET device further includes an interlayer dielectric layer, a contact hole, a front metal layer, and a back metal layer. The interlayer dielectric layer covers the gate oxide layer. The contact hole extends downward from the upper surface of the interlayer dielectric layer to the P-well region. The front metal layer is disposed on the interlayer dielectric layer and connects to the contact hole. The back metal layer is disposed on the lower surface of the substrate.
5. The MOSFET device of claim 1, wherein: The depth of the trench ranges from 2 to 3 μm.
6. The MOSFET device of claim 1, wherein: The substrate is made of silicon carbide.