Semiconductor package

Abstract

A semiconductor package is provided. The package includes a first die and a second die coupled to the first die. The first crystal grain comprises a through hole structure and an electrostatic discharge (ESD) protection structure, and the first crystal grain comprises a through hole structure and an electrostatic discharge (ESD) protection structure. The electrostatic discharge protection structure includes a resistor connected in series between the via structure and the electrostatic discharge protection element. One end of the electrostatic discharge protection element is coupled to the substrate of the first die.

Description

Technical Field

[0001] This disclosure pertains to a semiconductor package. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this increase in integration density stems from the iterative reduction of the minimum feature size (e.g., shrinking semiconductor process nodes to below 20 nanometers), thus allowing more components to be integrated into a given area. With the recent growing demand for miniaturization, higher speeds and wider bandwidths, as well as lower power consumption and latency, the need for packaging technologies for smaller, more advanced semiconductor dies has also increased. Utility Model Content

[0003] In some embodiments, this disclosure provides a semiconductor package. The semiconductor package includes a first die. The first die includes a through-hole structure and an electrostatic discharge (ESD) protection structure, wherein the ESD protection structure includes a resistor and an ESD protection element. The resistor is coupled to the through-hole structure. The ESD protection element is connected in series with the resistor, wherein one end of the ESD protection element is coupled to a substrate of the first die.

[0004] In some embodiments, this disclosure also provides a semiconductor package. The semiconductor package includes a first die. The first die includes a through-hole structure and an electrostatic discharge (ESD) protection structure, wherein the ESD protection structure includes a resistor and an ESD protection element. The resistor is coupled to the through-hole structure. The ESD protection element is connected in series with the resistor. A second die is coupled to the first die.

[0005] In some embodiments, this disclosure also provides a semiconductor package. The semiconductor package includes a die. The die includes a through-hole structure, an electrostatic discharge (ESD) protection structure, and a barrier structure. The barrier structure perpendicularly surrounds the through-hole structure. The ESD protection structure includes a resistor and an ESD protection element. The resistor is coupled to the through-hole structure. The ESD protection element is connected in series with the resistor. Attached Figure Description

[0006] When with attachment Figure 1 The best way to understand the various aspects of this disclosure is by reading the following detailed description. It should be noted that, in accordance with industry standard practice, the various features may not be drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A cross-sectional view of an exemplary semiconductor package according to some embodiments is schematically shown;

[0008] Figure 2 A cross-sectional view of one embodiment of a semiconductor package including a through substrate via (TSV) is shown according to some embodiments.

[0009] Figure 3 A cross-sectional view of another embodiment of a semiconductor package including one or more substrate through-holes is shown according to some embodiments;

[0010] Figure 4 The cross-sectional view of the semiconductor package illustrates potential electrostatic discharge (ESD) damage;

[0011] Figure 5 This is a cross-sectional view of a semiconductor package including a substrate via and an electrostatic discharge protection structure according to some embodiments;

[0012] Figures 6 to 9 Various electrostatic discharge protection structures according to some embodiments are shown;

[0013] Figure 10 One embodiment illustrates one or more electrostatic discharge protection structures formed in an internal space confined by a substrate via barrier structure in a semiconductor package.

[0014] Figure 11 This is an exemplary flowchart of a method for manufacturing a semiconductor package according to some embodiments;

[0015] Figure 12 One embodiment of a system-on-integrated chip (SoIC) architecture is shown according to some implementation methods.

[0016] [Symbol Explanation]

[0017] 100: Semiconductor Packaging

[0018] 102: First grain

[0019] 104: Second grain

[0020] 105: Intermediate grains

[0021] 106: Relay Structure

[0022] 108: Bump

[0023] 109: Metal Cap

[0024] 110: Packaging substrate

[0025] 112: Conductive connector

[0026] 200: Semiconductor Packaging

[0027] 210: Through-hole structure

[0028] 300: Semiconductor Packaging

[0029] 301: Substrate

[0030] 303: Front

[0031] 305: Back

[0032] 307: Substrate

[0033] 309: Front

[0034] 311: Metallic traces

[0035] 313: Through hole

[0036] 315: Components

[0037] 317: Components

[0038] 319: Microbumps

[0039] 400: Semiconductor Packaging

[0040] 410: Electrostatic charge

[0041] 500: Semiconductor Packaging

[0042] 520: Electrostatic Discharge Protection Structure

[0043] 520A: Electrostatic Discharge Protection Structure

[0044] 520B: Electrostatic Discharge Protection Structure

[0045] 520C: Electrostatic Discharge Protection Structure

[0046] 520D: Electrostatic Discharge Protection Structure

[0047] 530: Resistor

[0048] 540: Electrostatic Discharge Protection Component

[0049] 540A: Complementary Metal-Oxide-Semiconductor Transistor

[0050] 540B: ​​Diode

[0051] 540C: Bipolar Transistor

[0052] 540D: First electrostatic discharge protection element

[0053] 540D': Second electrostatic discharge protection element

[0054] 550: Substrate through-hole barrier structure

[0055] 560: Dielectric section

[0056] 570: Interior Space

[0057] 1000: Semiconductor Packaging

[0058] 1100: Method

[0059] 1102: Operation

[0060] 1104: Operation

[0061] 1106: Operation

[0062] 1108: Operation

[0063] 1200: Integrated System-on-Chip Architecture

[0064] 1202: Top grain

[0065] 1204: Bottom grain

[0066] 1207: Bonding Pads

[0067] 1231: Conductive post

[0068] 1233: Dielectric materials

[0069] A-A': Line

[0070] D: Leakage extreme

[0071] ESD: Electrostatic Discharge Protection Structure

[0072] G: Gate terminal

[0073] PID: Plasma-induced damage

[0074] S: Source Extreme

[0075] TSV: Through-hole in substrate Detailed Implementation

[0076] The following disclosure provides many different implementations or examples for achieving different features of the provided object. Specific examples of elements and compositions are described below to simplify this disclosure. Of course, these are merely examples and are not intended to limit this disclosure. For example, in the following description, the formation of a first feature on or above a second feature may include embodiments where the first and second features are in direct contact, or embodiments where additional features may be formed between the first and second features, preventing direct contact between the first and second features. Furthermore, the reference numerals and / or letters in the figures may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself specify a relationship between the various implementations and / or configurations discussed.

[0077] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “below,” “above,” “top,” “bottom,” etc., to describe the relationship between one element or feature shown in the figure and another element or feature shown in the figure. In addition to the orientations described in the figures, spatial relative terms are also intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative terms used herein will be interpreted accordingly.

[0078] With the further development of semiconductor technology, stacked semiconductor devices, such as three-dimensional (3D) integrated circuits (3DIC or 3D-IC), have become an effective alternative for further reducing the physical size of semiconductor devices. In stacked semiconductor devices, active circuits such as logic, memory, and processor circuits are fabricated on different semiconductor wafers (substrates) to form their respective semiconductor dies. Two or more semiconductor wafers (or dies) can be arranged such that one is placed on top of another to further reduce the external size of the semiconductor device.

[0079] Two or more semiconductor wafers or dies (e.g., bottom die, top die, and intermediate die) can be bonded together using suitable bonding techniques, such as hybrid bonding, microbump bonding, direct bonding, chemically activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermo-compressive bonding, reactive bonding, and / or similar methods. Electrical connections based on a variety of through-hole structures can be provided between the stacked semiconductor dies, where the through-hole structures are, for example, substrate vias (TSVs, e.g., through silicon vias).

[0080] In 3D integrated circuits, through-hole structures, such as through-silicon vias (TSVs) or substrate vias (TSVs), are widely used to transmit power or signals from package pins through the bottom die to the top die, and vice versa. Therefore, by using one or more TSVs, the density of interconnect structures and devices in 3D integrated circuits can be advantageously increased, and the length of interconnect structures can be advantageously shortened. However, during the process of forming TSVs, a large amount of electrostatic charge may be generated and accumulate inside or near the TSVs. When this electrostatic charge is suddenly released, it can cause adverse damage to the devices, components, and interconnect structures formed in the 3D integrated circuit (e.g., in the top and bottom dies). For example, in plasma etching processes, a large amount of electrostatic charge induced by plasma may accumulate inside or near the TSVs, and when it is suddenly released, it may cause so-called plasma-induced damage (PID). Furthermore, electrostatic charges generated and accumulated during the operation or use of 3D integrated circuits can also damage the devices, components, and interconnect structures formed in the 3D integrated circuits due to sudden release. Therefore, there is a great need for a protective electrostatic discharge (ESD) device or mechanism that can effectively release accumulated electrostatic charge and save space.

[0081] This disclosure provides various embodiments of a semiconductor device or package. In some embodiments, the semiconductor package includes a first die and a second die vertically coupled to the first die via a plurality of microbumps. The first die includes a via structure (e.g., a substrate via) and an electrostatic discharge (ESD) protection structure. The ESD protection structure includes a resistor coupled to the substrate via and an ESD protection element connected in series with the resistor. One end of the ESD protection element is grounded. In some embodiments, this ESD protection structure is formed in the first die during the process of forming the substrate via in the first die. By employing such an ESD protection structure in the semiconductor package, electrostatic charges generated during the process of forming the substrate via in the first die or during the operation or use of the semiconductor package can be safely released by the ESD protection structure, thereby advantageously reducing or even preventing damage caused by ESD.

[0082] Figure 1 Cross-sectional views of a semiconductor package (or device) 100 according to various embodiments of this disclosure are shown. In one embodiment, the semiconductor package 100 is sometimes referred to as a three-dimensional integrated circuit (sometimes called a "3D IC") and multiple semiconductor devices (sometimes called "wafers" or "dies") having two or more layers are stacked one on top of the other. It should be understood that the semiconductor package 100 is simplified for illustrative purposes, and the arrangement of the elements of the semiconductor package 100 may be configured in various other ways and / or the semiconductor package 100 may include any other elements, all of which fall within the scope of this disclosure.

[0083] In some embodiments of this disclosure, the semiconductor package 100 includes a first die (e.g., a top die) 102 and a second die (e.g., a bottom die) 104, stacked one on top of the other. The first die 102 and the second die 104 can be electrically bonded together by suitable bonding techniques, such as hybrid bonding, micro bumps, direct bonding, chemically activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermo-compressive bonding, reactive bonding, and / or similar methods.

[0084] In one embodiment of this disclosure, the first die 102 may include multiple active circuits, devices, elements, or loads, such as system-on-chip (SoC) devices, high-bandwidth memory (HBM) devices, etc., while the second die 104 may include one or more passive circuits, devices, and / or loads, such as integrated passive devices, integrated voltage regulators, etc. In another embodiment, the first die 102 may include both active and passive circuits, devices, and / or loads, while the second die 104 may also include both active and passive circuits, devices, and / or loads. In yet another embodiment, the first die 102 may include passive circuits, devices, and / or loads, while the second die 104 may include active circuits, devices, and / or loads.

[0085] In some embodiments, the semiconductor package 100 also includes a redistribution structure 106 connected to the second die 104. It should be understood that... Figure 1 The redistribution structure 106 shown is merely illustrative. The redistribution structure 106 may include numerous redistribution lines (RDLs), such as metal traces (or metal wires), and vias located above or below the metal traces and connected to them; all of these are sometimes referred to as redistribution routes (RDL routes). Such redistribution routes may be shown in one or more of the figures below.

[0086] In some embodiments, the rediform lines of the redistribution structure 106 are formed by a plating process, wherein each rediform line includes a seed layer (not shown) and a metal material deposited on the seed layer. The seed layer can be formed using, for example, physical vapor deposition. A photoresist is then formed on the seed layer and patterned. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the rediform lines. The patterning process forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, for example, by electroplating or electroless plating. The seed layer and the plated metal material can be formed from the same material or different materials. The conductive material can be a metal, such as copper, titanium, tungsten, aluminum, etc. Next, the photoresist and the portion of the seed layer on which no conductive material is formed are removed. The photoresist can be removed by a feasible ashing or stripping process (e.g., using oxygen plasma). After the photoresist is removed, the exposed portion of the seed layer is removed, for example, by a feasible etching process, such as wet and / or dry etching. Thus, the remaining portion of the seed layer and the conductive material form the redistribution of the redistribution structure 106.

[0087] In some embodiments, the semiconductor package 100 further includes a plurality of bumps 108 that connect the redistribution structure 106 (e.g., electrically) to the package substrate 110. The bumps 108 may be metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using the electroless nickel-electroless palladium-immersion gold technique (ENEPIG), ball grid array (BGA) bumps, etc. In one embodiment, the bump 108 is a C4 bump. The bumps 108 may be formed by sputtering, printing, electroplating, electroless plating, chemical vapor deposition, etc. The bumps 108 may be solderless and have substantially vertical sidewalls. In some embodiments, a plurality of metal caps 109 are each formed on top of the bump 108. The metal cap 109 may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like or combinations thereof, and may be formed by a coating process.

[0088] In some embodiments, the package substrate 110 may be, for example, a printed circuit board (PCB) or the like, and may be electrically connected to an intermediate package (e.g., a first die 102 and a second die 104 bonded to a redistribution structure 106) using bumps 108. The package substrate 110 may be made of a semiconductor material, such as silicon, germanium, diamond, etc. Optionally, compound materials, such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, or combinations thereof, may also be used as the semiconductor material for the package substrate 110. Furthermore, the package substrate 110 may be a silicon-on-insulator (SOI) substrate. Typically, a silicon-on-insulator substrate comprises a layer of semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In an alternative embodiment, the package substrate 110 is based on an insulating core, such as a fiberglass-reinforced resin core. In one example, the core material is a glass fiber resin, such as FR4. Alternatives to the core material include bismaleimide-triazine BT resin, or alternatively, other PCB materials or films. Build-up films, such as ABF or other laminates, may also be used for the encapsulation substrate 110.

[0089] In some embodiments, the package substrate 110 may include a metallization layer and vias, as well as pads on the metallization layer and vias. The metallization layer is intended to connect various devices to form functional circuitry, which is sometimes referred to as a package route. The metallization layer may be formed by alternating layers of dielectric (e.g., a low-k dielectric material) and conductive material (e.g., copper), with vias connecting the conductive material layers to each other, and the metallization layer may be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.). Such package routes may be illustrated in one or more of the figures below.

[0090] In some embodiments, the semiconductor package 100 further includes a plurality of conductive connectors 112 disposed on the side of the package substrate 110 opposite to the side facing the redistribution structure 106, such as Figure 1As shown. The conductive connector 112 can be formed of a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. In some embodiments, the conductive connector 112 is first formed with a solder layer by methods such as evaporation, electroplating, printing, solder transfer, or ball placement. Once the solder layer is structurally formed, reflow can be performed to shape the conductive connector 112 into the desired bump shape. In some embodiments, this conductive connector 112 can serve as a package pin of a semiconductor package 100 configured to receive one or more power supply voltages.

[0091] Figure 2 A cross-sectional view of one embodiment of a semiconductor package 200 is shown according to some embodiments, wherein the semiconductor package 200 includes one or more through-hole structures (or TSVs) 210. The semiconductor package 200 includes a plurality of dies stacked one on top of another and one or more through-hole structures 210. It should be understood that the semiconductor package 200 is simplified for illustrative purposes, and the number of dies stacked one on top of another may be greater than two and falls within the scope of this disclosure.

[0092] In some implementations, such as Figure 2 As shown, the semiconductor package 200 includes a first die 102, an intermediate die 105, and a second die 104 bonded together. The first die 102 is stacked on the intermediate die 105, and the intermediate die 105 is stacked on the second die 104. The first die 102 is bonded to the intermediate die 105 via microbumps (not shown), and the intermediate die 105 is bonded to the second die 104 via microbumps (not shown). The second die 104 is stacked on and coupled to a package substrate 110. In some embodiments, the package substrate 110 is a printed circuit board (PCB) and includes a plurality of conductive connectors 112 configured to couple to other devices. In some embodiments, the conductive connectors 112 include metal solder balls made of a metal or metal alloy material (e.g., tin, copper, brass, or silver).

[0093] In some embodiments, the via structure 210 extends vertically through the entire die. In other embodiments, the via structure 210 extends vertically through a large portion of the entire die. In other embodiments, the via structure 210 extends vertically through the substrate of the die. Typically, the via structure 210 has a high depth-to-diameter aspect ratio. In some embodiments, the aspect ratio of the via structure 210 is from about 8:1 to about 20:1, while in other embodiments, the aspect ratio of the via structure 210 is from about 12:1 to about 16:1. The via structure 210 can be used together with other routing elements (e.g., interconnecting metal traces and vias) as a power rail or signal rail to transmit power or signals from one die (e.g., second die 104) to another die (e.g., intermediate die 105) and vice versa.

[0094] Figure 3 A cross-sectional view of another embodiment of a semiconductor package 300 is shown according to some embodiments, wherein the semiconductor package 300 includes one or more TSVs. The semiconductor package 300 includes a first die (e.g., a top die) 102 and a second die (e.g., a bottom die) 104 stacked one on top of the other. In some embodiments, the first die 102 is flipped and bonded face-to-face to the second die 104. In some embodiments, the first die 102 and the second die 104 may be bonded together (e.g., electrically) via microbumps 319. In other embodiments, the first die 102 and the second die 104 may be bonded together (e.g., electrically) via using a hybrid bonding method such as through-hole bonding and bonding pad metal (not shown) without using microbumps. In other embodiments, the first grain 102 and the second grain 104 can be bonded together (e.g., electrically) using other suitable bonding techniques, such as direct bonding, chemically activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermo-compressive bonding, reactive bonding, and / or similar techniques (not shown). In some embodiments, such as Figure 3The semiconductor package 300 shown can be implemented as a System-on-a-Chip (SoIC). A System-on-a-Chip refers to a chip that integrates an entire system or subsystem onto a single integrated circuit. Further details on System-on-a-Chip will be available in [reference needed]. Figure 12 Describe it.

[0095] In some implementations, such as Figure 3 As shown, the first die 102 includes a substrate 301, a front side 303, a back side 305, a via structure 210, multiple interconnect structures (e.g., metal traces 311 and vias 313), and one or more semiconductor devices or elements (e.g., complementary metal oxide semiconductor (CMOS) transistors) 315. Similarly, the second die 104 includes a substrate 307 (e.g., a silicon substrate), a front side 309, multiple interconnect structures (e.g., metal traces 311 and vias 313), and one or more semiconductor devices or elements (e.g., complementary metal oxide semiconductor transistors) 317. In some embodiments, the via structure 210 may extend through a large portion of the first die 102 (e.g., the substrate 301 and the front side 303). In other embodiments, the via structure 210 may extend completely through the first die 102. In some embodiments, the via structure 210 functions to transmit power, and in other embodiments, the via structure 210 functions to transmit signals.

[0096] Figure 4 This is a cross-sectional view of a semiconductor package 400 including one or more through-hole structures 210, illustrating potential damage caused by electrostatic discharge (ESD). Semiconductor package 400 is similar to semiconductor package 300. In various cases, electrostatic charge 410 can be generated and accumulate in or near the through-hole structure 210 in semiconductor package 400. For example, in certain processes forming the through-hole structure 210, electrostatic charge 410 can be generated and accumulate in or near the through-hole structure 210. For example, in a plasma etching process forming the through-hole structure 210, plasma-induced electrostatic charge 410 can be generated and accumulate in or near the through-hole structure 210. Furthermore, during the operation of semiconductor package 400, electrostatic charge 410 may also be generated and accumulate in or near the through-hole structure 210. Figure 4 As shown, when the electrostatic charge 410 is suddenly released, the electrostatic charge 410 accumulated in or near the via structure 210 can damage (e.g., burn out) devices, components, and interconnects connected to or near the via structure 210. Therefore, there is a great need for a space-friendly and protective electrostatic discharge (ESD) device that can effectively release accumulated electrostatic charge.

[0097] Figure 5This is a cross-sectional view of a semiconductor package 500 including at least one through-hole structure 210 and at least one electrostatic discharge protection structure 520 according to some embodiments. It should be understood that the semiconductor package 500 is simplified for illustrative purposes, and therefore the arrangement of the components of the semiconductor package 500 can be configured in various other ways and / or the semiconductor package 500 can include any other components, all of which fall within the scope of this disclosure.

[0098] In some embodiments, the semiconductor package 500 includes a first die 102 and a second die 104 vertically coupled to the first die 102 via a plurality of microbumps 319. In some embodiments, such as Figure 5 As shown, the first die 102 is flipped, and the front side 303 of the first die 102 is coupled to the front side 309 of the second die 104 via a plurality of microbumps 319 (so-called face-to-face connection). In other embodiments (not shown), the first die 102 is not flipped, and the back side 305 of the first die 102 is coupled to the front side 309 of the second die 104 via a plurality of microbumps 319 (so-called back-to-face connection).

[0099] In some implementations, such as Figure 5 As shown, the first die 102 includes at least one via structure (e.g., TSV) 210 and an electrostatic discharge (ESD) protection structure 520. The via structure 210 is made of a metallic material (e.g., copper). In some embodiments, the via structure 210 serves as a power rail, while in other embodiments, it serves as a signal rail. In some embodiments, the ESD protection structure 520 includes a resistor 530 and an ESD protection element 540. The resistor 530 is coupled to the via structure 210 through one or more interconnect structures in the first die 102 (e.g., metal traces 311 and / or vias 313). The ESD protection element 540 is connected in series with the resistor 530. In some embodiments, a first end of the ESD protection element 540 is connected in series with the resistor 530, and a second end of the ESD protection element 540 is grounded. In some embodiments, the second end of the ESD protection element 540 is connected in series with the substrate 301 of the first die 102. The electrostatic discharge protection structure 520 can be formed in the manufacturing process that forms the through-hole structure 210.

[0100] As described above, during the process of forming the via structure 210 (e.g., plasma etching) or during the operation or use of the semiconductor package 500, a large amount of electrostatic charge may be generated and accumulated in or near the via structure 210. When this electrostatic charge is suddenly released, it may damage devices, components, and interconnect structures connected to or near the via structure 210 in the semiconductor package 500. By using this electrostatic discharge protection structure 520 in the semiconductor package 500, the electrostatic charge generated and accumulated in or near the via structure 210 can be safely released, thereby advantageously reducing the possibility of damage caused by electrostatic discharge. Various embodiments of the electrostatic discharge protection structure 520 may be implemented, and will be referred to... Figures 6 to 9 To explain in more detail.

[0101] Figure 6 An example of an electrostatic discharge (ESD) protection structure 520A according to some embodiments is shown. In some embodiments, the ESD protection structure 520A includes a resistor 530 (formed in a metallization layer) and a complementary metal-oxide-semiconductor (CMOS) transistor 540A (formed in another metallization layer) serving as an ESD protection element. In some embodiments, the CMOS transistor 540A is an N-type CMOS transistor, while in other embodiments, the CMOS transistor 540A is a P-type CMOS transistor. The resistor 530 is coupled to a via structure 210 using metal wires and / or metal vias (not shown). The CMOS transistor 540A is connected in series with the resistor 530 using metal wires and / or metal vias (not shown). In some embodiments, the drain terminal D of the complementary metal-oxide-semiconductor transistor 540A is connected in series to a resistor 530 using metal lines and / or metal vias (not shown), and the source terminal S and gate terminal G of the complementary metal-oxide-semiconductor transistor 540A are grounded using metal lines and / or metal vias (not shown). In some embodiments, the source terminal and gate terminal of the complementary metal-oxide-semiconductor transistor 540A may be coupled to the substrate 301 of the first die 102 (e.g., Figure 5 (As shown). The electrostatic discharge protection structure 520A can be formed in the manufacturing process that forms the through-hole structure 210.

[0102] Figure 7 Another example of an electrostatic discharge protection structure 520B according to some embodiments is shown. Electrostatic discharge protection structure 520B and... Figure 6Similar to the electrostatic discharge protection structure 520A, but with some differences. In some embodiments, the electrostatic discharge protection structure 520B includes a resistor 530 (formed in a metallization layer) and a diode 540B (formed in another metallization layer) serving as an electrostatic discharge protection element. The resistor 530 is coupled to a via structure 210 via some metal wires and / or metal vias (not shown). The diode 540B is connected in series to the resistor 530 via other metal wires and / or metal vias (not shown). In some embodiments, the cathode of the diode 540B is connected in series to the resistor 530, and the anode of the diode 540B is grounded. In some embodiments, the cathode of the diode 540B may be coupled to the substrate 301 of the first die 102 (e.g., Figure 5 (As shown).

[0103] Figure 8 Another example of an electrostatic discharge protection structure 520C according to yet another embodiment is shown. Electrostatic discharge protection structure 520C and... Figure 6 Similar to the electrostatic discharge protection structure 520A, but with some differences. In some embodiments, the electrostatic discharge protection structure 520C includes a resistor 530 (formed in a metallization layer) and a bipolar junction transistor (BJT) 540C (formed in another metallization layer) serving as an electrostatic discharge protection element. The resistor 530 is coupled to a via structure 210 using some metal wires and / or metal vias (not shown). The bipolar transistor 540C is connected in series to the resistor 530 using other metal wires and / or metal vias (not shown). In some embodiments, the collector terminal of the bipolar transistor 540C is connected in series to the resistor 530, and the base and emitter terminals of the bipolar transistor 540C are grounded. In some embodiments, the base and emitter terminals of the bipolar transistor 540C may be coupled to the substrate 301 of the first die 102 (e.g., Figure 5 (As shown).

[0104] Figure 9 Another example of an electrostatic discharge protection structure 520D according to some embodiments is shown. The electrostatic discharge protection structure 520D and... Figure 6Similar to the electrostatic discharge protection structure 520A, but with some differences. In some embodiments, the electrostatic discharge protection structure 520D includes a resistor 530, a first electrostatic discharge protection element 540D, and a second electrostatic discharge protection element 540D' connected in series. Each of the first electrostatic discharge protection element 540D and the second electrostatic discharge protection element 540D' can be a complementary metal-oxide-semiconductor transistor, a diode, or a bipolar transistor, etc. The resistor 530 is coupled to the through-hole structure 210. The first electrostatic discharge protection element 540D is coupled to the resistor 530, is connected in series between the resistor 530 and the second electrostatic discharge protection element 540D', and one end of the second electrostatic discharge protection element 540D' is grounded. In some embodiments, one end of the second electrostatic discharge protection element 540D' can be coupled to the substrate 301 of the first die 102 (e.g., Figure 5 (As shown) to perform grounding.

[0105] It should be understood that the number of electrostatic discharge protection elements (e.g., electrostatic discharge protection element 540) in the electrostatic discharge protection structure 520D is not limited to... Figure 9 The number of electrostatic discharge (ESD) protection elements is two, but can be more than two (e.g., three, four, or even more). The number of ESD protection elements is designed or configured based on the estimated scale or quantity of electrostatic charge that may be generated and accumulated inside or near the substrate vias. The larger the estimated scale or quantity of electrostatic charge generated and accumulated inside or near the substrate vias, the more ESD protection elements need to be designed or configured.

[0106] Figure 10 This is a cross-sectional view of a semiconductor package 1000 including a substrate through-hole barrier structure 550 according to some embodiments (the portion on the right is a view cut along line A-A' of the structure in the left image). Semiconductor package 1000 and Figure 5 Similar to the semiconductor package 500, but with some differences, such as including a substrate via barrier structure 550. The semiconductor package 1000 includes a first die 102 and a second die 104 vertically coupled to the first die 102 via a plurality of microbumps 319. The first die 102 includes a via structure 210, an electrostatic discharge protection structure 520, and a substrate via barrier structure 550. The substrate via barrier structure 550 is made of a semiconductor material (e.g., silicon) and serves to reduce or prevent the adverse effects of the via structure 210 on nearby devices and components.

[0107] like Figure 10As shown, the substrate via barrier structure 550 extends vertically to the dielectric portion 560 of the first die 102 and laterally surrounds the via structure 210. The dielectric portion 560 is made of a dielectric material (e.g., silicon oxide, silicon nitride, etc.) and contains no other devices or components. Therefore, an internal space 570 within the dielectric portion 560 of the first die 102, containing no other devices or components, can be defined or confined between the substrate via barrier structure 550 and the via structure 210. In some embodiments, the substrate via barrier structure 550 extends vertically through the entire die of the first die 102. In other embodiments, the substrate via barrier structure 550 extends vertically to the first die 102 at a considerable depth. In yet another embodiment, the substrate via barrier structure 550 extends vertically through the substrate of the first die 102. In some embodiments, the depth to which the substrate via barrier structure 550 extends vertically in the dielectric portion 560 of the first die 102 is equal to or greater than the depth to which the via structure 210 extends vertically in the dielectric portion 560 of the first die 102.

[0108] In some embodiments, a single electrostatic discharge protection structure 520 is formed within the internal space 570 of the dielectric portion 560 of the first die 102. See also Figure 5 The electrostatic discharge (ESD) protection structure 520 includes a resistor 530 and an ESD protection element 540. The resistor 530 is coupled to the via structure 210, one end of the ESD protection element 540 is coupled to the resistor 530, and the other end of the ESD protection element 540 is grounded. In other embodiments, a plurality of ESD protection structures 520 are formed in the internal space 570 of the dielectric portion 560 of the first die 102. In each ESD protection structure 520, the resistor 530 is coupled to the via structure 210, one end of each ESD protection element 540 is connected in series with the resistor 530, and the other end of each ESD protection element 540 is grounded.

[0109] Figure 11 Manufacturing according to some implementation methods Figure 5 An exemplary flowchart of method 1100 for semiconductor packaging 500 is provided. It should be noted that method 1100 is merely an example and is not intended to limit the scope of this disclosure. Therefore, it can be understood that... Figure 11 The operation order of method 1100 can be changed, and can be... Figure 11 Additional operations are provided before, during, and after method 1100, and some other operations are only briefly described here.

[0110] The semiconductor package 500 manufactured by method 1100 may include at least a first (e.g., top) die 102 and a second (e.g., bottom) die 104, and they are operationally and physically coupled to each other. For example, the semiconductor package may include the above-described... Figures 5 to 10 One of the semiconductor packages discussed. Therefore, the operation of method 1100 will be related to... Figures 5 to 10 Let's discuss the components we've already discussed together.

[0111] refer to Figure 5 and Figure 11 Method 1100 begins with operation 1102, which provides a first die (e.g., first die 102) comprising a first substrate (e.g., substrate 301). For example, the first substrate or substrate 301 may be made of a semiconductor material, such as silicon, germanium, diamond, etc. Alternatively, compounds such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, etc., or combinations thereof, may be used. Furthermore, the first substrate or substrate 301 may be a silicon-on-insulator (SOI) substrate. Typically, a SOI substrate comprises a layer of semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof.

[0112] Next, refer to Figure 5 and Figure 11 Method 1100 continues to operation 1104, forming one or more via structures (or substrate vias) 210 extending through the substrate 301 of the first die 102. For example, one or more via structures 210 are formed and extend through the substrate 301 of the first die 102. Specifically, the via structure 210 can be formed by semiconductor manufacturing processes, such as lithography, etching, metal filling, and chemical mechanical polishing (CMP) processes. During the process of forming the via structure 210, electrostatic charges can be generated and accumulated inside or near the via structure 210, thus posing a potential hazard to devices or components located near or connected to the via structure 210.

[0113] Next, refer to Figure 5 and Figure 11Method 1100 continues to operation 1106, forming an electrostatic discharge (ESD) protection structure in the first die. For example, an ESD protection structure 520 including a resistor 530 (deposited in a metallization layer) and an ESD protection element 540 (deposited in another metallization layer) is formed in the first die 102. Specifically, the resistor 530 is coupled to the via structure 210 using some metal wires and / or metal vias (not shown), a first end of the ESD protection element 540 is coupled to the resistor 530 using some metal wires and / or metal vias (not shown), and a second end of the ESD protection element 540 is grounded using some metal wires and / or metal vias (not shown). In some embodiments, the second end of the ESD protection element 540 is coupled to the substrate 301 of the first die 102. In some embodiments, operation 1106 of forming the ESD protection structure 520 is performed simultaneously with operation 1104 of forming the via structure 210 or before operation 1104. Therefore, electrostatic charges accumulated during the process of forming the via structure 210 or during the operation of the semiconductor package 500 can be safely released through the electrostatic discharge protection structure 520, which is embedded in the semiconductor package 500 without requiring Vdd and Vss processing, thereby advantageously reducing the potential damage that electrostatic discharge may cause in a power and space-efficient manner.

[0114] Next, refer to Figure 5 and Figure 11 Method 1100 continues to operation 1108, where the first die is connected to the second die to couple the first die to the second die. For example, the first die 102 is connected and coupled to the second die 104. In some embodiments, the first die 102 is flipped and coupled to the second die 104 via a plurality of microbumps 319.

[0115] Figure 12 One embodiment of an integrated system-on-a-chip (SoIC) architecture 1200 is illustrated according to some implementations. In some embodiments, a semiconductor package can be used as the SoIC for implementation. SoIC refers to a chip that integrates an entire system or subsystem onto a single integrated circuit. SoICs typically include not only the main processing unit but also memory, input / output interfaces, and other components required to perform specific functions, and are commonly used in applications where space and power efficiency are critical, such as Internet of Things (IoT) devices, wearable electronics, and embedded systems. In some embodiments, such as Figure 12As shown, the integrated system-on-a-chip (SoC) 1200 includes a bottom die 1204, one or more top dies 1202 connected to the front side of the bottom die 1204, conductive pillars 1231 located on the front side of the bottom die 1204, and a dielectric material 1233. The number of top dies 1202 attached to the bottom die 1204 and the structure of the SoC 1200 can be changed to have different structures, details of which will be discussed below. Figure 11 In the example, the integrated system-on-a-chip (SoC) 1200 includes two top dies 1202 and one bottom die 1204, wherein the back side of the top dies 1202 is attached to the front side of the bottom die 1204. Therefore, this SoC 1200 is also referred to as having back-to-back bonding, or back-to-back SoIC. Conductive posts 1231 are formed on bonding pads 1207.

[0116] Some embodiments of this disclosure provide a semiconductor package. The semiconductor package includes a first die. The first die includes a through-via structure and an electrostatic discharge (ESD) protection structure, wherein the ESD protection structure includes a resistor and an ESD protection element. The resistor is coupled to the through-via structure. The ESD protection element is connected in series with the resistor, wherein one end of the ESD protection element is coupled to a substrate of the first die. In some embodiments, the semiconductor package further includes a second die vertically coupled to the first die via a plurality of micro-bumps. In some embodiments, the ESD protection element includes a complementary metal-oxide-semiconductor (CMOS) transistor, wherein a first source / drain terminal of the CMOS transistor is coupled to the resistor, and the gate terminal and the second source / drain terminal of the CMOS transistor are grounded. In some embodiments, the ESD protection element includes a diode, wherein the cathode terminal of the diode is coupled to the resistor, and the anode terminal of the diode is grounded. In some embodiments, the electrostatic discharge (ESD) protection element includes a bipolar junction transistor (BJT), wherein the collector terminal of the BJT is coupled to a resistor, and the base and emitter terminals of the BJT are grounded. In some embodiments, the first die includes one or more first load circuits. In some embodiments, the first die also includes a via barrier surrounding the via structure to separate the via structure from the first load circuit. In some embodiments, the second die includes one or more second load circuits. In some embodiments, the ESD protection structure further includes another ESD protection element coupled between the resistor and the ESD protection element. In some embodiments, the other ESD protection element is selected from the group consisting of complementary metal-oxide-semiconductor (CMOS) transistors, diodes, and bipolar transistors.

[0117] Some embodiments of this disclosure also provide a semiconductor package. The semiconductor package includes a first die. The first die includes a via structure and an electrostatic discharge (ESD) protection structure, wherein the ESD protection structure includes a resistor and an ESD protection element. The resistor is coupled to the via structure. The ESD protection element is connected in series with the resistor. A second die is coupled to the first die. In some embodiments, the second die is vertically coupled to the first die via a plurality of microbumps. In some embodiments, the ESD protection structure further includes another ESD protection element connected in series between the resistor and the ESD protection element. In some embodiments, the first die also includes a barrier structure vertically surrounding the via structure. In some embodiments, the ESD protection structure is deposited in a space defined between the via structure and the barrier structure. In some embodiments, the ESD protection structure is in a space defined between the via structure and the barrier structure. In some embodiments, one end of the ESD protection element is grounded.

[0118] Some embodiments of this disclosure also provide a method for forming a semiconductor package. The method includes the following operations: providing a first die including a first substrate; forming a through-hole structure extending through the first substrate of the first die; forming an electrostatic discharge (ESD) protection structure in the first die, wherein the ESD protection structure includes a resistor coupled to the through-hole structure and an ESD protection element connected in series to the resistor; connecting the first die to a second die. In some embodiments, the first die and the second die are vertically coupled together by a plurality of microbumps. In some embodiments, the ESD protection structure further includes another ESD protection element connected in series between the resistor and the ESD protection element. In some embodiments, one end of the ESD protection element is grounded.

[0119] Some embodiments of this disclosure provide a semiconductor package. The semiconductor package includes a die. The die includes a through-hole structure, an electrostatic discharge (ESD) protection structure, and a barrier structure. The barrier structure perpendicularly surrounds the through-hole structure. The ESD protection structure includes a resistor and an ESD protection element. The resistor is coupled to the through-hole structure. The ESD protection element is connected in series with the resistor.

[0120] As used herein, “approximately” and “about” generally refer to plus or minus 10% of the value. For example, approximately 0.5 includes 0.45 and 0.55, approximately 10 includes 9 to 11, and approximately 1000 includes 900 to 1100.

[0121] The foregoing outlines some features of the embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from its spirit and scope.

Claims

1. A semiconductor package, characterized by, include: A first grain includes a through-hole structure and an electrostatic discharge (ESD) protection structure, wherein the ESD protection structure includes: A resistor is coupled to the via structure; as well as An electrostatic discharge protection element is connected in series with the resistor, wherein one end of the electrostatic discharge protection element is coupled to a substrate of the first die.

2. The semiconductor package of claim 1, wherein, The electrostatic discharge protection element includes a complementary metal-oxide-semiconductor transistor (CMOS), wherein a first source / drain terminal of the CMOS transistor is coupled to the resistor, and a gate terminal and a second source / drain terminal of the CMOS transistor are grounded.

3. The semiconductor package of claim 1, wherein, The electrostatic discharge protection element includes a diode, wherein one cathode of the diode is coupled to the resistor, and one anode of the diode is grounded.

4. The semiconductor package of claim 1, wherein, The electrostatic discharge protection element includes a bipolar transistor, wherein one base terminal of the bipolar transistor is coupled to the resistor, and one base terminal and one emitter terminal of the bipolar transistor are grounded.

5. A semiconductor package, characterized by, include: A first grain includes a through-hole structure and an electrostatic discharge (ESD) protection structure, wherein the ESD protection structure includes: A resistor is coupled to the via structure; and An electrostatic discharge protection element is connected in series with the resistor; and A second grain is coupled to the first grain.

6. The semiconductor package of claim 5, wherein, The second grain is vertically coupled to the first grain through multiple microbumps.

7. The semiconductor package of claim 5, wherein the semiconductor package is a flip chip semiconductor package. The electrostatic discharge protection structure also includes another electrostatic discharge protection element connected in series between the resistor and the electrostatic discharge protection element.

8. The semiconductor package as described in any one of claims 5 to 7, characterized in that, The first grain also includes a barrier structure that vertically surrounds the through-hole structure.

9. The semiconductor package of claim 8, wherein the semiconductor package is a flip chip semiconductor package. The electrostatic discharge protection structure is located in a space defined between the through-hole structure and the barrier structure.

10. A semiconductor package, characterized by, include: A grain includes a through-hole structure, an electrostatic discharge (ESD) protection structure, and a barrier structure, the barrier structure perpendicularly surrounding the through-hole structure, wherein the ESD protection structure includes: A resistor is coupled to the via structure; as well as An electrostatic discharge protection element is connected in series with the resistor.

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