SoC array server case

Abstract

The utility model discloses an SoC (System on Chip) array server chassis. The SoC array server case comprises a case body, a backboard, a mainboard, a BMC control board, an exchange board, a power module and a carrier board framework, the backboard, the mainboard, the BMC control board, the exchange board, the backboard and the power module are detachably arranged in the case body, the mainboard serves as a core interconnection assembly of a server and is connected with the BMC control board, the exchange board, the backboard and the power module, and the carrier board framework is connected into the mainboard through the backboard. The carrier plate framework further comprises a carrier plate and a plurality of SoC calculation modules, and a calculation unit and a storage unit in each SoC calculation module are detachably connected with a bottom plate on the carrier plate through interfaces. Therefore, according to the technical scheme, the backboard, the mainboard, the BMC control board, the exchange board, the power supply module and the carrier board framework in the box body or the computing unit and the storage unit on the carrier board all adopt modular design, maintenance and upgrading are facilitated, stable operation of the system is ensured, all the modules are connected through high-bandwidth interfaces, high-speed data transmission is achieved, and the data transmission efficiency is improved. The overall performance is improved.

Description

Technical Field

[0001] This application relates to the field of SoC array server technology, and in particular to a SoC array server chassis. Background Technology

[0002] With the rapid development of cloud computing, edge computing, artificial intelligence, and high-performance computing (HPC), server systems are facing higher demands for computing density, resource elasticity, maintainability, and energy efficiency. Traditional server chassis designs, employing integrated or semi-modular architectures, suffer from the following technical bottlenecks:

[0003] The hardware is highly coupled, limiting scalability. Existing servers typically permanently integrate computing units such as CPUs / GPUs / NPUs with components like motherboards, memory, and storage, preventing users from dynamically adjusting computing power types based on business needs (e.g., switching from CPU-intensive to GPU-accelerated). The upgrade cycles for different modules (e.g., computing units, storage units, network units) are inconsistent, but due to the integrated design, the entire hardware must be replaced, resulting in wasted resources (e.g., upgrading only the GPU requires scrapping the entire server).

[0004] Therefore, it is necessary to improve the existing SoC array server chassis. Utility Model Content

[0005] This application provides a SoC array server chassis, which aims to solve the problems of strong hardware coupling, limited scalability, and inability to adapt to the needs of technological development in existing SoC array server chassis.

[0006] To achieve the above objectives, this application proposes a SoC array server chassis. The SoC array server chassis includes a chassis and a backplane, motherboard, BMC control board, switching board, power module, and carrier board architecture detachably disposed within the chassis. The backplane is located near the center of the chassis to divide the chassis into a first cavity and a second cavity. The motherboard, BMC control board, switching board, and power module are all disposed within the second cavity, and the BMC control board, switching board, power module, and backplane are all electrically connected to the motherboard via a custom PCIe interface. Multiple carrier board architectures are arranged in an array within the first cavity.

[0007] The carrier board architecture includes a carrier board and multiple SoC computing modules. A baseboard is detachably mounted on the carrier board, and the baseboard is electrically connected to the backplane via a custom PCIe interface to access the motherboard. The SoC computing modules are mounted on the baseboard, and each SoC computing module includes a computing unit and a storage unit. The baseboard is provided with a plug-in interface for each SoC computing module, so that the computing unit and the storage unit are detachably connected to the baseboard, and the computing unit in each SoC computing module accesses the storage unit through the baseboard.

[0008] In some embodiments, a PCIe interface is provided on the base plate corresponding to the computing unit, and an M.2 interface is provided on the base plate corresponding to the storage unit.

[0009] In some embodiments, the base plate is a double-sided circuit board, and the SoC computing module is disposed on both opposite sides of the base plate.

[0010] In some embodiments, the computing unit is a SoC computing core board, and the storage unit includes an SSD and an HDD.

[0011] In some embodiments, each of the SoC computing modules further includes a heat sink attached to the computing unit, the heat sink comprising a plurality of spaced-apart heat sink fins.

[0012] In some embodiments, the carrier board is pulled out and connected to the chassis; it includes a pull-out head and side plates extending opposite to each other on both sides of the pull-out head, a base plate is disposed between the two side plates, and SoC computing modules on the base plate are arranged at intervals along the extending direction of the side plates;

[0013] The base plate has a connector on the side away from the pull-out head, and the connector corresponds to the PCIe slot in the back plate.

[0014] In some embodiments, the end of the pull-out head is provided with a ventilation hole, and the end of the chassis opposite to the pull-out head is provided with a ventilation mesh; and the SoC array server chassis also includes a plurality of cooling fans, which are connected to the motherboard and are linearly distributed along the extension direction of the backplane, for forming air convection between the ventilation hole and the ventilation mesh to cool and dissipate heat from the carrier board architecture.

[0015] The gaps between the multiple heat sinks form air ducts, and the extension direction of the air ducts is the same as the airflow direction.

[0016] In some embodiments, the base plate is disposed opposite to the center of the carrier board so that the installed SoC computing module does not exceed the overall thickness range of the carrier board.

[0017] In some embodiments, the two oppositely arranged side plates extend to form a support plate, the support plate is provided with a positioning post and a first locking hole, and the bottom plate is provided with a positioning hole corresponding to the positioning post and a second locking hole corresponding to the first locking hole.

[0018] In some embodiments, the number of power modules is set to two, and each power module is hot-swappably connected to the motherboard, so that one of the power modules can serve as a backup power supply when one of the power modules fails.

[0019] This application proposes a SoC array server chassis. The SoC array server chassis includes a chassis and a backplane, motherboard, BMC control board, switching board, power module, and carrier board architecture detachably disposed within the chassis. The motherboard serves as the core interconnect component of the server, connecting the BMC control board, switching board, backplane, and power module. The carrier board architecture is connected to the motherboard via the backplane. The carrier board architecture further includes a carrier board and multiple SoC computing modules. The computing units and storage units within each SoC computing module are detachably connected to the baseboard on the carrier board via interfaces. Therefore, this application's technical solution employs a modular design for all components, including the backplane, motherboard, BMC control board, switching board, power module, and carrier board architecture within the chassis, as well as the computing and storage units on the carrier board. This facilitates maintenance and upgrades, ensures stable system operation, and allows for high-speed data transmission between modules via high-bandwidth interfaces, thereby improving overall performance. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0021] Figure 1 This is a schematic diagram of the structure of a SoC array server chassis after removing the cover plate according to an embodiment of this application;

[0022] Figure 2 This is a schematic diagram of the assembly structure of a carrier board architecture according to an embodiment of this application;

[0023] Figure 3 This is an exploded structural diagram of a carrier board architecture according to an embodiment of this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0025] It should be noted that, unless otherwise stated or limited, all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0026] It should also be noted that, unless otherwise stated or limited, when an element is referred to as being "fixed to" or "set on" another element, it may be directly on the other element or there may be an intervening element present. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intervening element present.

[0027] Furthermore, unless otherwise stated or limited, the descriptions involving "first," "second," etc., in this application are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0028] See Figures 1-3 As shown, this application proposes a SoC array server chassis 100. The SoC array server chassis 100 includes a chassis 10 and a backplane 20, a motherboard 30, a BMC control board 40, a switching board 50, a power module 60, and a carrier board architecture 70, which are detachably disposed within the chassis 10. The backplane 20 is disposed near the middle of the chassis 10 to divide the chassis 10 into a first cavity and a second cavity. The motherboard 30, BMC control board 40, switching board 50, and power module 60 are all disposed in the second cavity, and the BMC control board 40, switching board 50, power module 60, and backplane 20 are all electrically connected to the motherboard 30 through a custom PCIe interface. The number of carrier board architectures 70 is provided, and the multiple carrier board architectures 70 are arranged in an array within the first cavity.

[0029] Specifically, a custom PCIe x4 interconnect between the BMC control board 40 and the motherboard 30 enables remote management, device monitoring, and system maintenance, ensuring efficient system management functions through this interconnection. The switch board 50 connects to the motherboard 30 via custom dual PCIe x16 ports and provides two 10 Gigabit Ethernet ports for high-bandwidth external network communication, protecting the efficient connection and network data transmission capabilities between the switch board 50 and the motherboard 30. The backplane 20 connects to the motherboard 30 via a custom PCIe x4 port and provides a stable data channel for the carrier boards 71, ensuring the stable operation of multiple carrier boards 71 ​​within the server and supporting efficient data transmission. The power supply module 60 preferably uses dual 1300W power supplies, each hot-swappable to the motherboard 30. This allows one power supply module to act as a backup in case of a failure, ensuring stable system operation. A small fan can be further configured to cool the power supply module 60. The motherboard 30, as the core interconnect component of the server, connects the BMC control board 40, the switching board 50, the backplane 20, and the power module 60. Through this interconnection, the backplane 20 further provides power to the carrier architectures 70, enabling each carrier architecture 701 to independently and stably obtain the required power, avoiding the complexity of distributed power supply. Each carrier architecture 70 is connected to the backplane 20 via a custom PCIe x4 interface, and each carrier architecture 70 implements distributed processing of computing tasks.

[0030] As is understandable, PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard that provides extremely high data transfer rates and low latency, making it suitable for connecting high-performance computing units. High-speed data transfer between modules meets the demands of high-performance computing. Furthermore, a custom PCIe bus architecture reduces data transfer latency, ensuring efficient data exchange, making it suitable for high-performance computing and big data analytics.

[0031] Furthermore, the interconnection of various modules through standardized interfaces protects the scalability of the server architecture, while the independence and easy replacement of each module enhance the system's flexibility and maintainability.

[0032] In terms of overall layout, the backplate 20 divides the enclosure 10 into a first cavity (computing area) and a second cavity (management area), ensuring functional independence between the computing and management areas, improving overall system stability and heat dissipation efficiency, and optimizing server performance. Furthermore, the partitioned design enables efficient resource allocation to meet diverse computing needs. The backplate 20, motherboard 30, BMC control board 40, and switching board 50 are all electrically connected to the enclosure 10 via interfaces and secured with screws, ensuring structural stability while allowing for detachable connections.

[0033] Furthermore, the carrier architecture 70 includes a carrier board 71 and multiple SoC computing modules 72. A baseboard 73 is detachably mounted on the carrier board 71, and the baseboard 73 is electrically connected to the backplane 20 via a custom PCIe interface. The SoC computing modules 72 are mounted on the baseboard 73, and each SoC computing module 72 includes a computing unit (not shown in the figures) and a storage unit (not shown in the figures). The baseboard 73 is provided with a plug-in interface 731 corresponding to each SoC computing module 72, allowing the computing unit and storage unit to be detachably connected to the baseboard 73. The computing unit in each SoC computing module 72 accesses the storage unit through the baseboard 73. The carrier board 71 serves as the basic support platform for the entire architecture, with the baseboard 73 detachably mounted on it, facilitating the replacement and upgrade of the baseboard 73. The baseboard 73 serves as the mounting platform for the SoC computing modules 72, providing electrical connection interfaces with the computing unit and storage unit. Different plug-in interfaces 731 are provided on the baseboard 73 corresponding to the computing unit and storage unit to achieve independent detachable connection of the computing unit and storage unit. Each SoC computing module 72 includes a computing unit and a storage unit. The computing unit is responsible for data processing, and the storage unit is responsible for data storage. Each SoC computing module 72 can be independently installed on the baseboard 73 and communicate with the backplane 20 through the baseboard 73.

[0034] In summary, the technical solution of this application adopts a modular design for all components, including the backplane 20, motherboard 30, BMC control board 40, switching board 50, power module 60, and carrier board architecture 70 within the enclosure 10, as well as the computing and storage units on the carrier board 71. This facilitates maintenance and upgrades, ensures stable system operation, and enables high-speed data transmission between modules via high-bandwidth interfaces, thereby improving overall performance.

[0035] Furthermore, the SoC computing module 72 employs a one-to-one architecture design between computing units and storage units (i.e., each computing unit is equipped with a dedicated storage unit). This allows computing units to directly access their bound storage units, avoiding contention and waiting times across modules or shared storage. The binding relationship between each computing unit and storage unit also enables multiple modules to execute tasks in parallel without interference, avoiding bandwidth contention issues.

[0036] In some embodiments, a PCIe interface is provided on the baseboard 73 corresponding to the computing unit, and an M.2 interface is provided on the baseboard 73 corresponding to the storage unit. The M.2 interface is a next-generation interface standard tailored for Ultrabooks. It is compact, supports multiple protocols (such as SATA, PCIe, NVMe, etc.), and can connect to various high-performance storage devices, such as SSDs (Solid State Drives). It not only provides high data transfer rates but also has good scalability and compatibility.

[0037] Furthermore, the use of PCIe and M.2 interfaces enables high-speed and stable data transmission between the computing and storage units, thereby improving the overall system performance. Additionally, by providing separate PCIe and M.2 interfaces for the computing and storage units, independent connections and interoperability between modules are achieved, further enhancing the flexibility of modular design. Users can flexibly select and configure different computing and storage units according to their actual needs.

[0038] Furthermore, the computing unit is a SoC (System-on-a-Chip) computing core board. This board integrates multiple functions such as CPU, GPU, memory, and I / O interfaces onto a single chip, reducing component count, power consumption, and heat dissipation requirements, while improving system stability and reliability. The accompanying storage units include SSDs and HDDs. SSDs offer extremely high read and write speeds, significantly improving system response and operating efficiency. While HDDs have larger storage capacities than SSDs, they are suitable for storing large amounts of infrequently accessed data. SSDs are further categorized into consumer-grade and enterprise-grade SSDs. Consumer-grade SSDs offer a cost advantage over enterprise-grade SSDs while maintaining sufficient performance for most application scenarios; therefore, consumer-grade SSDs are preferred for energy storage in this system.

[0039] In some embodiments, the base plate 73 is a double-sided circuit board, and SoC computing modules 72 are provided on both opposite sides of the base plate 73.

[0040] In this embodiment, space is effectively utilized by deploying SoC computing modules 72 on both sides of the base plate 73 simultaneously. For example, the double-sided design can arrange four SoC computing modules 72 on each of the front and back sides of the base plate 73, thereby arranging a total of eight modules on a single base plate 73, which can significantly improve computing density and system performance.

[0041] See Figure 3 As shown, in some embodiments, each SoC computing module 72 further includes a heat sink 721, which is attached to the computing unit and includes a plurality of spaced heat sinks.

[0042] Understandably, in the modular SoC carrier architecture 70, each SoC computing module 72 is responsible for performing high-intensity computing tasks, which generates a large amount of heat. If this heat cannot be dissipated in time, it will cause the temperature of the computing unit to rise, thereby affecting its performance, stability, and lifespan. Therefore, a heat sink 721 is provided in the SoC computing module 72.

[0043] In this embodiment, the heat sink 721 needs to be in close contact with the computing unit to ensure effective heat absorption and conduction. This can be achieved through methods such as thermal grease, thermal pads, or direct metal contact to reduce thermal resistance and improve heat dissipation efficiency. Furthermore, the heat sink 721 in this embodiment includes multiple spaced-apart heat sinks, which increase the heat dissipation area, allowing heat to be dissipated into the surrounding environment more quickly.

[0044] In some embodiments, the carrier board 71 is pull-out connected to the chassis; wherein the carrier board 71 is provided with a pull-out structure for pull-out connection with the chassis. This allows the carrier board 71 and its onboard SoC computing module 72 to be easily inserted into or removed from the server chassis, thereby improving the maintainability and scalability of the system. This pull-out structure typically includes one or more guide rails, sliders, or similar mechanical components for guiding the carrier board 71 smoothly in and out of the chassis; it is a common structure in the art and will not be described in detail here.

[0045] In further proposals, such as Figure 3 As shown, the carrier board 71 includes a pull-out head 711 and side plates 712 extending opposite to each other on both sides of the pull-out head 711. The pull-out head 711 is typically designed with a shape and texture that facilitates gripping, allowing users to easily pull out or insert the carrier board 71. A plug-in switch can also be provided on the pull-out head 711 to control the locking and unlocking state of the carrier board 71, facilitating its removal from or entry into the chassis. The side plates 712 not only provide structural support for the carrier board 71 but also protect the SoC computing modules 72. Typically, the side plates 712 and the chassis 10 are connected by a pull-out guide rail slider to guide the carrier board 71 in and out of the chassis. A base plate 73 is disposed between the two side plates 712. The SoC computing modules 72 on the base plate 73 are arranged at intervals along the extending direction of the side plates 712. A connector 732 is provided on the side of the side plate 712 away from the pull-out head 711, corresponding to the PCIe interface in the back panel 20. In this way, when the carrier board 71 is inserted into the server chassis, the connector 732 will be accurately inserted into the PCIe interface, realizing the electrical connection between the baseboard 73 and the backplane 20, ensuring the stability and high speed of data transmission, and meeting the needs of high-performance computing.

[0046] See Figure 1 and Figure 2As shown, in some embodiments, the end of the pull-out head 711 is provided with a ventilation hole 713, and the end of the chassis opposite to the pull-out head 711 is provided with a ventilation mesh 110; and the SoC array server chassis 100 also includes multiple cooling fans, which are connected to the motherboard 30 and are linearly distributed along the extension direction of the backplate 20, for forming air convection between the ventilation hole 713 and the ventilation mesh 110 to cool down the carrier board architecture 70; wherein, the gap between the multiple heat sinks forms an air duct, and the extension direction of the air duct is the same as the airflow direction.

[0047] In this embodiment, the ventilation hole 713 is located at the end of the pull-out head 711 of the carrier board structure 70. It can adopt a honeycomb or strip hole design to maximize the air intake area while ensuring structural strength. It directly guides cold air into the carrier board 71 area to prioritize cooling high-heat components, such as the SoC computing module 72. The chassis ventilation mesh 110 is located at the rear of the chassis (opposite to the pull-out head 711). It can also adopt a hexagonal honeycomb structure to balance dust prevention and low wind resistance. As an exhaust channel, it quickly exhausts hot air and forms a pressure difference between the front and rear to drive the airflow.

[0048] Multiple cooling fans are connected to the motherboard 30 and arranged in a straight line along the extension direction of the backplate 20, forming a full-coverage airflow guidance system within the enclosure 10 to ensure even temperature distribution and prevent localized overheating. Preferably, the system consists of six 7200 RPM fans, whose speed can be dynamically adjusted, automatically increasing or decreasing the speed based on real-time temperature feedback to maintain optimal heat dissipation and extend the server's lifespan.

[0049] Furthermore, the gaps between the heat sinks (air ducts) are aligned with the direction of the fan array to ensure unobstructed airflow. The airflow between the ventilation holes 713 and the ventilation mesh 110 directly enters the heat dissipation core area, thereby achieving more efficient heat dissipation and effectively reducing the operating temperature of the SoC computing module 72.

[0050] See Figure 3 As shown, in some embodiments, to accommodate the dual-sided SoC computing modules 72 on the base plate 73, the base plate 73 is positioned opposite to the middle of the carrier plate 71, providing space for the installation of the SoC computing modules 72 on both sides. Furthermore, after the SoC computing modules 72 are installed on opposite sides of the base plate 73, the total thickness of the SoC computing modules 72 on both sides does not exceed the overall thickness of the carrier plate 71. This avoids installation difficulties caused by excessive module thickness, ensures a compact overall structure of the carrier plate 71, facilitates efficient operation within a limited space, improves heat dissipation, and ensures stable system operation.

[0051] In the specific installation structure of the base plate 73, two oppositely arranged side plates 712 extend to form a support plate 714. The support plate 714 is provided with a positioning post 716 and a first locking hole 715. The base plate 73 is provided with a positioning hole 734 corresponding to the positioning post 716 and a second locking hole 733 corresponding to the first locking hole 715. Thus, through the precise cooperation of the positioning hole 734 and the locking hole, the carrier plate 71 is stably positioned within the chassis, preventing poor contact caused by vibration or movement, and further improving the reliability and service life of the system.

[0052] The above are only some or preferred embodiments of this application. Neither the text nor the drawings should limit the scope of protection of this application. All equivalent structural transformations made using the content of this application's specification and drawings under the overall concept of this application, or direct / indirect applications in other related technical fields, are included within the scope of protection of this application.

Claims

1. A SoC array server chassis, characterized in that, The enclosure includes a chassis and a detachable backplate, motherboard, BMC control board, switching board, power module, and carrier board architecture. The backplate is located near the center of the chassis to divide the chassis into a first cavity and a second cavity. The motherboard, BMC control board, switching board, and power module are all located in the second cavity, and the BMC control board, switching board, power module, and backplate are all electrically connected to the motherboard via a custom PCIe interface. Multiple carrier board architectures are arranged in an array within the first cavity. The carrier board architecture includes a carrier board and multiple SoC computing modules. A baseboard is detachably mounted on the carrier board, and the baseboard is electrically connected to the backplane via a custom PCIe interface to access the motherboard. The SoC computing modules are mounted on the baseboard, and each SoC computing module includes a computing unit and a storage unit. The baseboard is provided with a plug-in interface for each SoC computing module, so that the computing unit and the storage unit are detachably connected to the baseboard, and the computing unit in each SoC computing module accesses the storage unit through the baseboard.

2. The SoC array server chassis according to claim 1, characterized in that, The base plate is provided with a PCIe interface corresponding to the computing unit, and the base plate is provided with an M.2 interface corresponding to the storage unit.

3. The SoC array server chassis according to claim 2, characterized in that, The base plate is a double-sided circuit board, and the SoC computing module is provided on both opposite sides of the base plate.

4. The SoC array server chassis according to claim 3, characterized in that, The computing unit is a SoC computing core board, and the storage unit includes an SSD and an HDD.

5. The SoC array server chassis according to any one of claims 1-4, characterized in that, Each of the SoC computing modules further includes a heat sink, which is attached to the computing unit and includes a plurality of spaced heat sink fins.

6. The SoC array server chassis according to claim 5, characterized in that, The carrier board is connected to the chassis by a pull-out mechanism; it includes a pull-out head and side plates extending opposite to each other on both sides of the pull-out head, and a bottom plate is disposed between the two side plates. The SoC computing modules on the bottom plate are arranged at intervals along the extending direction of the side plates. The base plate has a connector on the side away from the pull-out head, and the connector corresponds to the PCIe slot in the back plate.

7. The SoC array server chassis according to claim 6, characterized in that, The end of the pull-out head is provided with a ventilation hole, and the end of the chassis opposite to the pull-out head is provided with a ventilation mesh; and the SoC array server chassis also includes multiple cooling fans, which are connected to the motherboard and are distributed in a straight line along the extension direction of the back plate, for forming air convection between the ventilation hole and the ventilation mesh to cool and dissipate heat from the carrier board architecture. The gaps between the multiple heat sinks form air ducts, and the extension direction of the air ducts is the same as the airflow direction.

8. The SoC array server chassis according to claim 6, characterized in that, The base plate is positioned opposite to the center of the carrier board so that the installed SoC computing module does not exceed the overall thickness range of the carrier board.

9. The SoC array server chassis according to claim 7, characterized in that, The two oppositely arranged side plates extend to form a support plate. The support plate is provided with a positioning post and a first locking hole. The bottom plate is provided with a positioning hole corresponding to the positioning post and a second locking hole corresponding to the first locking hole.

10. The SoC array server chassis according to claim 1, characterized in that, The power supply module is configured to have two components, each of which is hot-swappable to the motherboard, so that if one of the power supply modules fails, the other power supply module can serve as a backup power supply.

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