Protection circuit

Abstract

The utility model provides a protection circuit, which comprises a sampling module, a comparison module, a wave sealing module and an anti-logic driving module, and is characterized in that the input end of the sampling module is connected to the signal acquisition end of a target driving device, and the output end of the sampling module is connected to the input end of the comparison module; the output end of the comparison module is connected to the input end of the wave sealing module, the output end of the wave sealing module is connected to the input end of the anti-logic driving module, the first output end of the anti-logic driving module is connected to the grid control end of the target driving device, and the second output end of the anti-logic driving module is connected to the source end of the target driving device. According to the protection circuit provided by the invention, wave sealing processing can be performed on the target driving device when the target driving device is in an abnormal operation state, and the operation reliability of the power device is improved.

Description

Technical Field

[0001] This application relates to the field of power drive device protection technology, and in particular to a protection circuit. Background Technology

[0002] With the development of power electronics technology, switching power supplies have been widely used in industrial control, communication equipment, consumer electronics, and new energy fields due to their advantages such as high efficiency, small size, and light weight. However, in actual operation, switching power supplies often face abnormal conditions such as input voltage fluctuations, sudden load changes, short circuits, or overheating. Currently, the protection circuits in existing switching power supplies integrate multiple protection structures. These multiple protection structures have the following drawbacks when abnormal conditions occur in the switching power supply:

[0003] First, due to the lack of a coordinated control mechanism between the protection modules, when multiple abnormal signals occur simultaneously or occur consecutively in a short period of time, it is easy to cause protection malfunctions, resulting in frequent system restarts or unexpected shutdowns, affecting normal power supply. Second, some protection circuits have a slow response speed, especially when facing rapidly changing abnormal operating conditions (such as output short circuits or sudden load increases), failing to trigger protection actions in time, causing power devices to bear excessive current or voltage stress, thereby causing component damage or even fires and other safety accidents. Utility Model Content

[0004] In view of this, the purpose of this application is to provide at least one protection circuit that can block out the target driving device when it is in an abnormal operating state, thereby increasing the reliability of the power device operation.

[0005] This application mainly includes the following aspects:

[0006] In a first aspect, embodiments of this application provide a protection circuit, which includes a sampling module, a comparison module, a blocking module, and an inverted logic driving module: wherein, the input terminal of the sampling module is connected to the signal acquisition terminal of the target driving device, the output terminal of the sampling module is connected to the input terminal of the comparison module, the output terminal of the comparison module is connected to the input terminal of the blocking module, the output terminal of the blocking module is connected to the input terminal of the inverted logic driving module, the first output terminal of the inverted logic driving module is connected to the gate control terminal of the target driving device, and the second output terminal of the inverted logic driving module is connected to the source terminal of the target driving device.

[0007] In one possible implementation, the comparison module includes a differentiating unit, a first comparison unit, and a second comparison unit. The output of the sampling module is connected to the input of the differentiating unit and the input of the second comparison unit, respectively. The output of the differentiating unit is connected to the input of the first comparison unit. The outputs of the first comparison unit and the second comparison unit are connected to different inputs of the blocking module, respectively. The output of the blocking module is connected to the output of the inverse logic driving module.

[0008] In one possible implementation, the sealing module includes a sealing period adjustment unit, a counting unit, a triggering unit, and a sealing control unit. The output of a first comparison unit is connected to the inputs of the sealing period adjustment unit and the counting unit, respectively. The output of the counting unit is connected to the input of the triggering unit, and the output of the triggering unit is connected to the first input of the sealing control unit. The output of the sealing period adjustment unit is connected to the second input of the sealing control unit. The output of the second comparison unit is connected to the third input of the sealing control unit. The output of the sealing control unit is connected to the output of the inverse logic drive module. 。

[0009] In one possible implementation, the sealing control unit includes a first sealing signal generation unit, a second sealing signal generation unit, and a sealing output unit. The input terminal of the first sealing signal generation unit is connected to the output terminal of the sealing period adjustment unit, and the output terminal of the first sealing signal generation unit is connected to the first enable terminal of the sealing output unit. The input terminal of the second sealing signal generation unit is connected to the output terminal of the trigger unit and the output terminal of the second comparison unit, respectively, and the output terminal of the second sealing signal generation unit is connected to the second enable terminal of the sealing output unit. The output terminal of the sealing output unit is connected to the output terminal of the inverse logic drive module.

[0010] In one possible implementation, the wave blocking period adjustment unit includes a timer chip, a first resistor, a first capacitor, a second capacitor, and a wave blocking trigger component. The ground pin of the timer chip is connected to the power supply ground; the trigger input pin of the timer chip is connected to the output of the first comparison unit; the output pin of the timer chip is connected to the input of the wave blocking trigger component; the output of the wave blocking trigger component is connected to the input of the first wave blocking signal generation unit; the reset input pin of the timer chip is connected to the first driving power supply; the control voltage input pin of the timer chip is connected to the power supply ground through the first capacitor; the threshold input pin of the timer chip is connected to the discharge pin of the timer chip, and then connected to the power supply ground through the second capacitor and to the first driving power supply through the first resistor, respectively; and the power supply input pin of the timer chip is connected to the first driving power supply.

[0011] In one possible implementation, the counting unit includes a counting chip, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a third capacitor. The counting trigger signal input pin of the counting chip is connected to the output of a first comparison unit. The clear input pin of the counting chip is connected to one end of the second resistor, one end of the third capacitor, and a count clear signal, respectively. The ground pin of the counting chip is connected to the other end of the second resistor, the other end of the third capacitor, and power ground, respectively. The first output of the counting chip is connected to power ground through the third resistor. The second output of the counting chip is connected to power ground through the fourth resistor. The third output of the counting chip is connected to power ground through the fifth resistor. The fourth output of the counting chip is connected to the input of the trigger unit.

[0012] In one possible implementation, the first sealing signal generation unit includes a first diode, a sixth resistor, a seventh resistor, an eighth resistor, and a first control switch. The output terminal of the sealing period adjustment unit is connected to the cathode of the first diode. The anode of the first diode is connected to the control terminal of the first control switch and the first connection terminal of the first control switch through the sixth resistor and the seventh resistor, respectively. The second connection terminal of the first control switch is connected to the first driving power supply and the first enable terminal of the sealing output unit through the eighth resistor, respectively. The first connection terminal of the first control switch is also connected to the power ground.

[0013] In one possible implementation, the second blocking signal generation unit includes a second diode, a third diode, a ninth resistor, a tenth resistor, an eleventh resistor, and a second control switch. The cathode of the second diode is connected to the output terminal of the trigger unit, the cathode of the third diode is connected to the output terminal of the second comparator unit, and the anodes of the second and third diodes are connected and then connected to the control terminal of the second control switch via the ninth resistor and the first connection terminal of the second control switch via the ninth and tenth resistors, respectively. The first connection terminal of the second control switch is also connected to the power ground, and the second connection terminal of the second control switch is connected to the first driving power supply and the second enable terminal of the blocking output unit via the eleventh resistor, respectively.

[0014] In one possible implementation, the blocking output unit includes a driver chip, a signal output component, and a signal input component. The first enable pin of the driver chip is connected to the output terminal of the second blocking signal generation unit. The drive signal input pin of the driver chip is connected to an input drive signal and to a second drive power supply through the signal input component. The power supply pin of the driver chip is connected to a first drive power supply. The drive signal output pin of the driver chip is connected to the input terminal of the inverted logic drive module and to the first drive power supply through the signal output component. The second enable pin of the driver chip is connected to the output terminal of the first blocking signal generation unit. The ground pin of the driver chip is connected to the power ground.

[0015] In one possible implementation, the reverse logic drive module includes a gate drive optocoupler, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a fourth diode, a fifth diode, and a fourth capacitor. The anode pin of the gate drive optocoupler is connected to one end of the twelfth resistor and one end of the thirteenth resistor. The other end of the twelfth resistor is connected to one end of the fourteenth resistor and the cathode of the gate drive optocoupler. The fifteenth resistor is connected in parallel between the other ends of the thirteenth and fourteenth resistors. The other end of the thirteenth resistor is also connected to a first drive power supply, and the other end of the fourteenth resistor is also connected to the output terminal of the wave blocking module. The positive power supply pin of the driving optocoupler is connected to the positive given voltage. The output pin of the gate driving optocoupler is connected to one end of the sixteenth resistor and one end of the seventeenth resistor, respectively. The other end of the sixteenth resistor is connected to the cathode of the fourth diode. The other end of the seventeenth resistor is connected to the anode of the fourth diode, and then connected to the cathode of the fifth diode, one end of the fourth capacitor, and the gate driving terminal of the target driving device, respectively. The anode of the fifth diode is connected to DRIVE_INV_-5V. The other end of the fourth capacitor is connected to the source terminal of the target driving device through the eighteenth resistor. The nineteenth resistor is connected in parallel between the gate driving terminal and the source terminal of the target driving device. The negative power supply pin of the gate driving optocoupler is connected to the negative given voltage.

[0016] In one possible implementation, the reverse logic driving module further includes a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a twentieth resistor, a twenty-first resistor, and a Zener diode. One end of the fifth capacitor is connected to one end of the sixth capacitor, one end of the twentieth resistor, and one end of the twenty-first resistor to be connected to a positive given voltage. The other end of the fifth capacitor is connected to the other end of the sixth capacitor, the other end of the twentieth resistor, the other end of the twenty-first resistor, one end of the seventh capacitor, one end of the eighth capacitor, and the cathode of the Zener diode to be connected to the source terminal of the target driving device. The other ends of the seventh capacitor, the other end of the eighth capacitor, and the anode of the Zener diode are connected to be connected to a negative given voltage.

[0017] This application provides a protection circuit comprising a sampling module, a comparison module, a blocking module, and an inverted logic drive module. The input of the sampling module is connected to the signal acquisition terminal of the target driven device; the output of the sampling module is connected to the input of the comparison module; the output of the comparison module is connected to the input of the blocking module; the output of the blocking module is connected to the input of the inverted logic drive module; the first output of the inverted logic drive module is connected to the gate control terminal of the target driven device; and the second output of the inverted logic drive module is connected to the source terminal of the target driven device. This protection circuit can block the target driven device when it is in an abnormal operating state, increasing the reliability of the power device.

[0018] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This illustration shows one of the structural schematic diagrams of a protection circuit provided in an embodiment of this application;

[0021] Figure 2 This is a second schematic diagram of the structure of a protection circuit provided in an embodiment of this application;

[0022] Figure 3 This paper shows a schematic diagram of the structure of a wave blocking control unit provided in an embodiment of this application;

[0023] Figure 4 This illustration shows a schematic diagram of the structure of a data acquisition module provided in an embodiment of this application;

[0024] Figure 5 This illustration shows a structural schematic diagram of a differential unit provided in an embodiment of this application;

[0025] Figure 6 This illustration shows a schematic diagram of the structure of a first comparison unit provided in an embodiment of this application;

[0026] Figure 7 This paper shows a schematic diagram of the structure of a blocking period adjustment unit provided in an embodiment of this application;

[0027] Figure 8A schematic diagram of the structure of a counting unit provided in an embodiment of this application is shown;

[0028] Figure 9 This illustration shows a schematic diagram of the structure of a triggering unit provided in an embodiment of this application;

[0029] Figure 10 This paper shows one of the partial structural schematic diagrams of the wave-blocking control unit provided in an embodiment of this application;

[0030] Figure 11 This illustration shows a schematic diagram of the structure of a second comparison unit provided in an embodiment of this application;

[0031] Figure 12 This is a second schematic diagram of a partial structure of the wave-blocking control unit provided in an embodiment of this application;

[0032] Figure 13 A schematic diagram of the structure of an anti-logic driving module provided in an embodiment of this application is shown. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0034] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0035] When existing power devices (such as switching power supplies) are in operation, they may be in abnormal operating conditions such as overvoltage or overcurrent due to various factors. Under such conditions, it is very easy to cause damage to the devices and reduce the reliability of the entire circuit operation because the drive output to the power devices is not cut off in time.

[0036] Based on this, the embodiments of this application provide a protection circuit that can perform waveform blocking when the target driving device is in an abnormal operating state, thereby increasing the operational reliability of the power device, as detailed below:

[0037] Please see Figure 1 , Figure 1 This illustration shows one of the structural schematic diagrams of a protection circuit provided in an embodiment of this application. For example... Figure 1 As shown, the protection circuit provided in this application embodiment includes a sampling module 1, a comparison module 2, a blocking module 3, and an inverted logic drive module 4. The input terminal of the sampling module 1 is connected to the signal acquisition terminal I_VIOUT of the target driving device (e.g., a switching power supply). The output terminal of the sampling module 1 is connected to the input terminal of the comparison module 2. The output terminal of the comparison module 2 is connected to the input terminal of the blocking module 3. The output terminal of the blocking module 3 is connected to the input terminal of the inverted logic drive module 4. The first output terminal of the inverted logic drive module 4 is connected to the gate control terminal Drive_G of the target driving device, and the second output terminal of the inverted logic drive module 4 is connected to the source terminal Drive_S of the target driving device.

[0038] In a preferred embodiment, please refer to Figure 2 , Figure 2 This is a second schematic diagram of a protection circuit provided in an embodiment of this application. Figure 2 As shown, the comparison module 2 includes a differential unit 21, a first comparison unit 22, and a second comparison unit 23. The wave blocking module 3 includes a wave blocking period adjustment unit 31, a counting unit 32, a triggering unit 33, and a wave blocking control unit 34.

[0039] The output of sampling module 1 is connected to the input of differential unit 21 and the input of second comparison unit 23, respectively. The output of differential unit 21 is connected to the input of first comparison unit 22. The output of first comparison unit 22 is connected to the input of sealing period adjustment unit 31 and the input of counting unit 32, respectively. The output of counting unit 32 is connected to the input of trigger unit 33. The output of trigger unit 33 is connected to the first input of sealing control unit 34. The output of sealing period adjustment unit 31 is connected to the second input of sealing control unit 34. The output of second comparison unit 23 is connected to the third input of sealing control unit 34. The output of sealing control unit 34 is connected to the output of inverse logic drive module 4.

[0040] In a preferred embodiment, please refer to Figure 3 , Figure 3 A schematic diagram of a wave blocking control unit provided in an embodiment of this application is shown. Figure 3 As shown, the sealing control unit 34 includes a first sealing signal generation unit 341, a second sealing signal generation unit 342, and a sealing output unit 343. The input terminal of the first sealing signal generation unit 341 is connected to the output terminal of the sealing period adjustment unit 31, and the output terminal of the first sealing signal generation unit 341 is connected to the first enable terminal of the sealing output unit 343. The input terminals of the second sealing signal generation unit 342 are respectively connected to the output terminals of the trigger unit 33 and the second comparison unit 23. The output terminal of the second sealing signal generation unit 342 is connected to the second enable terminal of the sealing output unit 343, and the output terminal of the sealing output unit 343 is connected to the output terminal of the inverse logic drive module 4.

[0041] In one specific embodiment, please refer to Figure 4 , Figure 4 A schematic diagram of the structure of a data acquisition module provided in an embodiment of this application is shown. Figure 4 As shown, the acquisition module includes a first operational amplifier LM1, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a thirteenth capacitor C13, and a fourteenth capacitor C14.

[0042] In this configuration, the non-inverting input of the first operational amplifier LM1 is connected to one end of the 22nd resistor R22, one end of the 24th resistor R24, and one end of the 11th capacitor C11. The other end of the 22nd resistor R22 is connected to the signal acquisition terminal I_VIOUT of the target driving device (which can be a current signal or a voltage signal, without specific limitations) and one end of the 9th capacitor C9. The other end of the 24th resistor R24 ​​is connected to the other end of the 11th capacitor C11 and then fed into the second given reference signal 1.65Vref. The inverting input of the first operational amplifier LM1 is connected to one end of the 23rd resistor R23, and the other end of the 23rd resistor R23 is connected to the 10th capacitor C11. One end of capacitor C10 is connected to the reference signal I_VREF. The other end of capacitor C10 is connected to the power ground AGND. Resistor R25 and capacitor C12 are connected in parallel. One end of R25 is connected to the inverting input of the first operational amplifier LM1, and the other end is connected to the output of the first operational amplifier LM1. The output of the first operational amplifier LM1 outputs signal ADC_1 and is connected to the input of the differentiating unit 21 and the input of the second comparator unit 23. The positive power supply of the first operational amplifier LM1 is connected to the first driving power supply 5VDDA. The positive power supply of the first operational amplifier LM1 is also connected to the power ground AGND through capacitors C13 and C14 connected in parallel.

[0043] In one specific embodiment, the first operational amplifier LM1 is model LMV358AIDR.

[0044] In a preferred embodiment, please refer to Figure 5 , Figure 5 A schematic diagram of a differential unit provided in an embodiment of this application is shown. Figure 5 As shown, the differentiating unit includes the fifteenth capacitor C15, the sixteenth capacitor C16, the seventeenth capacitor C17, the eighteenth capacitor C18, the nineteenth capacitor C19, the twenty-sixth resistor R26, the twenty-seventh resistor R27, the twenty-eighth resistor R28, and the second operational amplifier LM2.

[0045] The non-inverting input of the second operational amplifier LM2 is connected to the second given reference signal 1.65Vref via the parallel connection of the 27th resistor R27 and the 16th capacitor C16. The inverting input of the second operational amplifier LM2 is connected to the output of the first operational amplifier LM1 via the 26th resistor R26 and the 15th capacitor C1. The inverting input of the second operational amplifier LM2 is also connected to the output of the second operational amplifier LM2 via the parallel connection of the 28th resistor R28 and the 17th capacitor C17. The output of the second operational amplifier LM2 outputs the signal Diff_ADC and is connected to the input of the first comparator unit 22. The positive power supply of the second operational amplifier LM2 is connected to the first driving power supply 5VDDA and to the power ground AGND via the parallel connection of the 18th capacitor C18 and the 19th capacitor C19. The negative power supply of the second operational amplifier LM2 is connected to the power ground AGND.

[0046] In a preferred embodiment, please refer to Figure 6 , Figure 6 A schematic diagram of the structure of a first comparison unit provided in an embodiment of this application is shown. Figure 6 As shown, the first comparator unit includes resistors R29 (29th), R30 (30th), R31 (31st), R32 (32nd), R33 (33rd), R34 (34th), and R35 (35th), capacitors C20 (20th), C21 (21st), C22 (22nd), C23 (23rd), C24 (24th), and C25 (25th), as well as operational amplifiers LM3 (3rd) and LM4 (4th).

[0047] The non-inverting input of the third operational amplifier LM3 is connected to the first given reference signal 3.3Vref through the twenty-ninth resistor R29 and to the power ground AGND through the thirty-first resistor R31 and the twentieth capacitor C20 connected in parallel. The inverting input of the third operational amplifier LM3 is connected to the output of the second operational amplifier LM2 (i.e., the output signal Diff_ADC) through the thirtieth resistor R30, to the power ground AGND through the twenty-first capacitor C21, and to the non-inverting input of the fourth operational amplifier LM4. The positive power supply of the third operational amplifier LM3 is connected to the first driving power supply 5VDDA and to the power ground AGND through the twenty-second capacitor C22 and the twenty-third capacitor C23 connected in parallel. The negative power supply of the third operational amplifier LM3 is connected to the power ground AGND.

[0048] The inverting input of the fourth operational amplifier LM4 is connected to the first given reference signal 3.3Vref through the thirty-second resistor R32 and to the power ground AGND through the thirty-third resistor R33 and the twenty-fourth capacitor R24 ​​connected in parallel. The positive power supply of the fourth operational amplifier LM4 is connected to the first driving power supply 5VDDA, and the negative power supply of the fourth operational amplifier LM4 is connected to the power ground AGND. The output of the fourth operational amplifier LM4 is connected to the output of the third operational amplifier LM3. The output of the third operational amplifier LM3 is also connected to the second driving power supply 3.3VDDA through the thirty-fourth resistor R34, outputs the signal CBC through the thirty-fifth resistor R35 and connects it to the input of the blocking period adjustment unit 31 and the input of the counting unit 32, and is connected to the power ground AGND through the thirty-fifth resistor R35 and the twenty-fifth capacitor C25.

[0049] In one specific embodiment, both the third operational amplifier LM3 and the fourth operational amplifier LM4 are LMV393IDR.

[0050] In a preferred embodiment, please refer to Figure 7 , Figure 7 A schematic diagram of the structure of a blocking period adjustment unit provided in an embodiment of this application is shown. Figure 7 As shown, the wave blocking period adjustment unit 31 includes a timer chip U1, a first resistor R1, a first capacitor C1, a second capacitor C2, a twenty-sixth capacitor C26, a twenty-seventh capacitor C27, and a wave blocking trigger component 311. The ground pin GND of the timer chip U1 is connected to the power ground AGND. The trigger input pin TRIG of the timer chip U1 is connected to the output terminal of the first comparison unit 22 (i.e., the input signal CBC). The output pin OUT of the timer chip U1 outputs the signal Fault_CBC and is connected to the input terminal of the wave blocking trigger component 311. The output terminal of the wave blocking trigger component 311 is connected to the input terminal of the first wave blocking signal generation unit 341. The timer chip U1's complexing... The RESET pin of the timer chip U1 is connected to the first drive power supply 5VDDA. The CONT pin of the timer chip U1 is connected to the power ground AGND through the first capacitor C1. The THRES pin of the timer chip U1 is connected to the DISCH pin of the timer chip U1, and then connected to the power ground AGND through the second capacitor C2 and the first drive power supply 5VDDA through the first resistor R1. The VCC pin of the timer chip U1 is connected to the first drive power supply 5VDDA. The VCC pin of the timer chip U1 is also connected to the power ground AGND through the twenty-sixth capacitor C26 and the twenty-seventh capacitor C27 connected in parallel.

[0051] In another preferred embodiment, the wave blocking trigger component 311 includes a first trigger resistor RN1, a second trigger resistor RN12, a pull-up resistor RN3, and a fourth control switch K4. The control terminal of the fourth control switch K4 is connected to the output pin OUT (i.e., the access signal Fault_CBC) of the timer chip U1 through the first trigger resistor RN1 and to the power ground AGND through the first connection terminal of the fourth control switch K4 through the second trigger resistor RN12. The second connection terminal of the fourth control switch K4 is connected to the first drive power supply 5VDDA and the output signal Fault_EN through the pull-up resistor RN3 and is connected to the input terminal of the first wave blocking signal generation unit 341.

[0052] In one specific embodiment, the timer chip U1 adopts SE555D. For the timer chip U1, its corresponding output signal Fault_CBC is affected by the signal CBC it is connected to. When the signal CBC is high, the output signal Fault_CBC remains low. When the signal CBC is low, the output signal Fault_CBC will change from a low level to a high level and maintain it for a predetermined time period before returning to a low level. The predetermined time period is determined by the first resistor R1 and the second capacitor C2. Specifically, the predetermined time period = 1.1 × R × C.

[0053] In a preferred embodiment, please refer to Figure 8 , Figure 8 A schematic diagram of the structure of a counting unit provided in an embodiment of this application is shown. Figure 8 As shown, the counting unit 32 includes a counting chip U2, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a third capacitor C3. The counting trigger signal input pin 1A of the counting chip U2 is connected to the output terminal (i.e., the input signal CBC) of the first comparison unit 22. The clear input pin 1CRL of the counting chip U2 is connected to one end of the second resistor R2, one end of the third capacitor C3, and the count clear signal Clear. The ground pin GND of the counting chip U2 is connected to the other end of the second resistor R2, the other end of the third capacitor C3, and the power ground AGND. The first output pin 1QA of the counting chip U2 is connected to the power ground AGND through the third resistor R3. The second output pin 1QB of the counting chip U2 is connected to the power ground AGND through the fourth resistor R4. The third output pin 1QC of the counting chip U2 is connected to the power ground AGND through the fifth resistor R5. The fourth output pin 1QD of the counting chip U2 outputs the signal Count and is connected to the input terminal of the trigger unit 33.

[0054] Specifically, the count reset signal (Clear) can be controlled by input from the host computer software, or it can be triggered manually, such as... Figure 8As shown, the counting unit 32 also includes a manual switch SW and a thirty-sixth resistor R36. One end of the manual switch SW is connected to the clear input pin 1CRL of the counting chip U2, and the other end of the manual switch SW is connected to the second drive power supply 3.3VDDA through the thirty-sixth resistor R36. When the user presses the manual switch SW, a corresponding clear signal will be generated.

[0055] Preferably, the counter chip U2 can be an SN54LS393.

[0056] In a preferred embodiment, please refer to Figure 9 , Figure 9 A schematic diagram of a trigger unit provided in an embodiment of this application is shown. Figure 9 As shown, the triggering unit includes a 37th resistor R37, a 38th resistor R38, a 39th resistor R39, and a third control switch K3. The control terminal of the third control switch K3 is connected to the output terminal of the counting unit 32 (i.e., the output signal Count) through the 37th resistor R37 and to the power ground AGND through the 38th resistor R38. The second connection terminal of the third control switch K3 is connected to the first driving power supply 5VDDA and the output signal Count_pwm through the 39th resistor R39 and is directly connected to the input terminal of the second semaphore signal generation unit 342.

[0057] In one specific embodiment, the third control switch K3 can be an NPN transistor. The control terminal of the third control switch K3 is the base of the NPN transistor, the first connection terminal of the third control switch K3 is the emitter of the NPN transistor, and the second connection terminal of the third control switch K3 is the collector of the NPN transistor.

[0058] In a preferred embodiment, please refer to Figure 10 , Figure 10 This illustration shows one of the partial structural schematic diagrams of the wave-sealing control unit provided in an embodiment of this application. For example... Figure 10 As shown, the first sealing signal generation unit 341 includes a first diode D1, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a first control switch K1. The output terminal (i.e., the signal Fault_EN) of the sealing period adjustment unit 31 is connected to the cathode of the first diode D1. The anode of the first diode D1 is connected to the control terminal of the first control switch K1 through the sixth resistor R6 and to the first connection terminal and power ground AGND of the first control switch K1 through the sixth resistor R6 and the seventh resistor R7. After the second connection terminal of the first control switch K1 outputs the first enable signal CBC_EN, it is connected to the first driving power supply and the first enable terminal of the sealing output unit 343 through the eighth resistor R8.

[0059] In one specific embodiment, the first control switch K1 can be an NPN transistor, the control terminal of the first control switch K1 is the base of the NPN transistor, the first connection terminal of the first control switch K1 is the emitter of the NPN transistor, and the second connection terminal of the first control switch K1 is the collector of the NPN transistor.

[0060] In a preferred embodiment, the second blocking signal generation unit 342 includes a second diode D2, a third diode D3, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and a second control switch K2. The cathode of the second diode D2 is connected to the output terminal of the trigger unit 33 (i.e., the input signal Count_pwm), and the cathode of the third diode D3 is connected to the output terminal of the second comparison unit 23. After the anodes of the second diode D2 and the third diode D3 are connected, they are respectively connected to the control terminal of the second control switch K2 through the ninth resistor R9 and to the first connection terminal of the second control switch K2 and the power ground AGND through the ninth resistor R9 and the tenth resistor R10. The first connection terminal of the second control switch K2 is also connected to the power ground AGND. After the second connection terminal of the second control switch K2 outputs the second enable signal PWM_EN, it is respectively connected to the first driving power supply and the second enable terminal of the blocking output unit 343 through the eleventh resistor R11.

[0061] In one specific embodiment, the second control switch K2 can be an NPN transistor. The control terminal of the second control switch K2 is the base of the NPN transistor, the first connection terminal of the second control switch K2 is the emitter of the NPN transistor, and the second connection terminal of the second control switch K2 is the collector of the NPN transistor.

[0062] In a preferred embodiment, please refer to Figure 11 , Figure 11 A schematic diagram of the structure of a second comparison unit provided in an embodiment of this application is shown. Figure 11 As shown, the second comparison unit 23 includes a comparison component 231 and a latch component 232. The input terminal of the comparison component 231 is connected to the output terminal of the sampling module 1 (i.e., signal ADC_1), the output terminal of the comparison component 231 is connected to the input terminal of the latch component 232, and the output terminal of the latch component 232 outputs a signal OC and is connected to the cathode of the third diode D3 in the second semaphore signal generation unit 342.

[0063] In another preferred embodiment, such as Figure 11As shown, the comparator assembly 231 includes the 40th resistor R40, the 41st resistor R41, the 42nd resistor R42, the 43rd resistor R43, the 44th resistor R44, the 45th resistor R45, the 46th resistor R46, the 28th capacitor C28, the 29th capacitor C29, the 30th capacitor C30, the 31st capacitor C31, the 32nd capacitor C32, the 33rd capacitor C33, the 34th capacitor C34, the 35th capacitor C35, the fifth operational amplifier LM5, and the sixth operational amplifier LM6.

[0064] Specifically, the non-inverting input of the fifth operational amplifier LM5 is connected to 3.3Vref through the fortieth resistor R40 and to power ground AGND through the fortieth resistor R42 and the twenty-eighth capacitor C28 connected in parallel. The inverting input of the fifth operational amplifier LM5 is connected to the output of sampling module 1 (i.e. signal ADC_1) through the fortieth resistor R41, to power ground AGND through the twenty-ninth capacitor C29, and directly to the non-inverting input of the sixth operational amplifier LM6. The positive power supply of the fifth operational amplifier LM5 is connected to the first driving power supply 5VDDA and to power ground AGND through the thirtieth capacitor C30 and the thirty-first capacitor C31 connected in parallel. The negative power supply of the fifth operational amplifier LM5 is connected to power ground AGND.

[0065] The inverting input of the sixth operational amplifier LM6 is connected to 3.3Vref through the forty-third resistor R43 and to power ground AGND through the forty-fourth resistor R44 and the thirty-second capacitor C32 connected in parallel. The positive power supply of the sixth operational amplifier LM6 is connected to the first drive power supply 5VDDA and to power ground AGND through the thirty-third capacitor C33 and the thirty-fourth capacitor C34 connected in parallel. The negative power supply of the sixth operational amplifier LM6 is connected to power ground AGND. The output of the sixth operational amplifier LM6 is connected to the output of the fifth operational amplifier LM5.

[0066] The output of the fifth operational amplifier LM5 is connected to the second drive power supply 5VDDA through the forty-fifth resistor R45, to the input of the latch component 232 through the forty-sixth resistor R46, and to the power ground AGND in sequence through the forty-sixth resistor R46 and the thirty-fifth capacitor C35.

[0067] In one specific embodiment, the fifth operational amplifier LM5 and the sixth operational amplifier LM6 are selected from LMV393IDR.

[0068] In another specific embodiment, the latch component 232 includes a forty-seventh resistor R47, a forty-eighth resistor R48, a forty-ninth resistor R49, a fiftieth resistor R50, a fifty-first resistor R51, a thirty-sixth capacitor C36, and a seventh operational amplifier LM7, wherein the latch component 232 can maintain the state of the output signal of the comparator component 231.

[0069] Preferably, the non-inverting input of the seventh operational amplifier LM7 is connected to the output of the comparator component 231 and to the output of the seventh operational amplifier LM7 via the forty-seventh resistor R47. The inverting input of the seventh operational amplifier LM7 is connected to the latch clear signal Pro_Clear via the forty-eighth resistor R48 and to the power ground AGND via the forty-ninth resistor R49. The positive power supply of the seventh operational amplifier LM7 is connected to the first driving power supply 5VDDA. The negative power supply of the seventh operational amplifier LM7 is connected to the power ground AGND. The output of the seventh operational amplifier LM7 is connected to the second driving power supply 3.3VDDA via the fiftieth resistor R50, to the power ground AGND via the fifty-first resistor R51 and the thirty-sixth capacitor C36, and to the output signal OC via the fifty-first resistor R51 and connected to the cathode of the third diode D3 in the second blocking signal generation unit 342.

[0070] Specifically, the seventh operational amplifier LM7 is an LMV393IDR, the latch clear signal Pro_Clear is output by the host computer, and the latching time of the latch component 232 is determined by the timing of the host computer outputting the latch clear signal Pro_Clear.

[0071] In this application, the first comparison unit determines whether to perform wave blocking processing based on the rate of change of the signal generated by the target driving device, and the second comparison unit determines whether to perform wave blocking processing based on the instantaneous signal generated by the target driving device. The combination of the two achieves drive control of the target driving device, improving accuracy and reliability.

[0072] Please see Figure 12 , Figure 12 This is a second schematic diagram of a partial structure of the wave-blocking control unit provided in an embodiment of this application. For example... Figure 12 As shown, the wave blocking output unit 343 includes a driver chip U3, a signal output component 3430, a signal input component 3431, a thirty-seventh capacitor C37, and a thirty-eighth capacitor C38.

[0073] In this embodiment, the first enable pin OE1 of the driver chip U3 is connected to the output terminal (i.e., the input signal PWM_EN) of the second ripple signal generation unit 342. The first enable pin OE1 is used to control the input signal of the driver chip U3. The drive signal input pins of the driver chip U3 are respectively connected to the input drive signal and connected to the second drive power supply 3.3VDDA through the signal input component 3431. Specifically, the signal input component 3431 is a pull-up resistor. In a specific embodiment provided in this application, as shown... Figure 12 The driver chip U3 provides drive signal input pins A1 to A6. In addition, it provides input drive signals EPWM1 ​​to EPWM6 that correspond one-to-one with the drive signal input pins A1 to A6. The signal input component 3431 includes pull-up resistors R52 to R57 that correspond one-to-one with the drive signal input pins A1 to A6. Taking the drive signal input pin A1 of the driver chip U3 as an example, the drive signal input pin A1 of the driver chip U3 is connected to the corresponding input drive signal EPWM1 ​​and connected to the second drive power supply 3.3VDDA through the corresponding pull-up resistor R57.

[0074] The power supply pin VCC of the driver chip U3 is connected to the first driving power supply 5VDDA and to the power ground AGND through the 37th capacitor C37 and the 38th capacitor C38 connected in parallel. The drive signal output pin of the driver chip U3 is connected to the input terminal of the inverted logic driver module 4 and to the first driving power supply 5VDDA through the signal output component 3430. Specifically, the signal output component 3430 is a pull-up resistor. In a specific embodiment provided in this application, as shown... Figure 12 The driver chip U3 provides drive signal output pins Y1 to Y6, which correspond one-to-one with the drive signal input pins A1 to A6. In addition, it provides output drive signals EPWM_1 to EPWM_6, which also correspond one-to-one with the drive signal output pins Y1 to Y6. The signal output component 3430 includes pull-up resistors R58 to R63, which correspond one-to-one with the drive signal output pins Y1 to Y6. Taking the drive signal output pin Y1 of the driver chip U3 as an example, the drive signal output pin Y1 of the driver chip U3 outputs the corresponding output drive signal EPWM_1 and connects to the input terminal of the corresponding inverse logic drive module 4, and is connected to the first drive power supply 5VDDA through its corresponding pull-up resistor R58. In this application, the drive signal output pins provided by the driver chip U3 include multiple pins. Therefore, the protection circuit provided in this application provides an inverse logic drive module 4 corresponding to each drive signal output pin. That is, the number of output drive signals output by the inverse logic drive module 4 corresponds one-to-one with the number of output drive signals output by the driver chip U3. This part can be set according to actual needs.

[0075] The second enable pin of driver chip U3 is connected to the output terminal of the first cascade signal generation unit 341 (i.e., the input signal CBC_EN). The second enable pin OE2 is used to control the output signal of driver chip U3. The ground pin GND of driver chip U3 is connected to the power ground AGND, such as... Figure 12 In the illustrated embodiment, drive signal input pin A7 and drive signal input pin A8 are connected to power ground AGND, drive signal output pin Y7 is connected to power ground AGND through the sixty-fourth resistor R64, and drive signal output pin Y8 is connected to power ground AGND through the sixty-fifth resistor R65.

[0076] In one specific embodiment, the driver chip U3 is selected as SN74LV541ATPWR.

[0077] In a preferred embodiment, please refer to Figure 13 , Figure 13 A schematic diagram of the structure of an anti-logic driving module provided in an embodiment of this application is shown. Figure 13 As shown, the reverse logic drive module 4 includes a gate drive optocoupler U4, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a fourth diode D4, a fifth diode D5, and a fourth capacitor C4.

[0078] Specifically, the anode pin ANODE of the gate-driven optocoupler U4 is connected to one end of the twelfth resistor R12 and one end of the thirteenth resistor R13. The other end of the twelfth resistor R12 is connected to one end of the fourteenth resistor R14 and the cathode CATHODE of the gate-driven optocoupler U4. The fifteenth resistor R15 is connected in parallel between the other ends of the thirteenth resistor R13 and the fourteenth resistor R14. The other end of the thirteenth resistor R13 is also connected to the first driving power supply 5VDDA. The other end of the fourteenth resistor R14 is also connected to the output terminal of the blocking module (i.e., the output driving signal output by the blocking output unit).

[0079] The positive power supply pin VCC of the gate-driven optocoupler U4 is connected to the positive given voltage Drive_+15V. The output pin VOUT of the gate-driven optocoupler U4 is connected to one end of the sixteenth resistor R16 and one end of the seventeenth resistor R17. The other end of the sixteenth resistor R16 is connected to the cathode of the fourth diode D4. The other end of the seventeenth resistor R17 is connected to the anode of the fourth diode D4, and then connected to the cathode of the fifth diode D5, one end of the fourth capacitor C4, and the gate driving terminal Drive_1_G of the target driving device. The anode of the fifth diode D5 is connected to the off negative voltage DRIVE_INV_-5V. The other end of the fourth capacitor C4 is connected to the source terminal Drive_1_S of the target driving device through the eighteenth resistor R18. The nineteenth resistor R19 is connected in parallel between the gate driving terminal Drive_1_G and the source terminal Drive_1_S of the target driving device. The negative power supply pin VEE of the gate-driven optocoupler U4 is connected to the negative given voltage Drive_-5V.

[0080] In one specific embodiment, the gate drive optocoupler U4 is selected as UCC23513DWYR. The turn-off negative voltage DRIVE_INV_-5V is connected to the gate terminal of the target driving device through the fifth diode to prevent the target driving device from having too low a voltage when turned off.

[0081] In this application, the target driving device is a driving structure that internally achieves switching via a field-effect transistor.

[0082] In another preferred embodiment, such as Figure 13 As shown, the reverse logic drive module 4 also includes a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a twentieth resistor R20, a twenty-first resistor R21, and a Zener diode TVS. One end of the fifth capacitor C5 is connected to one end of the sixth capacitor C6, one end of the twentieth resistor R20, and one end of the twenty-first resistor R21, and is connected to a positive given voltage Drive_+15V. The other end of the fifth capacitor C5 is connected to the other end of the sixth capacitor C6, the other end of the twentieth resistor R20, the other end of the twenty-first resistor R21, one end of the seventh capacitor C7, one end of the eighth capacitor C8, and the cathode of the Zener diode TVS, and is connected to the source terminal Drive_1_S of the target drive device. The other end of the seventh capacitor C7, the other end of the eighth capacitor C8, and the anode of the Zener diode TVS are connected to a negative given voltage Drive_-5V.

[0083] In one specific embodiment, the protection circuit provided in this application operates as follows:

[0084] The main drive signal I_VIOUT generated by the target drive device is acquired by the sampling module 1, and after processing by the sampling module, the output signal ADC_1 is output. The signal ADC_1 is input to the differentiating unit 21 and the second comparison unit 23 respectively.

[0085] Differentiating unit 21 processes signal ADC_1 to obtain signal Diff_ADC reflecting the rate of change of the main driving signal and inputs it into first comparison unit 22. First comparison unit 22 compares signal Diff_ADC with first given reference signal 3.3Vref and finally outputs signal CBC.

[0086] For the signal Diff_ADC input to the first comparison unit 22, part of the signal processing is as follows: when the signal Diff_ADC is lower than the first given reference signal, the signal CBC is high and output to the sealing period adjustment unit 31 and the counting unit 32. In this case:

[0087] The counting unit 32 does not perform the counting operation. The counting unit 32 outputs a low level to the trigger unit 33. The third control switch K3 in the trigger unit 33 is not turned on. The output signal Count_pwm of the trigger unit 33 is high level. The signal Count_pwm is input to the second semaphore signal generation unit 342.

[0088] When the sealing cycle adjustment unit 31 detects that CBC is high, its corresponding output signal Fault_CBC is low and is input to the sealing trigger component 311. The fourth control switch K4 in the sealing trigger component 311 is cut off when Fault_CBC is low, and its output signal Fault_EN is high and is input to the first sealing signal generation unit 341. The first control switch in the first sealing signal generation unit 341 is turned on when the signal Fault_EN is high, and the output signal CBC_EN of the first sealing signal generation unit 341 is low and is input to the second enable pin OE2 of the driver chip U3.

[0089] For the signal ADC_1 input to the second comparison unit 23, part of the signal processing is as follows: the signal ADC_1 is compared with the first given reference signal 3.3Vref by the second comparison unit 23. When the signal ADC_1 is lower than the first given reference signal 3.3Vref, the comparison component 231 outputs a high-level signal to the latch component 232. Under the latching action of the latch component 232, the second comparison unit 23 maintains the high-level output of the signal OC, and the signal OC is input to the second blocking signal generation unit 342.

[0090] At this time, the second sealing signal generation unit 342 detects that both signal OC and signal Count_pwm are high-level signals, and the corresponding second control switch K2 is turned on. The output signal PWM_EN is low-level, and signal PWM_EN is input to the first enable pin OE1 of the driver chip (the first enable pin OE1 is active low).

[0091] The first enable pin OE1 of the driver chip U3 detects that the signal PWM_EN is low, and maintains the corresponding input drive signal of the driver chip U3. The second enable pin OE2 of the driver chip U3 detects that the signal CBC_EN is low, and maintains the corresponding output drive signal of the driver chip U3.

[0092] For the signal Diff_ADC input to the first comparison unit 22, another part of the signal processing is as follows: when the signal Diff_ADC is higher than the first given reference signal 3.3Vref, the signal CBC is low and output to the sealing period adjustment unit 31 and the counting unit 32. In this case:

[0093] When the counting unit 32 detects a falling edge of CBC, the counting chip U2 performs a counting operation. Each time a falling edge is generated, the counting chip U2 performs a count. When the counting count of the counting chip U2 is equal to 8, the signal Count output by the fourth output pin 1QD of the counting chip U2 is pulled high and maintained. The signal Count is input to the trigger unit 33. The third control switch K3 in the trigger unit 33 is turned on when the signal Count is high. The signal Count_pwm output by the trigger unit 33 is pulled low and input to the second semaphore signal generation unit 342.

[0094] When the sealing period adjustment unit 31 detects that CBC is low, its corresponding output signal Fault_CBC changes from low to high for a predetermined time period and then returns to low. The fourth control switch K4 in the sealing trigger component 311 is turned on when Fault_CBC is high, and its output signal Fault_EN is low and input to the first sealing signal generation unit 341. The first control switch K1 in the first sealing signal generation unit 341 is turned off when the signal Fault_EN is low. The output signal CBC_EN of the first sealing signal generation unit 341 is high and is input to the second enable pin OE2 of the driver chip U3.

[0095] For the signal ADC_1 input to the second comparison unit 23, another part of the signal processing is as follows: the signal ADC_1 is compared with the first given reference signal 3.3Vref by the second comparison unit 23. When the signal ADC_1 is higher than the first given reference signal 3.3Vref, the comparison component 231 outputs a low-level signal to the latch component 232. Under the latching action of the latch component 232, the second comparison unit 23 maintains the low-level output of the signal OC, and the signal OC is input to the second semaphore signal generation unit 342.

[0096] At this time, the second sealing signal generation unit 342 detects that both signal OC and signal Count_pwm are low-level signals, and the corresponding second control switch K2 is turned off. The output signal PWM_EN is high-level, and signal PWM_EN is input to the first enable pin OE1 of the driver chip (the first enable pin OE1 is active low).

[0097] When the first enable pin OE1 of the driver chip U3 detects that the signal PWM_EN is high, it turns off the corresponding input drive signal of the driver chip U3. When the second enable pin OE2 of the driver chip U3 detects that the signal CBC_EN is high, it turns off the corresponding output drive signal of the driver chip U3.

[0098] Preferably, in this application, for the signal CBC_EN received by the second enable pin OE2 of the driver chip U3, if either the signal OC or the signal Count_pwm is at a low level in the second shielding signal generation unit 342, then the signal CBC_EN will be at a high level, that is, the driver chip U3 will turn off the corresponding output drive signal.

[0099] In this application, any enable pin of the driver chip U3 can be turned off when its output drive signal is at a high level. Furthermore, when there is no drive signal input or output, the reverse logic drive module 4 turns off the target drive device to prevent it from being damaged. The target drive device is a power drive device.

[0100] The advantages of this application are:

[0101] Increase the reliability of protection for power drive devices to avoid malfunctions or failure to trigger protection in time when power drive devices are in overvoltage or overcurrent operating conditions, which could lead to personal and property safety issues.

[0102] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A protection circuit, characterized in that, The protection circuit includes a sampling module, a comparison module, a blocking module, and an inverse logic driving module. The sampling module's input is connected to the signal acquisition terminal of the target driver device, the sampling module's output is connected to the input of the comparison module, the comparison module's output is connected to the input of the blocking module, the blocking module's output is connected to the input of the inverted logic driver module, the inverted logic driver module's first output is connected to the target driver device's gate control terminal, and the inverted logic driver module's second output is connected to the target driver device's source terminal.

2. The protection circuit according to claim 1, characterized in that, The comparison module includes a differentiation unit, a first comparison unit, and a second comparison unit. The output of the sampling module is connected to the input of the differentiating unit and the input of the second comparison unit. The output of the differentiating unit is connected to the input of the first comparison unit. The outputs of the first comparison unit and the second comparison unit are connected to different inputs of the blocking module. The output of the blocking module is connected to the output of the inverse logic driving module.

3. The protection circuit according to claim 2, characterized in that, The wave blocking module includes a wave blocking period adjustment unit, a counting unit, a triggering unit, and a wave blocking control unit. The output of the first comparison unit is connected to the input of the sealing period adjustment unit and the input of the counting unit, respectively. The output of the counting unit is connected to the input of the trigger unit, and the output of the trigger unit is connected to the first input of the sealing control unit. The output of the wave sealing period adjustment unit is connected to the second input of the wave sealing control unit; The output of the second comparison unit is connected to the third input of the wave-blocking control unit; The output of the wave blocking control unit is connected to the output of the reverse logic drive module.

4. The protection circuit according to claim 3, characterized in that, The sealing control unit includes a first sealing signal generation unit, a second sealing signal generation unit, and a sealing output unit. The input terminal of the first sealing signal generation unit is connected to the output terminal of the sealing period adjustment unit, and the output terminal of the first sealing signal generation unit is connected to the first enable terminal of the sealing output unit. The input terminal of the second sealing signal generation unit is connected to the output terminal of the trigger unit and the output terminal of the second comparison unit, respectively, and the output terminal of the second sealing signal generation unit is connected to the second enable terminal of the sealing output unit. The output terminal of the wave blocking output unit is connected to the output terminal of the inverse logic drive module.

5. The protection circuit according to claim 3, characterized in that, The wave blocking period adjustment unit includes a timer chip, a first resistor, a first capacitor, a second capacitor, and a wave blocking trigger component. The timer chip's ground pin is connected to the power supply ground; the timer chip's trigger input pin is connected to the output of the first comparator unit; the timer chip's output pin is connected to the input of the wave blocking trigger component; the output of the wave blocking trigger component is connected to the input of the first wave blocking signal generation unit; the timer chip's reset input pin is connected to the first drive power supply; the timer chip's control voltage input pin is connected to the power supply ground through the first capacitor; the timer chip's threshold input pin is connected to the timer chip's discharge pin, and then connected to the power supply ground through the second capacitor and to the first drive power supply through the first resistor, respectively; and the timer chip's power supply input pin is connected to the first drive power supply.

6. The protection circuit according to claim 3, characterized in that, The counting unit includes a counting chip, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a third capacitor. The counting trigger signal input pin of the counting chip is connected to the output of the first comparison unit. The clear input pin of the counting chip is connected to one end of the second resistor, one end of the third capacitor, and the count clear signal, respectively. The ground pin of the counting chip is connected to the other end of the second resistor, the other end of the third capacitor, and the power ground, respectively. The first output of the counting chip is connected to the power ground through the third resistor. The second output of the counting chip is connected to the power ground through the fourth resistor. The third output of the counting chip is connected to the power ground through the fifth resistor. The fourth output of the counting chip is connected to the input of the trigger unit.

7. The protection circuit according to claim 4, characterized in that, The first wave signal generation unit includes a first diode, a sixth resistor, a seventh resistor, an eighth resistor, and a first control switch. The output terminal of the wave blocking cycle adjustment unit is connected to the cathode of the first diode. The anode of the first diode is connected to the control terminal of the first control switch through the sixth resistor and to the first connection terminal of the first control switch through the sixth resistor and the seventh resistor. The second connection terminal of the first control switch is connected to the first driving power supply and the first enable terminal of the wave blocking output unit through the eighth resistor. The first connection terminal of the first control switch is also connected to the power ground.

8. The protection circuit according to claim 4, characterized in that, The second wave signal generation unit includes a second diode, a third diode, a ninth resistor, a tenth resistor, an eleventh resistor, and a second control switch. The cathode of the second diode is connected to the output terminal of the trigger unit, the cathode of the third diode is connected to the output terminal of the second comparator unit, and the anodes of the second and third diodes are connected to the control terminal of the second control switch through the ninth resistor and the first connection terminal of the second control switch through the ninth and tenth resistors, respectively. The first connection terminal of the second control switch is also connected to the power ground, and the second connection terminal of the second control switch is connected to the first drive power supply and the second enable terminal of the blocking output unit through the eleventh resistor, respectively.

9. The protection circuit according to claim 4, characterized in that, The wave blocking output unit includes a driver chip, a signal output component, and a signal input component. The first enable pin of the driver chip is connected to the output of the second semaphore signal generation unit. The drive signal input pin of the driver chip is connected to the input drive signal and to the second drive power supply through the signal input component. The power supply pin of the driver chip is connected to the first drive power supply. The drive signal output pin of the driver chip is connected to the input of the inverted logic drive module and to the first drive power supply through the signal output component. The second enable pin of the driver chip is connected to the output of the first semaphore signal generation unit. The ground pin of the driver chip is connected to the power ground.

10. The protection circuit according to claim 1, characterized in that, The reverse logic drive module includes a gate drive optocoupler, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a fourth diode, a fifth diode, and a fourth capacitor. Among them, the anode pin of the gate drive optocoupler is connected to one end of the twelfth resistor and one end of the thirteenth resistor. The other end of the twelfth resistor is connected to one end of the fourteenth resistor and the cathode of the gate drive optocoupler. The fifteenth resistor is connected in parallel between the other ends of the thirteenth resistor and the fourteenth resistor. The other end of the thirteenth resistor is also connected to the first drive power supply. The other end of the fourteenth resistor is also connected to the output terminal of the wave blocking module. The positive power supply pin of the gate-driven optocoupler is connected to the positive given voltage. The output pin of the gate-driven optocoupler is connected to one end of the sixteenth resistor and one end of the seventeenth resistor, respectively. The other end of the sixteenth resistor is connected to the cathode of the fourth diode. The other end of the seventeenth resistor is connected to the anode of the fourth diode, and then connected to the cathode of the fifth diode, one end of the fourth capacitor, and the gate driving terminal of the target driving device, respectively. The anode of the fifth diode is connected to DRIVE_INV_-5V. The other end of the fourth capacitor is connected to the source terminal of the target driving device through the eighteenth resistor. The nineteenth resistor is connected in parallel between the gate driving terminal and the source terminal of the target driving device. The negative power supply pin of the gate-driven optocoupler is connected to a negative given voltage.

11. The protection circuit according to claim 10, characterized in that, The reverse logic driving module also includes a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a twentieth resistor, a twenty-first resistor, and a Zener diode. One end of the fifth capacitor is connected to one end of the sixth capacitor, one end of the twentieth resistor, and one end of the twenty-first resistor, and then connected to the positive given voltage. The other end of the fifth capacitor is connected to the other end of the sixth capacitor, the other end of the twentieth resistor, the other end of the twenty-first resistor, one end of the seventh capacitor, one end of the eighth capacitor, and the cathode of the Zener diode, and then connected to the source terminal of the target driving device. The other end of the seventh capacitor, the other end of the eighth capacitor, and the anode of the Zener diode are connected to the negative given voltage.

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