Power semiconductor device and electronic equipment
By configuring multiple chips in the upper and lower transistors of the inverter bridge arm and maintaining equal distance when connected in parallel, the complex manufacturing process and module balance issues in the existing technology are solved, realizing a low-complexity power semiconductor device that can meet the needs of different current and voltage platforms.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- WEICHAI POWER CO LTD
- Filing Date
- 2025-03-07
- Publication Date
- 2026-04-24
AI Technical Summary
When existing power semiconductor device modules are connected in parallel, the manufacturing process is complex and the requirements for module balancing performance are strict, making it difficult to adapt to the needs of different current and voltage platforms.
The inverter bridge arm upper and lower transistors are designed with multiple upper and lower transistor chips respectively. When connected in parallel, the distance between the drain and source terminals of each chip is kept equal. They are connected by parallel distribution and welding or silver sintering methods, which simplifies the manufacturing process and improves current sharing consistency.
It reduces the manufacturing complexity of power systems, improves system reliability and adaptability, and can meet the needs of different current and voltage platforms.
Smart Images
Figure CN224164786U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, specifically to a power semiconductor device and electronic device. Background Technology
[0002] Power semiconductor devices are semiconductor devices that can withstand large currents and high voltages. They are mainly used in high-power (usually referring to currents of tens to thousands of amperes and voltages of hundreds of volts and above) electronic devices in power conversion and power control circuits.
[0003] Figure 1 This is a schematic diagram of a power semiconductor device packaging and power system design scheme in the prior art. Figure 1 In this design, 602 is the upper inverter arm transistor, and 604 is the lower inverter arm transistor. The upper and lower transistors have identical packages. AC output is from the middle (628 and 614). The power devices and DC bus copper busbars (606 and 608) form a stack, reducing the parasitic inductance of the entire power system. However, this design has a drawback: each module can only package one chip. When different current and voltage platforms are required, connecting too many modules in parallel increases the complexity of the manufacturing process and the requirements for module balancing performance. Utility Model Content
[0004] In view of this, the present invention provides a power semiconductor device and an electronic device, thereby providing a power semiconductor device with low complexity.
[0005] To achieve the above objectives, the present invention provides the following technical solutions:
[0006] A power semiconductor device, comprising:
[0007] Inverter bridge arm upper diode and inverter bridge arm lower diode;
[0008] The upper transistor of the inverter bridge arm is encapsulated with an upper transistor D-terminal connection terminal and an upper transistor S-terminal connection terminal, and the lower transistor of the inverter bridge arm is encapsulated with a lower transistor first D-terminal connection terminal, a lower transistor second D-terminal connection terminal and a lower transistor S-terminal connection terminal.
[0009] The upper transistor chip corresponding to the upper transistor of the inverter bridge arm and the lower transistor chip corresponding to the lower transistor of the inverter bridge arm are fixed on the substrate. The S-pole of the upper transistor chip is connected to the S-pole connection terminal of the upper transistor, and the S-pole of the lower transistor chip is connected to the S-pole connection terminal of the lower transistor.
[0010] Each inverter bridge arm upper tube corresponds to N upper tube chips, where N is a positive integer not less than 1. The N upper tube chips are distributed in parallel on the inverter bridge arm upper tube, and the distance between the drain (D) terminal of each upper tube chip and the drain terminal of the upper tube is equal, and the distance between the source (S) terminal of each upper tube chip and the source terminal of the upper tube is equal.
[0011] Each inverter bridge arm lower transistor corresponds to N lower transistor chips. The N lower transistor chips are distributed in parallel on the inverter bridge arm lower transistor. The distance between the drain (D) terminal of each lower transistor chip and the first drain terminal of the lower transistor is equal. The distance between the drain (D) terminal of each lower transistor chip and the second drain terminal of the lower transistor is equal. The distance between the source (S) terminal of each lower transistor chip and the source terminal of the lower transistor is equal.
[0012] Optionally, in the above power semiconductor device, the value of N is 1, 2, 3 or greater than or equal to 4.
[0013] Optionally, in the above-mentioned power semiconductor device, the inverter bridge arm upper transistor further includes:
[0014] The upper tube ceramic substrate has a first copper plating layer, a second copper plating layer, and a ceramic layer.
[0015] The upper tube ceramic substrate is disposed between the first copper layer and the second copper layer of the upper tube ceramic substrate;
[0016] The upper tube of the inverter bridge arm is disposed on the first copper layer of the ceramic substrate of the upper tube.
[0017] Optionally, in the above power semiconductor device, the drain (D) of the upper transistor chip is connected to the upper transistor drain terminal via the upper transistor connecting conductor and the metal in the first copper-clad layer of the upper transistor ceramic substrate.
[0018] The S-pole of the upper transistor chip is connected to the S-pole connection terminal of the upper transistor through the upper transistor S-pole terminal connection conductor;
[0019] The gate (G) terminals on each of the aforementioned upper transistor chips are connected to the upper transistor's gate terminal terminal via a gate connection conductor.
[0020] Optionally, in the above-mentioned power semiconductor device, the inverter bridge arm upper transistor further includes:
[0021] The upper tube K-terminal terminal is connected to the upper tube S-terminal terminal via the upper tube K-terminal connecting conductor;
[0022] The inverter bridge arm includes a first temperature monitoring terminal, a second temperature monitoring terminal, and a temperature detection element. The first and second temperature monitoring terminals are connected to both ends of the temperature detection element. The temperature detection element is used to detect the temperature of the inverter bridge arm's upper tube through the first and second temperature monitoring terminals.
[0023] The upper tube's drain (D) detection terminal is used to detect the voltage at the drain (D) of the upper tube.
[0024] Optionally, in the above-mentioned power semiconductor device, the lower transistor of the inverter bridge arm further includes:
[0025] The first copper plating layer of the lower tube ceramic substrate, the second copper plating layer of the lower tube ceramic substrate, and the ceramic layer of the lower tube ceramic substrate;
[0026] The lower tube ceramic substrate is disposed between the first copper layer and the second copper layer of the lower tube ceramic substrate;
[0027] The inverter bridge arm lower tube is disposed on the first copper layer of the lower tube ceramic substrate.
[0028] Optionally, in the above-mentioned power semiconductor device, the drain (D) terminal of the lower transistor chip is connected to the first drain (D) terminal and the second drain (D) terminal of the lower transistor through the lower transistor connecting conductor and the metal in the first copper-clad layer of the lower transistor ceramic substrate.
[0029] The S-pole of the lower transistor chip is connected to the S-pole connection terminal of the lower transistor through the lower transistor S-pole terminal connection conductor;
[0030] The gate (G) terminals on each of the lower transistor chips are connected to the lower transistor's gate terminal terminal via a gate connection conductor.
[0031] Optionally, in the above-mentioned power semiconductor device, the lower transistor of the inverter bridge arm further includes:
[0032] The lower tube K-terminal is connected to the lower tube S-terminal via a lower tube K-terminal connecting conductor.
[0033] The inverter bridge arm includes a first temperature monitoring terminal for the lower tube, a second temperature monitoring terminal for the lower tube, and a temperature detection element for the lower tube. The first temperature monitoring terminal for the lower tube and the second temperature monitoring terminal for the lower tube are connected to both ends of the temperature detection element for the lower tube. The temperature detection element for the lower tube is used to detect the temperature of the lower tube of the inverter bridge arm through the first temperature monitoring terminal for the lower tube and the second temperature monitoring terminal for the lower tube.
[0034] The lower diode drain (D) detection terminal is used to detect the voltage at the drain (D) of the lower diode.
[0035] An electronic device comprising: any one of the power semiconductor devices described above.
[0036] Optionally, the electronic device is a household appliance or a car.
[0037] Based on the above technical solution, the power semiconductor device provided in this utility model embodiment includes: an upper inverter bridge arm transistor and a lower inverter bridge arm transistor; the upper inverter bridge arm transistor is packaged with an upper transistor drain (D) terminal and an upper transistor source (S) terminal, and the lower inverter bridge arm transistor is packaged with a lower transistor first drain (D) terminal, a lower transistor second drain (D) terminal, and a lower transistor source (S) terminal; the upper transistor chip corresponding to the upper inverter bridge arm transistor and the lower transistor chip corresponding to the lower inverter bridge arm transistor are fixed on a substrate, the source (S) terminal of the upper transistor chip is connected to the upper transistor source (S) terminal, and the source (S) terminal of the lower transistor chip is connected to the lower transistor source (S) terminal; and Furthermore, each inverter bridge arm upper transistor corresponds to N upper transistor chips, where N is a positive integer not less than 1. The distance between the drain (D) terminal and the drain terminal connection terminal of each upper transistor chip is equal, and the distance between the source (S) terminal and the source terminal connection terminal of each upper transistor chip is equal. Similarly, each inverter bridge arm lower transistor corresponds to N lower transistor chips. The distance between the drain (D) terminal and the first drain terminal connection terminal of each lower transistor chip is equal, the distance between the drain (D) terminal and the second drain terminal connection terminal of each lower transistor chip is equal, and the distance between the source (S) terminal and the source terminal connection terminal of each lower transistor chip is equal. Therefore, in this solution, multiple upper and lower transistor chips can be configured simultaneously for both inverter bridge arm upper and lower transistors, allowing the power semiconductor devices to adapt to different current and voltage platforms. Attached Figure Description
[0038] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0039] Figure 1 This is a schematic diagram of a power semiconductor device packaging and power system design scheme disclosed in the prior art;
[0040] Figure 2 The circuit topology diagram of the existing inverter main power system;
[0041] Figure 3 This is a schematic diagram of the circuit symbol for an IGBT.
[0042] Figure 4 This is a schematic diagram of the IGBT chip structure;
[0043] Figure 5This is a schematic diagram of the electrical symbol for a MOSFET.
[0044] Figure 6 This is a schematic diagram of the MOSFET chip structure;
[0045] Figure 7a This is a schematic diagram of the upper-side chip layout provided in an embodiment of this application;
[0046] Figure 7b This is a schematic diagram of the upper transistor chip's packaging.
[0047] Figure 8a This is a schematic diagram of the lower-side MOSFET chip layout provided in an embodiment of this application;
[0048] Figure 8b This is a schematic diagram of the packaging of the lower-side transistor chip;
[0049] Figures 9a-9d This is a schematic diagram of various upper-side chip layouts provided in another embodiment of this application;
[0050] Figures 10a-10d This is a schematic diagram of various bottom-side MOSFET chip layouts provided for another embodiment of this application. Detailed Implementation
[0051] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0052] First, the relevant terms in this application will be explained:
[0053] Power electronic devices: devices that can convert and control electrical energy, consisting of power semiconductor devices, passive devices (inductors, capacitors), structural components, heat dissipation systems, and control devices.
[0054] Power system: The system consisting of the high-voltage, high-power part of the power electronic converter device, mainly including power semiconductor devices, passive devices (inductors or capacitors), and electrical connection components (such as copper busbars, wires, etc.).
[0055] Power semiconductor chips: made of semiconductor materials such as silicon (Si), silicon carbide (SiC), and gallium nitride (GaN), they can convert and control electrical energy through rapid switching on and off. They mainly include IGBTs (generally made of Si), MOSFETs (generally made of Si, SiC, or GaN), and diodes (made of Si or SiC). This application refers to them as "chips".
[0056] Power semiconductor packaging: Power semiconductor chips cannot be used directly. They must be installed inside a module through a series of processes to achieve functions such as chip-to-chip connectivity, external electrical connections, heat dissipation, and chip protection (insulation, waterproofing, dustproofing, oxidation prevention, and mechanical damage prevention). The structure of this module is called power semiconductor packaging. In this application, it is referred to as "packaging".
[0057] Power semiconductor device: A module consisting of a power semiconductor chip and a power semiconductor package is called a power semiconductor device. In this application, it is referred to as "device".
[0058] Inverter: A power electronic device that converts direct current (DC) to alternating current (AC). Its main power system is as follows: Figure 2 As shown. Figure 2 The left side shows the DC input of the inverter, which is typically a DC power source such as a battery. Figure 2 The AC output is on the right. The inverter consists of three-phase inverter arms. Power semiconductor devices S1 and S2 (MOSFETs shown in the diagram) form the A-phase inverter arm. S1 is the upper transistor of the inverter arm, and its drain (D) terminal is connected to the DC+ bus. S2 is the lower transistor of the inverter arm, and its source (S) terminal is connected to the DC- bus. Point A is the connection point between the source terminal of S1 and the drain terminal of S2, which is the AC output point of the A-phase inverter arm. S1 and S2 alternately and complementaryly conduct, allowing AC voltage to be output at point A. Similarly, the working principle of phases B and C is the same.
[0059] IGBT: Insulated Gate Bipolar Transistor is a power semiconductor device, its symbol is as follows: Figure 3 and Figure 4 As shown, an IGBT has three terminals: the collector (C), the emitter (E), and the gate (G). When the voltage between the gate and the emitter exceeds a certain value (threshold voltage), the IGBT conducts, and current can flow from the collector to the emitter, but it cannot conduct in the reverse direction. To provide a path for reverse conduction, a diode is typically connected in anti-parallel to the IGBT.
[0060] MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor (FET) is a power semiconductor device, its symbol is shown below. Figure 5 and Figure 6As shown, a MOSFET has three terminals: drain (D), source (S), and gate (G). When the voltage between the gate and source exceeds a certain value (threshold voltage), the MOSFET turns on, and current can flow from the drain to the source. Due to the structure of the MOSFET, it has a parasitic diode, so current can flow from the source to the drain regardless of whether the MOSFET is in the on state.
[0061] Figure 7a , Figure 7b , Figure 8a and Figure 8b , Figure 7a and Figure 7b This is a schematic diagram of the upper transistor 200 in the inverter bridge arm of a power semiconductor device. Figure 8a and Figure 8b This application discloses a power semiconductor device, including: (The diagram shows the structure of the lower inverter arm transistor 300 in the power semiconductor device.)
[0062] The inverter bridge arm includes upper transistor 200 and lower transistor 300. Upper transistor 200 refers to the power switch located on the upper arm of the inverter bridge. During inverter operation, upper transistor 200 and lower transistor 300 alternately turn on and off to convert DC to AC power. This conversion process requires precise control logic and timing to ensure the correctness and stability of the output waveform. Lower transistor 300 is located on the lower arm of the inverter bridge and works in conjunction with the power switch on the upper arm to complete the power conversion task. Similar to upper transistor 200, the gate of lower transistor 300 also receives drive signals from the controller. However, the on and off states of lower transistor 300 are opposite to those of upper transistor 200.
[0063] See Figure 7a , Figure 7b The inverter bridge arm upper transistor 200 has two electrical connection terminals: a drain (D) connection terminal 202 and a source (S) connection terminal 211. (See [reference]) Figure 8a and Figure 8b The inverter bridge arm lower tube 300 is encapsulated with three electrical connection terminals, namely the lower tube first D pole connection terminal 302, the lower tube second D pole connection terminal 314, and the lower tube S pole connection terminal 311.
[0064] The upper transistor chip 209 corresponding to the upper transistor 200 of the inverter bridge arm and the lower transistor chip 309 corresponding to the lower transistor 300 of the inverter bridge arm are both fixed on their respective substrates. Specifically, the upper transistor chip 209 is fixed on the upper transistor ceramic substrate 208, and the lower transistor chip 309 is fixed on the lower transistor ceramic substrate 308. The S-terminal of the upper transistor chip 209 is connected to the upper transistor S-terminal connection terminal 211 through the upper transistor S-terminal terminal connecting conductor 210, and the S-terminal of the lower transistor chip 309 is connected to the lower transistor S-terminal connection terminal 311 through the lower transistor S-terminal terminal connecting conductor 310.
[0065] Each inverter bridge arm upper tube 200 can correspond to N upper tube chips 209, where N is a positive integer not less than 1. Users can set the number of upper tube chips 209 according to actual needs. In this solution, in order to facilitate connection and heat dissipation, the N upper tube chips 209 are distributed in parallel on the inverter bridge arm upper tube 200, and each upper tube chip 209 is connected in parallel with each other.
[0066] Furthermore, to achieve a balanced design of the parallel electrical connection impedance of the upper transistor chips 209, in the upper transistors of the inverter bridge arm, the distance between the drain (D) terminal of each upper transistor chip 209 and the drain connection terminal 202 is equal. This ensures that the connection impedance between the drain terminals of all upper transistor chips 209 and the drain connection terminal 202 is equal. Similarly, in the upper transistors of the inverter bridge arm, the distance between the source (S) terminal of each upper transistor chip 209 and the source connection terminal 211 is equal. This ensures that the connection impedance between the source terminals of all upper transistor chips 209 and the source connection terminal 211 is equal. This arrangement of the upper transistor chips 209 and the design of the electrical connection terminals achieve a balanced design of the parallel electrical connection impedance of the upper transistor chips 209, improving the current sharing consistency among the upper transistor chips 209.
[0067] To achieve a balanced design of the parallel electrical connection impedance of the lower transistor chips 309, each inverter bridge arm lower transistor 300 corresponds to N lower transistor chips 309, where N is a positive integer not less than 1. The distance between the drain (D) terminal of each lower transistor chip 309 and the first drain terminal connection terminal 302 is equal. Similarly, the distance between the drain (D) terminal of each lower transistor chip 309 and the second drain terminal connection terminal 314 is equal. Furthermore, the distance between the source (S) terminal of each lower transistor chip 309 and the source terminal connection terminal 311 is equal. This achieves a balanced design of the parallel electrical connection impedance of the lower transistor chips 309.
[0068] In the above-disclosed scheme of this application embodiment, the lower surfaces of N upper-side chips 209 are distributed in parallel and fixed on the upper-side ceramic substrate 208 by welding or silver sintering. The S-pole of the upper surface of the upper-side chip 209 is connected in parallel to the upper-side S-pole connection terminal 211 through the upper-side S-pole terminal connecting conductor 210, and the N upper-side chips 209 can share one upper-side S-pole terminal connecting conductor 210, so that the distance from the S-pole of all upper-side chips 209 to the upper-side S-pole connection terminal 211 is equal. The lower surface of the lower-side chip 309 is fixed on the lower-side ceramic substrate 308 by welding or silver sintering. The S-pole of the upper surface of the lower-side chip 309 is connected in parallel to the lower-side S-pole connection terminal 311 through the lower-side S-pole terminal connecting conductor 310, and the N lower-side chips 309 can share one lower-side S-pole terminal connecting conductor 310, so that the distance from the S-pole of all lower-side chips 309 to the lower-side S-pole connection terminal 311 is equal.
[0069] In the technical solution disclosed in this embodiment, the power semiconductor device can be customized with different numbers N of upper-side transistor chips 209 and lower-side transistor chips 309 according to the design requirements of the current and voltage platform. That is, the number N of upper-side transistor chips 209 and lower-side transistor chips 309 in the power semiconductor device can be configured according to the design requirements. By directly customizing different upper-side transistor chips 209 and lower-side transistor chips 309 according to the design requirements of the current and voltage platform, these upper-side transistor chips 209 and lower-side transistor chips 309 are distributed in parallel on the substrate, reducing the complexity of subsequent power system packaging and improving the overall system reliability. Figures 9a-9d and Figures 10a-10d As shown, Figures 9a-9d and Figures 10a-10d These are schematic diagrams showing the layout of upper and lower transistor chips with different numbers of upper and lower transistor chips, respectively. The value of N can be 1, 2, 3, or greater than or equal to 4. See [link to diagram]. Figures 9a-9d The power semiconductor device may have one, two, three, or more than four upper-side transistor chips, see [link to relevant documentation]. Figures 10a-10d The power semiconductor device may have one, two, three or more, or more than four lower transistor chips. The connection methods of each upper transistor chip and lower transistor chip with other components or ports may be the same, as described above.
[0070] In this embodiment, when the upper tube D terminal 202, the lower tube S terminal, and the lower tube D second terminal 314 in the power semiconductor device are connected to the DC copper busbar and the AC copper busbar, they can be connected by welding. The welding process is easy to implement, reduces the design difficulty of the power system, and simplifies the production process.
[0071] In this embodiment, the inverter bridge arm upper transistor in the power semiconductor device is disposed on an upper transistor substrate. The upper transistor substrate may include: a first copper plating layer 205, a second copper plating layer 207, and a ceramic layer 206. The ceramic layer 206 is disposed between the first copper plating layer 205 and the second copper plating layer 207. The inverter bridge arm upper transistor is disposed on the first copper plating layer 205, and the first copper plating layer 205 provides connection wires for the connection between the upper transistor chip 209 and each port.
[0072] In this embodiment, the connection method between each pole (D, S, G) of the upper transistor chip 209 and each terminal in the upper transistor of the inverter bridge arm is also disclosed. Specifically, the D pole of the upper transistor chip is connected to the upper transistor D pole connection terminal 202 through the upper transistor D pole terminal connection conductor 203 and the metal line in the first copper layer of the upper transistor ceramic substrate; the S pole of the upper transistor chip 209 is connected to the upper transistor S pole connection terminal 211 through the upper transistor S pole terminal connection conductor 210; the G poles 213 on each of the upper transistor chips 209 are connected to the upper transistor G pole terminal 215 in sequence through the upper transistor chip G pole connection conductor 214, see [link to documentation]. Figure 7a , Figure 7b As shown, the G poles 213 on each pair of upper-side chips 209 are connected by an upper-side chip G pole connecting conductor 214. The G pole 213 on the upper-side chip 209 closest to the upper-side G pole terminal 215 is then connected to the upper-side G pole terminal 215 through the upper-side chip G pole connecting conductor 214. In this case, it can be considered that the G poles 213 on each upper-side chip 209 are directly connected to the upper-side G pole terminal 215.
[0073] In addition to having a drain (D) terminal 202, a sink (S) terminal 211, and a gate (G) terminal 215, the inverter bridge arm upper transistor also includes a gate (K) terminal 216, a first temperature monitoring terminal 218, a second temperature monitoring terminal 220, a temperature sensing element 219, and a drain (D) terminal 221. The gate (K) terminal 216 is connected to the sink (S) terminal 211 via a gate (K) terminal connecting conductor 217. The first temperature monitoring terminal 218 and the second temperature monitoring terminal 220 are connected to the temperature sensing element. The two ends of component 219 are connected. The upper tube temperature detection element 219 is used to output the detected temperature signal of the upper tube of the inverter bridge arm through the upper tube first temperature monitoring terminal 218 or the upper tube second temperature monitoring terminal 220. The upper tube D-terminal detection terminal 221 is used to detect the upper tube D-terminal voltage. The upper tube D-terminal detection terminal 221 is connected to the upper tube ceramic substrate first copper layer 205 through the upper tube D-terminal detection terminal connecting conductor 222, and then connected to the D-terminal of the upper tube chip through the upper tube ceramic substrate first copper layer 205 and the upper tube D-terminal terminal connecting conductor 203, thereby realizing the detection of the upper tube D-terminal voltage.
[0074] In this embodiment, the inverter bridge arm lower transistor is disposed on the lower transistor substrate, and the lower transistor substrate includes: a first copper plating layer 305, a second copper plating layer 307, and a ceramic layer 306 of the lower transistor ceramic substrate; the ceramic layer 306 of the lower transistor ceramic substrate is disposed between the first copper plating layer 305 and the second copper plating layer 307 of the lower transistor ceramic substrate; the inverter bridge arm lower transistor is disposed on the first copper plating layer 305 of the lower transistor ceramic substrate.
[0075] Similar to the upper inverter arm transistor, the drain (D) terminal of the corresponding lower transistor chip 309 of the lower inverter arm transistor is connected to the first drain terminal connection terminal 302 of the lower transistor via the lower transistor drain first terminal connecting conductor 303 and the metal in the first copper plating layer 305 of the lower transistor ceramic substrate. The drain terminal of the lower transistor chip 309 is also connected to the lower transistor drain second terminal connection terminal 314 via the lower transistor drain second terminal connecting conductor 313. The source (S) terminal of the lower transistor chip 309 is connected to the lower transistor S terminal connection terminal 311 via the lower transistor S terminal connecting conductor 310. The gate (G) terminals 316 on each of the lower transistor chips 309 are connected to the lower transistor G terminal terminal 318 via the lower transistor chip G terminal connecting conductor 317. See also... Figure 8a and Figure 8bAs shown, the gate (G) poles 316 on each pair of lower transistor chips 309 are connected by a lower transistor chip G pole connecting conductor 317. The gate (G) pole 316 on the lower transistor chip 309 closest to the lower transistor G pole terminal 318 is then connected to the lower transistor G pole terminal 318 via the lower transistor chip G pole connecting conductor 317. In this case, it can be considered that the gate (G) poles 316 on each lower transistor chip 309 are directly connected to the lower transistor G pole terminal 318.
[0076] Similarly, the inverter bridge arm lower transistor also includes: a lower transistor K-terminal 319, a lower transistor first temperature monitoring terminal 321, a lower transistor second temperature monitoring terminal 323, a lower transistor temperature detection element 322, and a lower transistor D-terminal detection terminal 324. The lower transistor K-terminal 319 is connected to the lower transistor S-terminal connection terminal 311 via a lower transistor K-terminal connecting conductor 320; the lower transistor first temperature monitoring terminal and the lower transistor second temperature monitoring terminal are connected to both ends of the lower transistor temperature detection element, which is used to detect the temperature of the inverter bridge arm lower transistor through the lower transistor first temperature monitoring terminal and the lower transistor second temperature monitoring terminal; the lower transistor D-terminal detection terminal is used to detect the lower transistor D-terminal voltage.
[0077] In the technical solution disclosed in this embodiment, the types of the upper transistor chip 209 and the lower transistor chip 309 can be selected according to user needs. For example, their types can be MOSFETs or IGBTs with anti-parallel diodes. When the type is a MOSFET, the three terminals of the upper transistor chip 209 and the lower transistor chip 309 are the drain (D), source (S), and gate (G) terminals, respectively. When the type is an IGBT with anti-parallel diodes, the three terminals of the upper transistor chip 209 and the lower transistor chip 309 are the emitter (E), collector (C), and gate (G) terminals, respectively. Corresponding to the D terminal, the C terminal corresponds to the S terminal, and the two G terminals correspond to each other. For ease of introduction, the technical solutions disclosed in this application are all described using MOSFETs as an example. However, it should be noted that, as is known to those skilled in the art, the MOSFET-type upper transistor chip 209 and the lower transistor chip 309 can be replaced by an IGBT composed of anti-parallel diodes, only requiring corresponding replacement of the pins of each terminal.
[0078] In one specific embodiment, the composition of the power semiconductor device and the labels, names and functions of each component are shown in Table 1.
[0079] serial number name describe 200 Inverter bridge arm upper tube The power semiconductor device on the upper arm of the inverter bridge, often referred to as the "upper arm". 201 Upper tube casing upper tube package housing 202 Upper tube D-pole connection terminal One of the electrical connection terminals of the upper tube, the upper tube D (or C) terminal, is exposed outside 201, realizing the external electrical connection function of the upper tube D (or C) terminal. 203 Upper tube D terminal connector conductor The upper tube's D (or C) terminal connection conductor is wrapped inside 201 and soldered to 205. 204 Upper tube D-polar conductor To achieve the electrical connection function of the drain (or collector) terminal of the upper transistor chip, it consists of 202 and 203. 205 First copper layer of upper tube ceramic substrate Serving as a welding carrier for the internal chip (209), conductor (204), monitoring terminals or components (221, 215, 216, 218, 219, 220) of the upper tube (200), it achieves electrical or thermal conductivity; 205 is welded to the D (or C) terminal of the chip (209). 206 Upper tube ceramic substrate ceramic layer Achieve electrical insulation and thermal conductivity between 205 and 207. 207 Second copper layer of upper tube ceramic substrate External heat conduction surface of the upper tube (200) 208 Top tube ceramic substrate Double-sided copper-clad ceramic substrate, or simply ceramic substrate or DCB, is composed of 205, 206, and 207. 209 upper-side chip A MOSFET chip, or simply a chip, has its bottom surface as the drain (D) terminal and its top surface as the source (S) and gate (G). Alternatively, an IGBT chip, or simply a chip, has its bottom surface as the collector (C) terminal and its top surface as the emitter (E) and gate (G). 210 Upper tube S-terminal connecting conductor The upper tube's S (or E) terminal is connected to a conductor, which is encased inside 201 and connected to the S (or E) terminal of the chip (209) inside the upper tube. 211 Upper tube S-pole connection terminal One of the electrical connection terminals for the upper tube, the upper tube S (or E) terminal, is exposed outside 201 to realize the external electrical connection function of the upper tube S (or E). 212 Upper tube S-pole conductor The upper transistor chip's source (or emitter) is electrically connected, consisting of transistors 210 and 211. 213 upper transistor chip G terminal upper transistor chip G terminal 214 upper transistor chip gate connection conductor The gate (G) terminal of the upper transistor chip is connected to a conductor, and the gate (G) terminal of the upper transistor chip is connected to the gate terminal (215). 215 Upper tube G extreme sub One of the monitoring terminals of the upper transistor is connected to the gate (G) terminal of the chip inside the upper transistor. 216 Upper tube K-end unit One of the monitoring terminals of the upper pipe is connected to the 210 of the upper pipe via a Kelvin connection. 217 upper tube K-pole connection conductor Connect 210 and 216 together 218 Upper tube first temperature monitoring terminal One of the upper tube monitoring terminals, the upper tube first temperature monitoring terminal, is connected to one end of the temperature detection element (219). 219 Upper tube temperature sensing element Used to detect the temperature of the upper tube. 220 Upper tube second temperature monitoring terminal One of the upper tube monitoring terminals, the second temperature monitoring terminal of the upper tube, is connected to the other end of the temperature sensing element (219). 221 Upper tube D-terminal detection terminal One of the monitoring terminals of the upper tube is used to detect the voltage at the drain (or collector) terminal of the upper tube. 222 Upper tube D (or C) detection terminal connection conductor Connect 221 and 205 together. 300 Inverter bridge arm lower tube The lower-side power semiconductor device in the inverter bridge arm, often referred to as the "lower-side transistor". 301 Lower tube housing The housing of the lower tube package 302 Lower tube first D pole connection terminal One of the electrical connection terminals of the lower tube, the first terminal of the lower tube's drain (or collector) pole, is exposed outside of 301, realizing the first external electrical connection function of the lower tube's drain (or collector) pole. 303 The conductor connected to the first terminal of the lower tube's drain (D) pole. The first terminal of the lower tube's D (or C) electrode is connected to a conductor, which is encased inside 301 and soldered to 305. 304 The first conductor of the lower tube's drain electrode The first electrical connection function of the drain (or collector) terminal of the lower transistor chip is achieved by components 302 and 303. 305 First copper layer of the lower tube ceramic substrate 305 serves as a welding carrier for the internal chip (309), conductors (304, 313), and monitoring terminals or components (324, 318, 319, 321, 322, 323) of the lower tube (300), achieving electrical or thermal conductivity; 305 is welded to the drain (or collector) of the chip (309). 306 Bottom tube ceramic substrate ceramic layer To achieve electrical insulation and thermal conductivity between 305 and 307 307 Second copper layer of the lower tube ceramic substrate External heat-conducting surface of the lower tube (300) 308 Bottom tube ceramic substrate Double-sided copper-clad ceramic substrates, or simply ceramic substrates or DCBs, are composed of 305, 306, and 307 materials. 309 Lower transistor chip A MOSFET chip, or simply a chip, has its bottom surface as the drain (D) terminal and its top surface as the source (S) and gate (G). Alternatively, an IGBT chip, or simply a chip, has its bottom surface as the collector (C) terminal and its top surface as the emitter (E) and gate (G). 310 Lower tube S-terminal connector conductor The S (or E) terminal of the lower transistor is connected to a conductor, which is encased inside 301 and connected to the S (or E) terminal of the chip (309) inside the lower transistor. 311 Lower tube S-pole connection terminal One of the electrical connection terminals for the lower tube, the lower tube's S (or E) terminal, is located on the upper surface of 301 and exposed outside 301, realizing the external electrical connection function of the lower tube's S (or E) terminal. 312 Lower tube S-pole conductor To achieve the electrical connection of the source (or emitter) terminal of the lower transistor chip, it consists of 310 and 311. 313 The conductor connected to the second terminal of the lower tube's D pole. The second terminal of the lower tube's D (or C) electrode is connected to a conductor, which is encased inside 301 and soldered to 305. 314 Second connection terminal of lower tube D pole One of the electrical connection terminals of the lower tube, the second terminal of the lower tube's drain (or collector) pole, is exposed outside of 301, realizing the function of a second external electrical connection for the lower tube's drain (or collector) pole. 315 The second conductor of the lower tube's D pole The second electrical connection function of the lower transistor chip's drain (or collector) is achieved by components 313 and 314. 316 lower transistor chip G terminal lower transistor chip G terminal 317 The gate connection conductor of the lower transistor chip The gate (G) terminal of the lower transistor chip is connected to a conductor, and the gate (G) terminal of the lower transistor chip is connected to the gate terminal (318). 318 Lower tube G extreme sub One of the monitoring terminals of the lower transistor is connected to the gate (G) terminal of the chip inside the lower transistor. 319 Lower tube K-end One of the monitoring terminals of the lower tube is connected to the 310 of the lower tube via a Kelvin connection. 320 The lower tube's K-pole is connected to the conductor. Connect 310 and 319 together 321 Lower tube first temperature monitoring terminal One of the lower tube monitoring terminals, the first temperature monitoring terminal of the lower tube, is connected to one end of the temperature detection element (322). 322 Lower tube temperature sensing element The lower tube temperature sensing element is used to detect the temperature of the lower tube. 323 Second temperature monitoring terminal of lower tube One of the lower tube monitoring terminals, the second temperature monitoring terminal of the lower tube, is connected to the other end of the temperature sensing element (322). 324 Lower tube D-terminal detection terminal One of the monitoring terminals of the lower tube, used to detect the voltage at the drain (or collector) terminal of the lower tube. 325 Lower tube D-pole detection terminal connection conductor Connect 324 and 305 together.
[0080] Table 1
[0081] An electronic device is provided that can utilize the power semiconductor device described in any of the above embodiments. The electronic device can be a household appliance or an automobile.
[0082] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0083] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, and also include other elements not expressly listed, or elements inherent to such an article or device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device that includes said element.
[0084] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
[0085] The above description is only a preferred embodiment of the present utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present utility model, and these improvements and modifications should also be considered within the protection scope of the present utility model.
Claims
1. A power semiconductor device, characterized by, include: Inverter bridge arm upper diode and inverter bridge arm lower diode; The upper transistor of the inverter bridge arm is encapsulated with an upper transistor D-terminal connection terminal and an upper transistor S-terminal connection terminal, and the lower transistor of the inverter bridge arm is encapsulated with a lower transistor first D-terminal connection terminal, a lower transistor second D-terminal connection terminal and a lower transistor S-terminal connection terminal. The upper transistor chip corresponding to the upper transistor of the inverter bridge arm and the lower transistor chip corresponding to the lower transistor of the inverter bridge arm are fixed on the substrate. The S-pole of the upper transistor chip is connected to the S-pole connection terminal of the upper transistor, and the S-pole of the lower transistor chip is connected to the S-pole connection terminal of the lower transistor. Each inverter bridge arm upper tube corresponds to N upper tube chips, where N is a positive integer not less than 1. The N upper tube chips are distributed in parallel on the inverter bridge arm upper tube, and the distance between the drain (D) terminal of each upper tube chip and the drain terminal of the upper tube is equal, and the distance between the source (S) terminal of each upper tube chip and the source terminal of the upper tube is equal. Each inverter bridge arm lower transistor corresponds to N lower transistor chips. The N lower transistor chips are distributed in parallel on the inverter bridge arm lower transistor. The distance between the drain (D) terminal of each lower transistor chip and the first drain terminal of the lower transistor is equal. The distance between the drain (D) terminal of each lower transistor chip and the second drain terminal of the lower transistor is equal. The distance between the source (S) terminal of each lower transistor chip and the source terminal of the lower transistor is equal.
2. The power semiconductor device according to claim 1, characterized in that, The value of N is 1, 2, 3 or greater than or equal to 4.
3. The power semiconductor device of claim 1, wherein, The inverter bridge arm upper tube also includes: The upper tube ceramic substrate has a first copper plating layer, a second copper plating layer, and a ceramic layer. The upper tube ceramic substrate is disposed between the first copper layer and the second copper layer of the upper tube ceramic substrate; The upper tube of the inverter bridge arm is disposed on the first copper layer of the ceramic substrate of the upper tube.
4. The power semiconductor device according to claim 3, characterized in that, The drain (D) of the upper transistor chip is connected to the upper transistor D terminal via the upper transistor connecting conductor and the metal in the first copper layer of the upper transistor ceramic substrate. The S-pole of the upper transistor chip is connected to the S-pole connection terminal of the upper transistor through the upper transistor S-pole terminal connection conductor; The gate (G) terminals on each of the aforementioned upper transistor chips are connected to the upper transistor's gate terminal terminal via a gate connection conductor.
5. The power semiconductor device of claim 1, wherein, The inverter bridge arm upper tube also includes: The upper tube K-terminal terminal is connected to the upper tube S-terminal terminal via the upper tube K-terminal connecting conductor; The inverter bridge arm includes a first temperature monitoring terminal, a second temperature monitoring terminal, and a temperature detection element. The first and second temperature monitoring terminals are connected to both ends of the temperature detection element. The temperature detection element is used to detect the temperature of the inverter bridge arm's upper tube through the first and second temperature monitoring terminals. The upper tube's drain (D) detection terminal is used to detect the voltage at the drain (D) of the upper tube.
6. The power semiconductor device of claim 1, wherein, The inverter bridge arm lower transistor also includes: The first copper plating layer of the lower tube ceramic substrate, the second copper plating layer of the lower tube ceramic substrate, and the ceramic layer of the lower tube ceramic substrate; The lower tube ceramic substrate is disposed between the first copper layer and the second copper layer of the lower tube ceramic substrate; The inverter bridge arm lower tube is disposed on the first copper layer of the lower tube ceramic substrate.
7. The power semiconductor device of claim 1, wherein, The drain (D) terminal of the lower transistor chip is connected to the first drain (D) terminal and the second drain (D) terminal of the lower transistor through the lower transistor connecting conductor and the metal in the first copper layer of the lower transistor ceramic substrate. The S-pole of the lower transistor chip is connected to the S-pole connection terminal of the lower transistor through the lower transistor S-pole terminal connection conductor; The gate (G) terminals on each of the lower transistor chips are connected to the lower transistor's gate terminal terminal via a gate connection conductor.
8. The power semiconductor device of claim 1, wherein, The inverter bridge arm lower transistor also includes: The lower tube K-terminal is connected to the lower tube S-terminal via a lower tube K-terminal connecting conductor. The inverter bridge arm includes a first temperature monitoring terminal for the lower tube, a second temperature monitoring terminal for the lower tube, and a temperature detection element for the lower tube. The first temperature monitoring terminal for the lower tube and the second temperature monitoring terminal for the lower tube are connected to both ends of the temperature detection element for the lower tube. The temperature detection element for the lower tube is used to detect the temperature of the lower tube of the inverter bridge arm through the first temperature monitoring terminal for the lower tube and the second temperature monitoring terminal for the lower tube. The lower diode drain (D) detection terminal is used to detect the voltage at the drain (D) of the lower diode.
9. An electronic device, comprising: include: The power semiconductor device according to any one of claims 1-8.
10. The electronic device of claim 9, wherein, The electronic device is a household appliance or a car.