RS485 self-adaptive communication circuit with intelligent reflection suppression

Abstract

The utility model relates to the technical field of industrial communication interfaces, in particular to an RS485 self-adaptive communication circuit with intelligent reflection suppression. The circuit comprises an RS485 chip, an automatic transceiving circuit and a micro-control unit, the enabling end of the RS485 chip is connected with the micro-control unit through the automatic transceiving circuit, and the transceiving state of the RS485 chip is controlled by the micro-control unit; the circuit is characterized in that an electromagnetic compatibility circuit is arranged between the input and output ends of the RS485 chip and the wiring terminal, and the electromagnetic compatibility circuit comprises a transient voltage suppression circuit, a resettable fuse, a pi-type filter circuit and a gas discharge tube. According to the utility model, the EMC circuit is improved, the circuit protection capability is increased, and the inter-stage coupling interference is reduced; an automatic transceiving circuit is improved, and transceiving state switching time is shortened. Meanwhile, the number of capacitive elements in the voltage acquisition circuit and the current acquisition circuit is reduced, and stray capacitance and signal rising time are reduced.

Description

Technical Field

[0001] This utility model relates to the field of industrial communication interface technology, and in particular to the design of an intelligent reflection suppression RS485 adaptive communication circuit. Background Technology

[0002] RS485 communication circuits are widely used interface circuits in industrial control, remote communication, and multi-point data transmission, and conform to the RS485 communication protocol. Because RS485 circuits are often used in harsh environments and for long-distance transmission, they require high levels of interference immunity, lightning protection, and electromagnetic compatibility. Existing RS485 communication circuits face three major technical bottlenecks in complex industrial environments, and the relevant existing technologies are disclosed below:

[0003] 1. Insufficient EMC protection capability

[0004] According to US20210099142A1 (publication date 2021.04.08), a two-stage protection scheme using a TVS and varistor is proposed. Tests show that it has a residual voltage of up to 85V for a 10 / 700μs surge. However, due to the lack of high-frequency suppression methods, it has no effect on radiated interference above 300MHz. The protective devices use a linear series layout, leading to a 15% increase in inter-stage coupling interference.

[0005] 2. Impedance matching technology is lagging behind.

[0006] The paper IEEE Trans. Ind. Electron. 2021, 68(5): 4321-4330 proposes a dynamic impedance network based on switched capacitors, which can be adjusted in the range of 60-140Ω. However, this scheme has fatal flaws: it introduces an additional capacitive load (>50pF), which causes the signal rise time to deteriorate by 35%; and it is not linked with the physical layer characteristics, so it cannot respond to topology changes in real time.

[0007] 3. Receiving and transmitting control performance bottleneck

[0008] Traditional direction control circuits suffer from switching times exceeding 500ns due to RC filtering delays. Existing improved solutions, such as CN114157321A, employ pre-charge technology to reduce the delay to 200ns, but the risk of bus contention still exists. Summary of the Invention

[0009] To address the aforementioned issues, this invention proposes an RS485 communication circuit capable of intelligent reflection suppression. Through a five-layer protection design of the electromagnetic compatibility circuit (EMC circuit), inter-stage coupling interference is reduced, and through improvements to the automatic transceiver circuit, the RS485 transceiver state switching time is reduced.

[0010] The technical solution adopted in this utility model is as follows:

[0011] An intelligent reflection-suppressing RS485 adaptive communication circuit includes an RS485 chip, an automatic transceiver circuit, and a microcontroller unit. The enable terminal of the RS485 chip is connected to the microcontroller unit via the automatic transceiver circuit, and the microcontroller unit controls the transmit and receive states of the RS485 chip. An electromagnetic compatibility (EMC) circuit is provided between the input / output terminals and the wiring terminals of the RS485 chip. The EMC circuit includes a transient voltage suppression circuit, a resettable fuse, a π-type filter circuit, and a gas discharge tube to reduce interstage coupling. This invention enhances the EMC circuit design by constructing a five-level protection circuit consisting of a transient voltage suppression circuit, a resettable fuse, a common-mode choke, a π-type filter circuit, and a gas discharge tube. Combined with a honeycomb layout on the PCB board, the protective devices are arranged in a snowflake-shaped topology on different layers of the PCB board with a layer spacing ≥5mm, reducing interstage coupling to below 3%, far lower than the 15% of traditional methods.

[0012] Preferably, the automatic transceiver circuit includes a field-effect transistor (FET). The gate of the FET is connected to the TXD data line of the microcontroller unit via a resistor. The drain of the FET is connected to the enable pins RE# and DE of the RS485 chip, and is also connected to a DC power supply via a resistor. The source of the FET is grounded. The RXD data line of the microcontroller unit is connected to the RO pin of the RS485 chip via a resistor. This invention connects the FET in parallel to the enable pin of the RS485 chip, utilizing its low on-resistance (Rds(on) = 0.1Ω) and large drive current (±2A transient) to compress the transceiver state switching time from 200ns to 35ns.

[0013] Furthermore, a voltage acquisition circuit is provided between the input / output terminals of the RS485 chip and the microcontroller unit. The voltage acquisition circuit includes a differential amplifier and a voltage follower. The input terminal of the differential amplifier is connected to the input / output terminals of the RS485 chip, and its output terminal is connected to the input terminal of the voltage follower. The output terminal of the voltage follower is connected to the analog voltage signal input terminal of the microcontroller unit, which is used to acquire the voltage difference between the input and output terminals to realize differential data transmission.

[0014] Furthermore, a current acquisition circuit is provided between the input / output terminals of the RS485 chip and the microcontroller unit. An electronic load is connected in parallel between the input / output terminals of the RS485 chip and the electromagnetic compatibility circuit. The SCLK and DIN pins of the electronic load are connected to the IIC bus of the microcontroller unit, its L pin is connected to the input / output terminal B of the RS485 chip, and its W pin is connected to the input / output terminal A of the RS485 chip through a first resistor. The two ends of the first resistor are connected to the IN+ and IN- pins of the current acquisition chip through a first filter circuit. The OUT pin of the current acquisition chip is connected to the analog current signal input terminal of the microcontroller unit through a second filter circuit, outputting the acquired current signal. This invention utilizes an electronic load connected in series with a low-resistance resistor. By configuring the resistance value of the load circuit through the electronic load, the load current can be precisely adjusted. The first resistor is connected to the current acquisition chip to detect the current passing through the first resistor.

[0015] This invention avoids capacitive components in its voltage and current acquisition circuits as much as possible, thereby significantly reducing parasitic capacitance to below 5pF. The signal rise time is also maintained at 28ns, far lower than the 48ns of traditional methods. Simultaneously, based on real-time PID control of overcharge amplitude, the differential current is detected by the current acquisition chip, and combined with data from the voltage acquisition circuit, impedance matching accuracy reaches ±0.8Ω, also far lower than the ±5Ω of traditional methods.

[0016] This invention improves the EMC circuit, increases circuit protection capabilities, and reduces interstage coupling interference; it also improves the automatic transceiver circuit, reducing the transceiver state switching time. Simultaneously, it reduces the number of capacitive components in the voltage and current acquisition circuits, lowering parasitic capacitance and signal rise time, thus significantly improving transmission efficiency. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the principle of this utility model;

[0018] Figure 2 This is a circuit diagram of the RS485 chip, its peripheral automatic transceiver circuit, and EMC circuit.

[0019] Figure 3 This is a circuit diagram of the voltage acquisition circuit described in this utility model;

[0020] Figure 4 This is a circuit diagram of the current acquisition circuit described in this utility model;

[0021] Figure 5 This is a circuit diagram of the microcontroller unit described in this utility model;

[0022] In the diagram, 1 is the automatic transceiver circuit, 2 is the electromagnetic compatibility circuit, 3 is the microcontroller unit, 4 is the current acquisition circuit, and 5 is the voltage acquisition circuit. Detailed Implementation

[0023] The specific structure of this utility model will be described below with reference to the accompanying drawings.

[0024] A smart reflection-suppressing RS485 adaptive communication circuit, such as Figure 1 As shown, the system includes an RS485 chip, a microcontroller unit 3, an automatic transceiver circuit 1, an electromagnetic compatibility (EMC) circuit 2, a voltage acquisition circuit 5, and a current acquisition circuit 4. The EMC circuit 2 includes a transient voltage suppression circuit, a resettable fuse, a π-type filter circuit, and a gas discharge tube. The enable terminal of the RS485 chip is connected to the microcontroller unit 3 via the automatic transceiver circuit 1, and the microcontroller unit controls the transceiver status of the RS485 chip. An electronic load and the EMC circuit 2 are sequentially arranged between the input / output terminals and the wiring terminals of the RS485 chip. The EMC circuit is used for EMC protection, and the electronic load is used to configure the resistance value and is connected to the current acquisition circuit 4 to achieve differential data transmission current acquisition. The input / output terminals of the RS485 chip are connected to the microcontroller unit via the voltage acquisition circuit 5 to achieve differential data transmission voltage acquisition.

[0025] The circuit structure will be explained using a specific circuit diagram:

[0026] like Figure 2 As shown, the RO pin of the RS485 chip U1 is connected to the RXD data line of the microcontroller unit via resistor R2. Its RE# and DE pins are connected in parallel to a DMN3010L MOSFET Q1, which is connected to a +5V DC power supply via resistor R4. This connection also connects to the drain of MOSFET Q1, while the source of MOSFET Q1 is grounded. The gate is connected to the TXD data line of the microcontroller unit U13 via resistor R6. By connecting a MOSFET in parallel to the enable pin of the RS485 chip, utilizing its low on-resistance (Rds(on) = 0.1Ω) and large drive current (±2A transient), the transmit / receive state switching time can be compressed from 200ns to 35ns. The DI and GND pins of the RS485 chip are grounded, the VCC pin is connected to a +5V DC power supply, and a filter capacitor is included.

[0027] like Figure 2As shown, the input / output terminal A of the RS485 chip U1 is connected to a +5V DC power supply through a limiting resistor R5, and the input / output terminal B is grounded through a limiting resistor R1. After a resistor R3 is connected in parallel, data transmission lines 485A and 485B are led out respectively. The two data transmission lines 485A and 485B are first connected in parallel to a transient voltage suppression circuit composed of TVS diodes D1, D2, and D4 to suppress possible surge pulse impacts. Self-resetting fuses F2 and F1 are connected in series on the two data transmission lines 485A and 485B respectively, followed by a common-mode inductor L2. The four terminals of the common-mode inductor L2 are grounded through filter capacitors C9, C10, C11, and C12 respectively, forming a π-type filter circuit to filter out harmonics and avoid harmonic interference. The two data transmission lines 485A and 485B are grounded through a gas discharge tube D3 for rapid current discharge to prevent damage to the circuit from lightning strikes. The above-mentioned multi-level EMC protection circuit is constructed on the RS485 chip data transmission line. Each protection device is arranged in a "snowflake" topology on different layers of the PCB board with a spacing of ≥5mm between levels (optimized by HFSS simulation). This can reduce the inter-level coupling to below 3%.

[0028] like Figure 3 As shown, the input and output terminals A and B of RS485 chip U1 are connected to the inverting input terminal and the non-inverting input terminal of differential amplifier U4.1 through resistors R13 and R15, respectively. The output terminal of differential amplifier U4.1 is connected to the non-inverting input terminal of voltage follower U4.2. The output terminal of voltage follower U4.2 is connected to the ADC_U_DIFF lead of microcontroller unit through the third filter circuit, so as to send the analog voltage signal in the data transmission line to microcontroller unit.

[0029] like Figure 4 As shown, an electronic load U2 is connected in parallel to the input / output terminals A and B of the RS485 chip U1. The SCLK and DIN pins of the electronic load U2 are connected to the IIC_SCL_R and IIC_SDA_R pins of the microcontroller U13 to receive clock signals and data from the microcontroller. The L pin of the electronic load U2 is connected to the data transmission line 485B, and the W pin is connected in series with the data transmission line 485A by a first resistor R8. A first filter circuit consisting of resistors R7 and R9 and capacitor C3 is connected in parallel across the first resistor R8, and then connected to the IN- and IN+ pins of the current acquisition chip U3. The OUT pin of the current acquisition chip is connected to the ADC_I_DIFF pin of the microcontroller through a second filter circuit consisting of resistor R10 and capacitor C5, sending the acquired analog current signal from the data transmission line to the microcontroller.

Claims

1. A RS485 adaptive communication circuit with intelligent reflection suppression, comprising a RS485 chip, an automatic transceiver circuit and a micro control unit, the enable end of the RS485 chip is connected with the micro control unit through the automatic transceiver circuit, and the transceiving state of the RS485 chip is controlled by the micro control unit; characterized in that: The RS485 chip has an electromagnetic compatibility circuit between its input / output terminals and the wiring terminals. The electromagnetic compatibility circuit includes a transient voltage suppression circuit, a self-resetting fuse, a π-type filter circuit, and a gas discharge tube, which are used to reduce the interstage coupling rate.

2. The intelligent reflection-suppressed RS485 adaptive communication circuit of claim 1, wherein: The automatic transceiver circuit includes a field-effect transistor (FET). The gate of the FET is connected to the TXD data line of the microcontroller unit through a resistor. The drain of the FET is connected to the enable pin RE# and the DE pin of the RS485 chip, and is also connected to a DC power supply through a resistor. The source of the FET is grounded. The RXD data line of the microcontroller unit is connected to the RO pin of the RS485 chip through a resistor.

3. The intelligent reflection-suppressed RS485 adaptive communication circuit of claim 1, wherein: A voltage acquisition circuit is also provided between the input / output terminals of the RS485 chip and the microcontroller unit. The voltage acquisition circuit includes a differential amplifier and a voltage follower. The input terminal of the differential amplifier is connected to the input / output terminals of the RS485 chip, and its output terminal is connected to the input terminal of the voltage follower. The output terminal of the voltage follower is connected to the analog voltage signal input terminal of the microcontroller unit. This circuit is used to acquire the voltage difference between the input and output terminals and realize differential data transmission.

4. The intelligent reflection-suppressed RS485 adaptive communication circuit of claim 1, wherein: A current acquisition circuit is also provided between the input / output terminals of the RS485 chip and the microcontroller unit. An electronic load is connected in parallel between the input / output terminals of the RS485 chip and the electromagnetic compatibility circuit. The SCLK and DIN pins of the electronic load are connected to the IIC bus of the microcontroller unit, its L pin is connected to the input / output terminal B of the RS485 chip, and its W pin is connected to the input / output terminal A of the RS485 chip through a first resistor. The two ends of the first resistor are connected to the IN+ and IN- pins of the current acquisition chip through a first filter circuit. The OUT pin of the current acquisition chip is connected to the analog current signal input terminal of the microcontroller unit through a second filter circuit to output the acquired current signal.

Images