Server CPU single-channel and double-channel switching system

Abstract

The utility model provides a server CPU (central processing unit) single-channel and double-channel switching system, which comprises two CPU core boards, each CPU core board is provided with a CPU, an FPGA (field programmable gate array) expansion module and a dial switch, each CPU is provided with UEFI (unified extensible firmware interface) firmware and a system hard disk, the CPUs of the two CPU core boards are connected with each other, and each CPU core board is connected with the dial switch through an ID (identity) pin of the FPGA expansion module so as to detect the state of the dial switch. When a user has a high requirement on the data stability of the server with the double-channel CPU architecture, the dial switches of the two CPU core boards can be set to be in a main state, so that the two CPU core boards are switched on after detecting that the states of the two dial switches are in the main state through the ID pins of the FPGA expansion modules of the two CPU core boards; the UEFI firmware and the system hard disk of the CPUs of the two CPU core boards are independently configured to enter the operating system, the CPUs of the two CPU core boards serve as main single-path output, cross-CPU transmission of the operating system does not need to be carried out, and data stability is improved.

Description

Technical Field

[0001] This utility model relates to the field of hardware chip technology, and in particular to a server CPU single-to-dual-path switching system. Background Technology

[0002] The CPU (Central Processing Unit) is the core component of a computer, serving as the computational and control hub of the computer system, responsible for executing computer instructions and processing data. With the continuous growth in computing power demands from high-performance computing, cloud computing, and other applications, dual-CPU architecture has become the mainstream solution in the server field. While dual-CPU architecture effectively increases the theoretical computing power ceiling of a server through parallel computing capabilities, in practical applications, the cross-CPU access process affects data stability, making it difficult to meet users' high requirements for data stability. Utility Model Content

[0003] The technical problem this invention aims to solve is how to enable the dual-CPU architecture of a server to meet users' high requirements for data stability.

[0004] To solve the above-mentioned technical problems, this utility model provides a server CPU single / dual-path switching system, including two CPU core boards. Each CPU core board is equipped with a CPU, an FPGA expansion module and a DIP switch. Each CPU is configured with UEFI firmware and a system hard disk. The CPUs of the two CPU core boards are interconnected. Each CPU core board is connected to its DIP switch through the ID pin of its FPGA expansion module to detect the status of the DIP switch.

[0005] Furthermore, the CPUs on the two CPU core boards are specifically interconnected via a RETIME chip.

[0006] Furthermore, the CPUs of the two CPU core boards are connected to the RETIME chip via a C2C bus.

[0007] Furthermore, each CPU core board specifically connects its DIP switch to three ID pins of its FPGA expansion module to detect the DIP switch status, wherein the DIP switch consists of three independent toggle switches arranged in parallel.

[0008] Furthermore, the FPGA expansion module is specifically an FMC interface module.

[0009] This invention offers the following advantages: Under normal circumstances, one CPU core board's DIP switch is set to master mode, while the other CPU core board's DIP switch is set to slave mode. When the two CPU core boards detect this master-slave configuration via the ID pin of their FPGA expansion module, the CPU core board in master mode configures its UEFI firmware and system hard drive to enter the operating system. This operating system is then transmitted to the CPU core board in slave mode via the connection link between the two CPU core boards, forming a dual-CPU architecture. When users have high requirements for data stability in this dual-CPU architecture, both CPU core boards can be set to master mode. When both CPU core boards detect this master mode via the ID pin of their FPGA expansion module, each CPU core board independently configures its UEFI firmware and system hard drive to enter the operating system. This allows each CPU core board to perform single-path master output, eliminating the need for cross-CPU operating system transmission and improving data stability. Attached Figure Description

[0010] Figure 1 This is a connection diagram of a server CPU single / dual-processor switching system.

[0011] Figure 2 This is a schematic diagram of the single / dual-path switching control logic of the server CPU single / dual-path switching system. Detailed Implementation

[0012] The present invention will be further described in detail below with reference to specific embodiments.

[0013] This embodiment provides a server CPU single / dual-processor switching system, such as... Figure 1 As shown, the system includes two CPU core boards, namely CPU core board one and CPU core board two. Each CPU core board is equipped with a CPU, an FPGA expansion module and a DIP switch. Each CPU is configured with UEFI firmware and a system hard disk. The CPUs of the two CPU core boards are interconnected. Each CPU core board connects to its DIP switch through the ID pin of its FPGA expansion module to detect the status of the DIP switch.

[0014] In this embodiment, the CPUs of the two CPU core boards are connected to a RETIME chip via a C2C bus, enabling interconnection between the CPUs of the two CPU core boards through the RETIME chip. The C2C bus speed determines the signal bandwidth, which is determined by the board material and the connection distance. The board design incorporates a RETIME chip in the middle of the C2C bus, improving the speed of ordinary boards without requiring high-speed boards, while simultaneously increasing the communication speed over long distances.

[0015] The CPU core board is a reconfigurable hardware module based on a Field Programmable Gate Array (FPGA). It typically serves as the core computing unit of an embedded system, used for high-speed data processing, protocol acceleration, and real-time control. The FPGA expansion module is specifically the FMC interface module (FPGAMezzanine Card). FMC is a modular expansion interface (VITA57) standardized by VITA (VME International Trade Association), primarily used for high-speed peripheral expansion of the CPU core board. It provides a flexible way for users to quickly connect ADC (Analog-to-Digital Converter), DAC (Digital-to-Analog Converter), high-speed communication, and image acquisition daughter cards to the CPU core board without redesigning the entire system. The system hard drive is the storage device for the operating system's core files, the bootloader, and user data. Its partition format and boot method directly affect system startup. UEFI firmware (Unified Extensible Firmware Interface) is a modern computer firmware standard responsible for initializing hardware and loading the operating system from the system hard drive during computer startup. A DIP switch is a manually configured miniature switch component, typically used in scenarios such as hardware configuration, address selection, and mode switching. It is used to physically toggle different combinations of voltage levels (high / low) to transmit information about the current carrier board's role (master / slave) or operating mode (single / dual) to the core board FPGA.

[0016] In this embodiment, the DIP switch consists of three independent toggle switches arranged in parallel. Each switch can be independently set to ON (closed, corresponding to logic 0) or OFF (open, corresponding to logic 1). By setting different DIP switch states, the master and slave states of the two core boards are determined. For example, DIP switch state 000 corresponds to the master state of the core board, and DIP switch state 001 corresponds to the slave state of the core board. Correspondingly, each CPU core board specifically connects its DIP switch to its three ID pins through its FPGA expansion module to detect the DIP switch state (000 or 001).

[0017] like Figure 2As shown, under normal circumstances, one CPU core board's DIP switch is set to master mode, and the other CPU core board's DIP switch is set to slave mode. When the two CPU core boards detect that the two DIP switches are in master and slave mode through the ID pin of their FPGA expansion module, the CPU core board in master mode configures its UEFI firmware and system hard drive to enter the operating system. Then, through the connection link between the CPUs of the two CPU core boards, the operating system is transmitted to the CPU core board in slave mode. The two CPUs together form a dual-CPU architecture.

[0018] For example, in the dual-processor scenario 1, the DIP switch of CPU core board 1 is set to master mode, and the DIP switch of CPU core board 2 is set to slave mode. In this way, CPU core board 1 detects its DIP switch state as 000 through the three ID pins of its FPGA expansion module, corresponding to master mode, while CPU core board 2 detects its DIP switch state as 001 through the three ID pins of its FPGA expansion module, corresponding to slave mode. Then, the CPU of CPU core board 1 in master mode configures its UEFI firmware and system hard drive to enter the operating system, outputs a 48M synchronous clock to the CPU of CPU core board 2 in slave mode, and then configures the CPU of CPU core board 2 in slave mode through I2C (integrated circuit bus). Finally, through the connection link between the CPUs of the two CPU core boards, the operating system is transmitted to the CPU of CPU core board 2 in slave mode, and the two CPUs together form a dual-processor CPU architecture.

[0019] For example, in the dual-processor scenario 2, the DIP switch of CPU core board 2 is set to master mode, and the DIP switch of CPU core board 1 is set to slave mode. In this way, CPU core board 2 detects its DIP switch state as 000 through the three ID pins of its FPGA expansion module, corresponding to master mode, while CPU core board 1 detects its DIP switch state as 001 through the three ID pins of its FPGA expansion module, corresponding to slave mode. Then, the CPU of CPU core board 2 in master mode configures its UEFI firmware and system hard disk to enter the operating system, outputs a 48M synchronous clock to the CPU of CPU core board 1 in slave mode, and then configures the CPU of CPU core board 1 in slave mode through I2C (integrated circuit bus). Finally, through the connection link between the CPUs of the two CPU core boards, the operating system is transmitted to the CPU of CPU core board 1 in slave mode, and the two CPUs together form a dual-processor CPU architecture.

[0020] When users have high requirements for the data stability of servers with dual-CPU architecture, the DIP switches of both CPU core boards can be set to the master state. In this way, after the two CPU core boards detect that the two DIP switches are in the master state through the ID pin of their FPGA expansion module, the CPUs of the two CPU core boards independently configure their UEFI firmware and system hard disk to enter the operating system. Then, the CPUs of the two CPU core boards each perform master single-channel output, without the need for cross-CPU transfer of the operating system, thus improving data stability.

[0021] For example, in a single-channel scenario, the DIP switches of both CPU core board 1 and CPU core board 2 are set to the master state. In this way, the two CPU core boards can detect that the state of their DIP switches is 000 through the three ID pins of their FPGA expansion modules, which corresponds to the master state. Then, the CPUs of CPU core board 1 and CPU core board 2 independently configure their UEFI firmware and system hard disk to enter the operating system. Thus, the CPUs of the two CPU core boards perform master single-channel output respectively, without the need for cross-CPU transfer of the operating system, thereby improving data stability.

[0022] The above description is merely an embodiment of the present invention and does not limit the scope of patent protection. Any non-substantial changes or substitutions made by those skilled in the art based on the present invention will still fall within the scope of patent protection.

Claims

1. A server CPU single / dual-processor switching system, characterized in that, It includes two CPU core boards, each with a CPU, an FPGA expansion module and a DIP switch. Each CPU is configured with UEFI firmware and a system hard drive. The CPUs on the two CPU core boards are interconnected. Each CPU core board connects to its DIP switch through the ID pin of its FPGA expansion module to detect the status of the DIP switch.

2. The server CPU single / dual-path switching system according to claim 1, characterized in that, The CPUs on the two CPU core boards are interconnected via a RETIME chip.

3. The server CPU single / dual-path switching system according to claim 2, characterized in that, The CPUs of the two CPU core boards are connected to the RETIME chip via a C2C bus.

4. The server CPU single / dual-path switching system according to claim 1, characterized in that, Each CPU core board specifically connects its DIP switches to three ID pins of its FPGA expansion module to detect the DIP switch status. The DIP switches consist of three independent toggle switches arranged in parallel.

5. The server CPU single / dual-path switching system according to claim 1, characterized in that, The FPGA expansion module is specifically an FMC interface module.

Images