Power semiconductor device and electronic equipment
By optimizing the connection terminal layout of the inverter's upper and lower transistors in the power semiconductor device, and avoiding the crossing of DC and AC copper busbars, the problem of reduced parasitic inductance in the prior art is solved, thereby improving device reliability and system integration flexibility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- WEICHAI POWER CO LTD
- Filing Date
- 2025-03-07
- Publication Date
- 2026-04-28
AI Technical Summary
In existing power semiconductor devices, the cross-design of DC and AC copper busbars reduces the integrity of the stacked copper busbars and decreases the parasitic inductance.
Design a power semiconductor device in which the connection terminals of the upper and lower inverter are arranged so that the AC copper busbars and DC copper busbars do not cross, and monitoring terminals and temperature sensing elements are distributed on the sides of the upper and lower inverters to ensure that there is no crossing during connection and reduce parasitic inductance.
It improves the reliability of power semiconductor devices and the flexibility of system integration, reduces the inductance of drive circuits, and simplifies the manufacturing process.
Smart Images
Figure CN224178091U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, specifically to a power semiconductor device and electronic device. Background Technology
[0002] Power semiconductor devices are semiconductor devices that can withstand large currents and high voltages. They are mainly used in high-power (usually referring to currents of tens to thousands of amperes and voltages of hundreds of volts or more) electronic devices in power conversion and power control circuits.
[0003] Figure 1 This is a schematic diagram of a power semiconductor device packaging design scheme in the prior art. Figure 1 In this diagram, 100 refers to the semiconductor device, 104 is the substrate, and 102A and 102B are planar terminals. Figure 1 The structure also includes: silicon wafer 106A, silicon wafer 106B, spacing 108, offset portion 110, contact portion 112, common opening 116, housing 114, and electrical insulator 118. The planar terminals 102A and 102B are DC busbars, and the offset portion 110 can be considered an AC busbar. It is evident that the DC and AC busbars are designed in an overlapping manner in this structure. This design compromises the integrity of the multilayer copper busbar and reduces its effectiveness in reducing parasitic inductance. Utility Model Content
[0004] In view of this, the present invention provides a power semiconductor device and an electronic device, wherein the DC copper busbar and the AC copper busbar do not cross.
[0005] To achieve the above objectives, the present invention provides the following technical solutions:
[0006] A power semiconductor device, comprising:
[0007] At least one inverter bridge arm, each inverter bridge arm including an upper inverter tube and a lower inverter tube, the upper inverter tube being encapsulated with an upper tube drain (D) connection terminal and an upper tube source (S) connection terminal, the upper tube drain (D) connection terminal being located at the upper side of the upper inverter tube, the upper tube source (S) connection terminal being located at the lower side of the upper inverter tube, the lower inverter tube being encapsulated with a lower tube first drain (D) connection terminal, a lower tube second drain (D) connection terminal, and a lower tube source (S) connection terminal, the upper tube source (S) connection terminal being connected to the lower tube first drain (D) connection terminal to form the midpoint of the inverter bridge arm, the lower tube first drain (D) connection terminal being located at the upper side of the lower inverter tube and matching the position of the upper tube drain (D) connection terminal, the lower tube second drain (D) connection terminal being located at the lower side of the lower inverter tube, and the lower tube source (S) connection terminal being located in the middle region of the lower inverter tube;
[0008] The monitoring terminals and temperature detection elements of the upper and lower inverter tubes are respectively located on the sides of the upper and lower inverter tubes.
[0009] Optionally, in the above-mentioned power semiconductor device, the monitoring terminal and temperature detection element of the inverter upper tube are distributed on the same side of the inverter upper tube.
[0010] The monitoring terminals and temperature sensing elements of the inverter's lower diode are located on the same side of the inverter's lower diode.
[0011] Optionally, in the above-mentioned power semiconductor device, the side of the upper inverter tube where the monitoring terminals and temperature sensing elements are distributed is directly opposite the side of the lower inverter tube where the monitoring terminals and temperature sensing elements are distributed.
[0012] Optionally, in the above power semiconductor device, the inverter upper transistor includes N upper transistor chips, and the inverter lower transistor includes N lower transistor chips, where N is a positive integer not less than 2, and the upper transistor source terminal of each upper transistor chip is bonded together by a metal connecting wire.
[0013] Optionally, in the above power semiconductor device, the monitoring terminal includes a K-terminal, a D-terminal detection terminal, a first temperature monitoring terminal, and a second temperature monitoring terminal;
[0014] The K-terminal is connected to the S-terminal of the corresponding upper or lower transistor chip via a K-terminal connecting conductor.
[0015] The D-terminal detection terminal is used to detect the D-terminal voltage of the corresponding upper or lower transistor chip.
[0016] The first temperature monitoring terminal and the second temperature monitoring terminal are disposed at both ends of the temperature detection element.
[0017] Optionally, in the above power semiconductor device, the upper inverter transistor is fixed on the upper transistor substrate, and the lower inverter transistor is fixed on the lower transistor substrate.
[0018] The upper tube substrate includes: a first copper plating layer of the upper tube ceramic substrate, a second copper plating layer of the upper tube ceramic substrate, and a ceramic layer of the upper tube ceramic substrate; the upper tube ceramic substrate is disposed between the first copper plating layer and the second copper plating layer of the upper tube ceramic substrate; the inverter upper tube is disposed on the first copper plating layer of the upper tube ceramic substrate.
[0019] The lower diode substrate includes: a first copper plating layer of the lower diode ceramic substrate, a second copper plating layer of the lower diode ceramic substrate, and a ceramic layer of the lower diode ceramic substrate; the lower diode ceramic substrate is disposed between the first copper plating layer and the second copper plating layer of the lower diode ceramic substrate; the lower diode of the inverter is disposed on the first copper plating layer of the lower diode ceramic substrate.
[0020] Optionally, in the above power semiconductor device, the drain (D) of the upper transistor chip is connected to the upper transistor drain terminal via an upper transistor connecting conductor and a metal line in the first copper-clad layer of the upper transistor ceramic substrate.
[0021] The S-pole of the upper transistor chip is connected to the S-pole connection terminal of the upper transistor through the upper transistor S-pole terminal connection conductor;
[0022] The gate (G) terminals on each of the aforementioned upper-side chips are connected to the upper-side G terminal terminals via a gate-side connection conductor.
[0023] Optionally, in the above-mentioned power semiconductor device, the drain (D) of the lower transistor chip is connected to the first drain connection terminal and the second drain connection terminal of the lower transistor through the lower transistor connection conductor and the metal line in the first copper layer of the lower transistor ceramic substrate.
[0024] The S-pole of the lower transistor chip is connected to the S-pole connection terminal of the lower transistor through the lower transistor S-pole terminal connection conductor;
[0025] The gate (G) terminals on each of the lower transistor chips are connected to the lower transistor G terminal terminal via a gate-connected conductor.
[0026] An electronic device comprising any of the power semiconductor devices described above. The electronic device is a household appliance or an automobile.
[0027] Based on the above technical solution, the above solution provided by this utility model embodiment includes an inverter bridge arm in the power semiconductor device comprising an upper inverter transistor and a lower inverter transistor. The upper inverter transistor is encapsulated with an upper transistor drain (D) connection terminal and an upper transistor source (S) connection terminal. The upper transistor drain (D) connection terminal is located at the upper side of the upper inverter transistor, and the upper transistor source (S) connection terminal is located at the lower side of the upper inverter transistor. The lower transistor's first drain (D) connection terminal is located at the upper side of the lower inverter transistor, matching the position of the upper transistor drain (D) connection terminal. The lower transistor's second drain (D) connection terminal is located at the lower side of the lower inverter transistor, and the lower transistor source (S) connection terminal is located in the middle region of the lower inverter transistor. The monitoring terminals and temperature detection elements of the upper and lower inverter transistors are respectively distributed on the sides of the upper and lower inverter transistors. When connecting the power semiconductor device, the AC busbar and DC busbar connected to the power semiconductor device do not cross each other, which avoids the situation where the parasitic inductance is reduced due to the crossing of the AC busbar and DC busbar, and can effectively improve the reliability of the power semiconductor device. Attached Figure Description
[0028] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0029] Figure 1 This is a schematic diagram of a power semiconductor device packaging and power system design scheme disclosed in the prior art;
[0030] Figure 2 The circuit topology diagram of the existing inverter main power system;
[0031] Figure 3 This is a schematic diagram of the circuit symbol for an IGBT.
[0032] Figure 4 This is a schematic diagram of the IGBT chip structure;
[0033] Figure 5 This is a schematic diagram of the electrical symbol for a MOSFET.
[0034] Figure 6 This is a schematic diagram of the MOSFET chip structure;
[0035] Figure 7 This is a schematic diagram of the inverter upper tube layout provided in an embodiment of this application;
[0036] Figure 8 This is a schematic diagram of the inverter bottom tube layout provided in an embodiment of this application;
[0037] Figure 9 A schematic diagram illustrating the connection and encapsulation method of the inverter upper transistor and inverter lower transistor provided in an embodiment of this application;
[0038] Figure 10 A schematic diagram of the left-side terminal arrangement of the inverter upper tube provided for another embodiment of this application;
[0039] Figure 11 This is a schematic diagram of the left-side terminal arrangement of the inverter's lower transistor, provided for another embodiment of this application.
[0040] Inverter bridge arm upper transistor S1; inverter bridge arm lower transistor S2;
[0041] Inverter upper transistor 200; upper transistor housing 201; upper transistor drain (D) terminal 202; upper transistor drain terminal connecting conductor 203; upper transistor drain conductor 204; upper transistor ceramic substrate first copper layer 205; upper transistor ceramic substrate ceramic layer 206; upper transistor ceramic substrate second copper layer 207; upper transistor ceramic substrate 208; upper transistor chip 209; upper transistor S terminal connecting conductor 210; upper transistor S terminal 211; upper transistor S conductor 212; upper transistor chip G terminal 213; upper transistor chip G terminal connecting conductor 214; upper transistor G terminal 215; upper transistor K terminal 216; upper transistor K terminal connecting conductor 217; upper transistor first temperature monitoring terminal 218; upper transistor temperature detection element 219; upper transistor second temperature monitoring terminal 220; upper transistor drain detection terminal 221; upper transistor drain detection terminal connecting conductor 222.
[0042] Inverter lower transistor 300; lower transistor housing 301; lower transistor first drain (D) terminal connection 302; lower transistor drain first terminal connection conductor 303; lower transistor drain first conductor 304; lower transistor ceramic substrate first copper plating layer 305; lower transistor ceramic substrate ceramic layer 306; lower transistor ceramic substrate second copper plating layer 307; lower transistor ceramic substrate 308; lower transistor chip 309; lower transistor S-terminal terminal connection conductor 310; lower transistor S-terminal connection terminal 311; lower transistor S-terminal conductor 312; lower transistor drain second terminal connection... Conductor 313; Second D-terminal connection terminal of lower tube 314; Second conductor of lower tube D-terminal 315; G-terminal of lower tube chip 316; G-terminal connection conductor of lower tube chip 317; G-terminal of lower tube 318; K-terminal of lower tube 319; K-terminal connection conductor of lower tube 320; First temperature monitoring terminal of lower tube 321; Temperature detection element of lower tube 322; Second temperature monitoring terminal of lower tube 323; D-terminal detection terminal of lower tube 324; Connecting conductor of D-terminal detection terminal of lower tube 325; Midpoint of inverter bridge arm 411. Detailed Implementation
[0043] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0044] First, the relevant terms in this application will be explained:
[0045] Power electronic devices: devices that can convert and control electrical energy, consisting of power semiconductor devices, passive devices (inductors, capacitors), structural components, heat dissipation systems, and control devices.
[0046] Power system: The system consisting of the high-voltage, high-power part of the power electronic converter device, mainly including power semiconductor devices, passive devices (inductors or capacitors), and electrical connection components (such as copper busbars, wires, etc.).
[0047] Power semiconductor chips: made of semiconductor materials such as silicon (Si), silicon carbide (SiC), and gallium nitride (GaN), they can convert and control electrical energy through rapid switching on and off. They mainly include IGBTs (generally made of Si), MOSFETs (generally made of Si, SiC, or GaN), and diodes (made of Si or SiC). This application refers to them as "chips".
[0048] Power semiconductor packaging: Power semiconductor chips cannot be used directly. They must be installed inside a module through a series of processes to achieve functions such as chip-to-chip connectivity, external electrical connections, heat dissipation, and chip protection (insulation, waterproofing, dustproofing, oxidation prevention, and mechanical damage prevention). The structure of this module is called power semiconductor packaging. In this application, it is referred to as "packaging".
[0049] Power semiconductor device: A module consisting of a power semiconductor chip and a power semiconductor package is called a power semiconductor device. In this application, it is referred to as "device".
[0050] Inverter: A power electronic device that converts direct current (DC) to alternating current (AC). Its main power system is as follows: Figure 2 As shown. Figure 2 The left side shows the DC input of the inverter, which is typically a DC power source such as a battery. Figure 2 The AC output is on the right. The inverter consists of three-phase inverter arms. Power semiconductor devices S1 and S2 (MOSFETs shown in the diagram) form the A-phase inverter arm. S1 is the upper transistor of the inverter arm, and its drain (D) terminal is connected to the DC+ bus. S2 is the lower transistor of the inverter arm, and its source (S) terminal is connected to the DC- bus. Point A is the connection point between the source terminal of S1 and the drain terminal of S2, which is the AC output point of the A-phase inverter arm. S1 and S2 alternately and complementaryly conduct, allowing AC voltage to be output at point A. Similarly, the working principle of phases B and C is the same.
[0051] IGBT: Insulated Gate Bipolar Transistor is a power semiconductor device, its symbol is as follows: Figure 3 and Figure 4As shown, an IGBT has three terminals: the collector (C), the emitter (E), and the gate (G). When the voltage between the gate and the emitter exceeds a certain value (threshold voltage), the IGBT conducts, and current can flow from the collector to the emitter, but it cannot conduct in the reverse direction. To provide a path for reverse conduction, a diode is typically connected in anti-parallel to the IGBT.
[0052] MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor (FET) is a type of power semiconductor device, its symbol being as follows: Figure 5 and Figure 6 As shown, a MOSFET has three terminals: drain (D), source (S), and gate (G). When the voltage between the gate and source exceeds a certain value (threshold voltage), the MOSFET turns on, and current can flow from the drain to the source. Due to the structure of the MOSFET, it has a reverse-parallel diode, so current can flow from the source to the drain regardless of whether the MOSFET is in the on state.
[0053] See Figure 7 and Figure 8 This application discloses a power semiconductor device, comprising:
[0054] At least one inverter bridge arm, each inverter bridge arm including an inverter upper tube 200 and an inverter lower tube 300;
[0055] The inverter upper transistor 200 is packaged with two high-voltage electrical connection terminals: a drain (D) connection terminal 202 and a source (S) connection terminal 211, for high-voltage DC connection. The inverter lower transistor 300 is packaged with three high-voltage electrical connection terminals: a first drain (D) connection terminal 302, a second drain (D) connection terminal 314, and a source (S) connection terminal 311, for high-voltage DC connection and AC output. (See also...) Figure 9 The upper S-terminal 211 of the upper inverter tube and the first D-terminal 302 of the lower inverter tube are connected by laser welding to form the midpoint 411 of the inverter bridge arm. At this time, an inverter upper tube 200 and an inverter lower tube 300 are welded together to form an inverter bridge arm.
[0056] See Figure 7 The upper tube's drain (D) terminal 202 is located in the upper region of the inverter's upper tube, and the upper tube's sink (S) terminal 211 is located in the lower region of the inverter's upper tube 200. (See also...) Figure 8The first D-terminal connection terminal 302 of the lower tube is located in the upper region of the lower tube 300 of the inverter. The position of the first D-terminal connection terminal 302 matches the position of the upper tube D-terminal connection terminal 202, and the two can be connected. The second D-terminal connection terminal 314 of the lower tube is located in the lower region of the lower tube 300 of the inverter. The S-terminal connection terminal 311 of the lower tube is located in the middle region of the lower tube 300 of the inverter. The middle region refers to any position within the area enclosed by the upper edge, lower edge, and side edge of the lower tube 300 of the inverter. In this scheme, the upper edge, lower edge, and side edge refer to the region of the upper tube / lower tube of the inverter that is close to the upper edge, lower edge, and side edge.
[0057] To ensure reliable operation of the power semiconductor devices, the upper inverter transistor 200 and the lower inverter transistor 300 have corresponding monitoring terminals and temperature sensing elements. To facilitate the connection of these monitoring terminals and temperature sensing elements, they are respectively located on the sides of the upper inverter transistor 200 and the lower inverter transistor 300. Figure 7 As shown, the monitoring terminals and temperature sensing elements of the inverter upper tube 200 can be distributed on the right side of the inverter upper tube 200, such as... Figure 8 As shown, the monitoring terminals and temperature sensing element of the inverter lower diode 300 are located on the right side of the inverter lower diode 300. Alternatively, it can be arranged as follows... Figure 10 and Figure 11 As shown, the monitoring terminals and temperature sensing elements can also be distributed on the left side. The monitoring terminals and temperature sensing elements corresponding to the upper inverter diode 200 can be distributed on the same side of the upper inverter diode 200 or on both sides of the upper inverter diode 200. Similarly, the monitoring terminals and temperature sensing elements corresponding to the lower inverter diode 300 can be distributed on the same side of the lower inverter diode 300 or on both sides of the lower inverter diode 300. In this solution, the monitoring terminals and temperature sensing elements of the upper inverter diode 200 and the lower inverter diode 300 can be distributed on the same side.
[0058] In the technical solutions disclosed in the above embodiments of this application, the positions of the D-terminal connection terminal, S-terminal connection terminal, monitoring terminal and temperature detection element in the upper and lower inverter tubes are reasonably arranged so that when the power semiconductor device is connected, the AC copper bus and DC copper bus connected to the power semiconductor device do not cross, avoiding the situation where the parasitic inductance is reduced due to the crossing of the AC copper bus and DC bus copper bus, thereby effectively improving the reliability of the power semiconductor device.
[0059] Furthermore, in the above layout, after the terminals are connected to the drain and source terminals of the upper and lower transistor chips during operation, a power circuit with overlapping positive and negative terminals can be formed, which can reduce the inductance of the drive circuit.
[0060] Furthermore, the aforementioned monitoring terminals can be set on any side of the upper and lower transistor chips according to actual design requirements, facilitating system connection and improving the flexibility of system integration.
[0061] The upper transistor chip 209 corresponding to the upper transistor 200 of the inverter is fixed on the upper transistor ceramic substrate 208, and the lower transistor chip 309 corresponding to the lower transistor 300 of the inverter is fixed on the lower transistor ceramic substrate 308. The source (S) terminal of the upper transistor chip 209 is connected to the source (S) terminal connection terminal 211 of the upper transistor, and the source (S) terminal of the lower transistor chip 309 is connected to the source (S) terminal connection terminal 311 of the lower transistor.
[0062] The inverter upper transistor 200 includes N upper transistor chips 209, and the inverter lower transistor 300 includes N lower transistor chips 309, where N is a positive integer not less than 1. The gate (G) terminals of each upper transistor chip 209 are bonded together via metal connecting wires (which can be copper or aluminum wires). The metal connecting wires are upper transistor chip G terminal connecting conductors 214, which connect the gate terminals of each upper transistor chip to the upper transistor G terminal 215. The gate terminals of each lower transistor chip 309 are bonded together via metal connecting wires (which can be copper or aluminum wires). The metal connecting wires are lower transistor chip G terminal connecting conductors 317, which connect the gate terminals of each lower transistor chip to the lower transistor G terminal 318.
[0063] In this embodiment, each inverter upper transistor 200 can correspond to N upper transistor chips 209. The distance between the drain (D) terminal of each upper transistor chip 209 and the upper transistor D terminal connection terminal 202 can be equal, thereby ensuring that the connection impedance between the drain terminal of all upper transistor chips 209 and the upper transistor D terminal connection terminal 202 is equal. The distance between the source (S) terminal of each upper transistor chip 209 and the upper transistor S terminal connection terminal 211 is also equal, thereby ensuring that the connection impedance between the source terminal of all upper transistor chips 209 and the upper transistor S terminal connection terminal 211 is equal. This arrangement of upper transistor chips 209 and the design of electrical connection terminals achieves a balanced design of parallel electrical connection impedance of upper transistor chips 209, improving the current sharing consistency among upper transistor chips 209.
[0064] In this embodiment, each inverter lower transistor 300 corresponds to N lower transistor chips 309. The distance between the drain (D) terminal of each lower transistor chip 309 and the first drain terminal connection terminal 302 of the lower transistor is equal. The distance between the drain (D) terminal of each lower transistor chip 309 and the second drain terminal connection terminal 314 of the lower transistor is equal. The distance between the source (S) terminal of each lower transistor chip 309 and the source terminal connection terminal 311 of the lower transistor is equal.
[0065] In the above-disclosed scheme of this application embodiment, the lower surface of the upper transistor chip 209 is fixed to the upper transistor ceramic substrate 208 by welding or silver sintering. The S-pole of the upper surface of the upper transistor chip 209 is connected in parallel to the upper transistor S-pole connection terminal 211 by a metal connecting wire through silver sintering or laser welding, so that the distance between all upper transistor chips 209 and the upper transistor S-pole connection terminal 211 is equal. The lower surface of the lower transistor chip 309 is fixed to the lower transistor ceramic substrate 308 by welding or silver sintering. The S-pole of the upper surface of the lower transistor chip 309 is connected in parallel to the lower transistor S-pole connection terminal 311 by a metal connecting wire through silver sintering or laser welding, so that the distance between all lower transistor chips and the lower transistor S-pole connection terminal 311 is equal.
[0066] In the technical solution disclosed in this embodiment, the power semiconductor device can be customized with different numbers N of upper and lower transistor chips according to the current and voltage platform. That is, the number N of upper and lower transistor chips in the power semiconductor device can be configured according to design requirements. By directly customizing different upper and lower transistor chips according to the current and voltage platform, the complexity of subsequent power system packaging is reduced and the reliability of the overall system is improved. The value of N can be 1, 2, 3 or 4.
[0067] In this embodiment, the power semiconductor device can be connected to the copper busbar by welding. The welding process is easy to implement, reduces the difficulty of power system design, and simplifies the manufacturing process.
[0068] In this embodiment, the inverter upper transistor of the power semiconductor device is disposed on an upper transistor substrate. The upper transistor substrate may include: a first copper plating layer 205, a second copper plating layer 207, and a ceramic layer 206 of the upper transistor ceramic substrate. The upper transistor ceramic substrate is disposed between the first copper plating layer and the second copper plating layer of the upper transistor ceramic substrate. The inverter upper transistor is disposed on the first copper plating layer of the upper transistor ceramic substrate, and connection wires are provided between the upper-level chip and each port through the first copper plating layer.
[0069] In this embodiment, the connection method between each pole (D, S, G) of the upper transistor chip and each terminal in the upper transistor of the inverter is also disclosed. Specifically, the D pole of the upper transistor chip is connected to the upper transistor D pole connection terminal through the upper transistor connection conductor and the metal line in the first copper layer of the upper transistor ceramic substrate; the S pole of the upper transistor chip is connected to the upper transistor S pole connection terminal through the upper transistor S pole terminal connection conductor; and the G poles on each of the upper transistor chips are connected to the upper transistor G pole terminal in sequence through the upper transistor chip G pole connection conductor 214.
[0070] In addition to the upper diode drain (D) terminal, upper diode sink (S) terminal, and upper diode gate (G) terminal, the inverter upper diode also includes: an upper diode sink (K) terminal, an upper diode first temperature monitoring terminal, an upper diode second temperature monitoring terminal, an upper diode temperature detection element, and an upper diode drain (D) detection terminal. The first and second temperature monitoring terminals and the temperature detection element constitute a temperature sensor, which can be pre-sealed with epoxy resin using a mold. Pins are then inserted into the diode pins at appropriate positions. The upper diode sink (K) terminal is connected to the upper diode sink (S) terminal via a sink (K) terminal connecting conductor. The first and second temperature monitoring terminals are connected to both ends of the upper diode temperature detection element, which detects the temperature of the inverter upper diode through the first and second temperature monitoring terminals. The drain (D) detection terminal detects the drain voltage of the upper diode.
[0071] In this embodiment, the upper inverter tube is fixed on the upper tube substrate, and the lower inverter tube is fixed on the lower tube substrate.
[0072] The upper tube substrate includes: a first copper plating layer of the upper tube ceramic substrate, a second copper plating layer of the upper tube ceramic substrate, and a ceramic layer of the upper tube ceramic substrate; the upper tube ceramic substrate is disposed between the first copper plating layer and the second copper plating layer of the upper tube ceramic substrate; the inverter upper tube is disposed on the first copper plating layer of the upper tube ceramic substrate.
[0073] The lower diode substrate includes: a first copper plating layer of the lower diode ceramic substrate, a second copper plating layer of the lower diode ceramic substrate, and a ceramic layer of the lower diode ceramic substrate; the lower diode ceramic substrate is disposed between the first copper plating layer and the second copper plating layer of the lower diode ceramic substrate; the lower diode of the inverter is disposed on the first copper plating layer of the lower diode ceramic substrate.
[0074] The drain (D) terminal of the corresponding upper transistor chip of the inverter is connected to the upper transistor D terminal connection terminal through the upper transistor connection conductor and the metal line in the first copper layer of the upper transistor ceramic substrate; the source (S) terminal of the upper transistor chip is connected to the upper transistor S terminal connection terminal through the upper transistor S terminal connection conductor; the gate (G) terminals on each upper transistor chip are connected to the upper transistor G terminal terminal in sequence through the upper transistor G terminal connection conductor.
[0075] The drain (D) terminal of the corresponding lower transistor chip of the inverter is connected to the first drain terminal and the second drain terminal through the lower transistor connecting conductor and the metal line in the first copper layer of the lower transistor ceramic substrate; the source (S) terminal of the lower transistor chip is connected to the lower transistor S terminal through the lower transistor S terminal connecting conductor; the gate (G) terminals on each lower transistor chip are connected to the lower transistor G terminal terminal in sequence through the lower transistor G terminal connecting conductor.
[0076] In one specific embodiment, the composition of the power semiconductor device and the labels, names and functions of each component are shown in Table 1.
[0077] serial number name describe 200 Inverter top tube The power semiconductor device on the upper arm of the inverter bridge, often referred to as the "upper arm". 201 Upper tube outer casing Top-mount package 202 Upper tube D extreme sub One of the electrical connection terminals of the upper tube, the upper tube D (or C) terminal, is exposed outside the upper tube casing, realizing the external electrical connection function of the upper tube D (or C) terminal. 203 Upper tube D terminal connector conductor The conductor connected to the D (or C) terminal of the upper tube is encased inside the upper tube casing and soldered to the first copper plating layer of the upper tube's ceramic substrate. 204 Upper tube D-polar conductor To achieve the electrical connection function of the upper transistor chip's drain (or collector) terminal, it consists of the upper transistor's drain connection terminal and the upper transistor's drain terminal connecting conductor. 205 First copper layer of upper tube ceramic substrate Serving as a welding carrier for the inverter's upper transistor chip, upper transistor D-terminal conductor, monitoring terminals or components (221, 215, 216, 218, 219, 220), it achieves electrical or thermal conductivity; the first copper-clad layer 205 of the upper transistor ceramic substrate is welded to the D-terminal (or C-terminal) of the upper transistor chip 209. 206 Upper tube ceramic substrate ceramic layer To achieve electrical insulation and thermal conductivity between the first copper layer 205 and the second copper layer 207 of the upper tube ceramic substrate. 207 Second copper cladding layer of upper tube ceramic substrate External heat conduction surface of inverter upper tube 200 208 Top tube ceramic substrate Double-sided copper-clad ceramic substrate, or simply ceramic substrate or DCB, consists of a first copper-clad layer 205 on the upper tube ceramic substrate, a ceramic layer 206 on the upper tube ceramic substrate, and a second copper-clad layer 207 on the upper tube ceramic substrate. 209 upper-side chip A MOSFET chip, or simply a chip, has a drain (D) terminal on its bottom surface and source (S) and gate (G) terminals on its top surface; or an IGBT chip, or simply a chip, has a collector (C) terminal on its bottom surface and emitter (E) and gate (G) terminals on its top surface. 210 Upper tube S-terminal connecting conductor The S (or E) terminal of the upper transistor is connected to a conductor, which is encased inside the upper transistor housing 201 and connected to the S (or E) terminal of the upper transistor chip 209. 211 Upper tube S-end One of the electrical connection terminals of the upper tube, the upper tube S (or E) terminal, is exposed outside the upper tube housing 201, realizing the external electrical connection function of the upper tube S (or E) terminal. 212 Upper tube S-pole conductor To achieve electrical connection of the upper transistor chip's source (or emitter) terminal, it consists of the upper transistor's source terminal connector 210 and the upper transistor's source terminal 211. 213 upper transistor chip G terminal upper transistor chip G terminal 214 upper transistor chip gate connection conductor The gate (G) terminal of the upper transistor chip is connected to a conductor, which connects the gate of the upper transistor chip to the gate terminal 215 of the upper transistor. 215 Upper tube G extreme sub One of the monitoring terminals of the upper transistor is connected to the gate (G) terminal of the chip inside the upper transistor. 216 Upper tube K-end unit One of the upper tube monitoring terminals is connected to the upper tube's S-end terminal connecting conductor 210 via a Kelvin connection. 217 upper tube K-pole connection conductor Connect the upper tube S-terminal connecting conductor 210 and the upper tube K-terminal 216 together. 218 Upper tube first temperature monitoring terminal One of the upper tube monitoring terminals, the upper tube first temperature monitoring terminal, is connected to one end of the upper tube temperature sensing element 219. 219 Upper tube temperature sensing element Used to detect the temperature of the upper tube. 220 Upper tube second temperature monitoring terminal One of the upper tube monitoring terminals, the second upper tube temperature monitoring terminal, is connected to the other end of the upper tube temperature sensing element 219. 221 Upper tube D-terminal detection terminal One of the monitoring terminals of the upper tube is used to detect the voltage at the drain (or collector) terminal of the upper tube. 222 Upper tube D-pole detection terminal connection conductor Connect the upper tube's D-terminal detection terminal 221 and the lower tube's ceramic substrate's first copper plating layer 305 together. 300 inverter lower diode The lower-side power semiconductor device in the inverter bridge arm, often referred to as the "lower-side transistor". 301 Lower tube housing The housing of the lower tube package 302 The first terminal of the lower tube's drain (D) One of the electrical connection terminals of the lower tube, the first terminal of the lower tube's D (or C) pole, is exposed outside the lower tube housing 301, realizing the first external electrical connection function of the lower tube's D (or C) pole. 303 The conductor connected to the first terminal of the lower tube's drain (D) pole. The first terminal of the lower tube's drain (or collector) is connected to a conductor, which is encased inside the lower tube's outer casing 301 and soldered to the first copper-clad layer 305 of the lower tube's ceramic substrate. 304 The first conductor of the lower tube's drain pole The first electrical connection function of the drain (or collector) terminal of the lower transistor chip is achieved by components 302 and 303. 305 First copper layer of the lower tube ceramic substrate As a welding carrier for the lower diode chip 309, conductors (lower diode D-terminal first conductor 304, lower diode D-terminal second terminal connecting conductor 313), and monitoring terminals or components (324, 318, 319, 321, 322, 323) of the lower diode 300 in the inverter, it realizes the functions of electrical conductivity or thermal conductivity; the first copper-clad layer 305 of the lower diode ceramic substrate is welded to the D-terminal (or C-terminal) of the lower diode chip 309. 306 Bottom tube ceramic substrate ceramic layer To achieve electrical insulation and thermal conductivity between the first copper layer 305 and the second copper layer 307 of the lower tube ceramic substrate. 307 Second copper layer of the lower tube ceramic substrate External heat-conducting surface of inverter bottom tube 300 308 Bottom tube ceramic substrate Double-sided copper-clad ceramic substrate, or simply ceramic substrate or DCB, consists of a first copper-clad layer 305 on the lower-side ceramic substrate, a ceramic layer 306 on the lower-side ceramic substrate, and a second copper-clad layer 307 on the lower-side ceramic substrate. 309 Lower transistor chip A MOSFET chip, or simply a chip, has its bottom surface as the drain (D) terminal and its top surface as the source (S) and gate (G). Alternatively, an IGBT chip, or simply a chip, has its bottom surface as the collector (C) terminal and its top surface as the emitter (E) and gate (G). 310 Lower tube S-terminal connector conductor The source (or emitter) terminal of the lower transistor is connected to a conductor, which is encased inside the lower transistor housing 301 and connected to the source (or emitter) of the lower transistor chip 309. 311 Lower tube S-terminal One of the electrical connection terminals of the lower tube, the lower tube S (or E) terminal, is located on the upper surface of the lower tube housing 301 and exposed outside the lower tube housing 301, realizing the external electrical connection function of the lower tube S (or E) terminal. 312 Lower tube S-pole conductor To achieve electrical connection of the lower transistor's source (or emitter) terminal, it consists of the lower transistor's source terminal connector 310 and the lower transistor's source terminal 311. 313 The conductor connected to the second terminal of the lower tube's drain (D) pole. The second terminal of the lower tube's drain (or collector) is connected to a conductor, which is encased inside the lower tube's outer casing 301 and soldered to the first copper-clad layer 305 of the lower tube's ceramic substrate. 314 Second terminal of the lower tube's D pole One of the electrical connection terminals of the lower tube, the second terminal of the lower tube's D (or C) pole, is exposed outside the lower tube housing 301, realizing the function of a second external electrical connection for the lower tube's D (or C) pole. 315 Second conductor of the lower tube (D pole) To achieve the second electrical connection function of the drain (or collector) terminal of the lower transistor chip, it consists of conductor 313 connecting the second terminal of the drain of the lower transistor and the second terminal 314 of the drain of the lower transistor. 316 lower transistor chip G terminal lower transistor chip G terminal 317 The gate connection conductor of the lower transistor chip The gate (G) terminal of the lower transistor chip is connected to a conductor, and the gate (G) terminal of the lower transistor chip is connected to the gate terminal 318 of the lower transistor. 318 Lower tube G extreme sub One of the monitoring terminals of the lower transistor is connected to the gate (G) terminal of the chip inside the lower transistor. 319 Lower tube K-end One of the lower tube monitoring terminals is connected to the lower tube S-terminal connecting conductor 310 via a Kelvin connection. 320 The lower tube's K-pole is connected to the conductor. Connect the S-terminal connector 310 and the K-terminal connector 319 of the lower tube together. 321 Lower tube first temperature monitoring terminal One of the lower tube monitoring terminals, the first temperature monitoring terminal of the lower tube, is connected to one end of the lower tube temperature sensing element 322. 322 Lower tube temperature sensing element The lower tube temperature sensing element is used to detect the temperature of the lower tube. 323 Second temperature monitoring terminal of lower tube One of the lower tube monitoring terminals, the second temperature monitoring terminal of the lower tube, is connected to the other end of the lower tube temperature sensing element 322. 324 Lower tube D-terminal detection terminal One of the monitoring terminals of the lower tube, used to detect the voltage at the drain (or collector) terminal of the lower tube. 325 Lower tube D-pole detection terminal connection conductor Connect the D-terminal detection terminal 324 of the lower tube and the first copper layer 305 of the ceramic substrate of the lower tube together. 411 Inverter arm midpoint The connection point between the upper S-terminal 211 and the lower D-terminal first terminal 302 is the midpoint of the inverter bridge arm.
[0078] An electronic device comprising: any one of the above-mentioned power semiconductor devices, wherein the electronic device is a household appliance or an automobile.
[0079] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0080] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, and also include other elements not expressly listed, or elements inherent to such an article or device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device that includes said element.
[0081] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
[0082] The above description is only a preferred embodiment of the present utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present utility model, and these improvements and modifications should also be considered within the protection scope of the present utility model.
Claims
1. A power semiconductor device, characterized in that, include: At least one inverter bridge arm, each inverter bridge arm including an upper inverter tube and a lower inverter tube, the upper inverter tube being encapsulated with an upper tube drain (D) connection terminal and an upper tube source (S) connection terminal, the upper tube drain (D) connection terminal being located at the upper side of the upper inverter tube, the upper tube source (S) connection terminal being located at the lower side of the upper inverter tube, the lower inverter tube being encapsulated with a lower tube first drain (D) connection terminal, a lower tube second drain (D) connection terminal, and a lower tube source (S) connection terminal, the upper tube source (S) connection terminal being connected to the lower tube first drain (D) connection terminal to form the midpoint of the inverter bridge arm, the lower tube first drain (D) connection terminal being located at the upper side of the lower inverter tube and matching the position of the upper tube drain (D) connection terminal, the lower tube second drain (D) connection terminal being located at the lower side of the lower inverter tube, and the lower tube source (S) connection terminal being located in the middle region of the lower inverter tube; The monitoring terminals and temperature detection elements of the upper and lower inverter tubes are respectively located on the sides of the upper and lower inverter tubes.
2. The power semiconductor device according to claim 1, characterized in that, The monitoring terminals and temperature sensing elements of the inverter upper tube are located on the same side of the inverter upper tube. The monitoring terminals and temperature sensing elements of the inverter's lower diode are located on the same side of the inverter's lower diode.
3. The power semiconductor device according to claim 2, characterized in that, The side of the inverter with the monitoring terminals and temperature sensing elements located on the upper tube is directly opposite the side of the inverter with the monitoring terminals and temperature sensing elements located on the lower tube.
4. The power semiconductor device according to claim 1, characterized in that, The inverter upper transistor includes N upper transistor chips, and the inverter lower transistor includes N lower transistor chips, where N is a positive integer not less than 1. The source-side (S) terminals of each upper transistor chip are bonded together by metal connecting wires.
5. The power semiconductor device according to claim 1, characterized in that, The monitoring terminal includes a K-terminal, a D-terminal detection terminal, a first temperature monitoring terminal, and a second temperature monitoring terminal. The K-terminal is connected to the S-terminal of the corresponding upper or lower transistor chip via a K-terminal connecting conductor. The D-terminal detection terminal is used to detect the D-terminal voltage of the corresponding upper or lower transistor chip. The first temperature monitoring terminal and the second temperature monitoring terminal are disposed at both ends of the temperature detection element.
6. The power semiconductor device according to claim 4, characterized in that, The upper inverter tube is fixed on the upper tube substrate, and the lower inverter tube is fixed on the lower tube substrate. The upper tube substrate includes: a first copper plating layer of the upper tube ceramic substrate, a second copper plating layer of the upper tube ceramic substrate, and a ceramic layer of the upper tube ceramic substrate; the upper tube ceramic substrate is disposed between the first copper plating layer and the second copper plating layer of the upper tube ceramic substrate; the inverter upper tube is disposed on the first copper plating layer of the upper tube ceramic substrate. The lower diode substrate includes: a first copper plating layer of the lower diode ceramic substrate, a second copper plating layer of the lower diode ceramic substrate, and a ceramic layer of the lower diode ceramic substrate; the lower diode ceramic substrate is disposed between the first copper plating layer and the second copper plating layer of the lower diode ceramic substrate; the lower diode of the inverter is disposed on the first copper plating layer of the lower diode ceramic substrate.
7. The power semiconductor device according to claim 6, characterized in that, The drain (D) of the upper transistor chip is connected to the upper transistor drain terminal via the upper transistor connecting conductor and the metal wire in the first copper layer of the upper transistor ceramic substrate. The S-pole of the upper transistor chip is connected to the S-pole connection terminal of the upper transistor through the upper transistor S-pole terminal connection conductor; The gate (G) terminals on each of the aforementioned upper-side chips are connected to the upper-side G terminal terminals via a gate-side connection conductor.
8. The power semiconductor device according to claim 6, characterized in that, The drain (D) terminal of the lower transistor chip is connected to the first D terminal connection terminal and the second D terminal connection terminal of the lower transistor through the lower transistor connecting conductor and the metal wire in the first copper layer of the lower transistor ceramic substrate. The S-pole of the lower transistor chip is connected to the S-pole connection terminal of the lower transistor through the lower transistor S-pole terminal connection conductor; The gate (G) terminals on each of the lower transistor chips are connected to the lower transistor G terminal terminal via a gate-connected conductor.
9. An electronic device, characterized in that, include: The power semiconductor device according to any one of claims 1-8.
10. The electronic device according to claim 9, characterized in that, The electronic device is a household appliance or a car.