Stacked hole and stacked disc chip packaging structure for transmitting high-speed signals

Abstract

The utility model discloses a stacked-hole stacked-disc chip packaging structure used for transmitting high-speed signals, which comprises a ball grid array (BGA) solder ball, a bottom layer area and a top layer area, and each layer between Ln-4 and Ln / 2 is provided with a plated through hole (PTH) expanded layer hole for stacked-hole alignment. Avoidance is arranged on each layer in the areas from Ln-4 to Ln-1 and the bottom layer. The micropores of every adjacent t layers from L1 to Ln / 2 are stacked; the micropores in each layer from Ln-3 to Ln are overlapped, and a micropore interlayer avoiding area is arranged in Ln-4 and is overlapped with the micropores in Ln-3; and BUMP salient points are also arranged in the overlapped micropores from Ln to Ln-3. According to the invention, a plurality of impedance discontinuous points on a transmission path are combined into three parts, the impedance of each part is controlled, and the impedance fluctuation is ensured to be reduced; in addition, through hole stacking and a shared avoiding area, space is saved, micro-ground via holes can be densely added, high-speed signal backflow and mutual isolation are carried out, and the transmission effect is guaranteed.

Description

Technical Field

[0001] This utility model relates to the field of switching chip technology, specifically to a stacked via and disk chip packaging structure for transmitting high-speed signals. Background Technology

[0002] In high-speed differential signals with speeds above 10Gbps, such as 10Gbps, 12.5Gbps, 16Gbps, 25Gbps, 32Gbps, 56Gbps and higher, in order to ensure low-loss signal transmission, the physical transmission channel is required to have small impedance fluctuations, thereby reducing signal reflection and maintaining the integrity of the transmitted signal.

[0003] However, both the DIE bump and BGA ball on the packaging substrate are densely packed. BGA stands for Ball Grid Array, and DIE bump refers to the chip bump, where DIE stands for chip or die, and bump refers to a bump or spike. In high-speed signal packaging design, firstly, it is necessary to overcome the difficulty of high-density wiring at both ends of the bump and BGA; secondly, it is necessary to ensure that the high-speed signal still has small impedance fluctuations after passing through various impedance discontinuities such as BGA pads, via pads, via anti-pads, BUMP pads, microvia anti-pads, and microvia pads. How to achieve both of these aspects simultaneously has become a key technical problem that needs to be overcome in packaging substrates. Utility Model Content

[0004] To address the aforementioned technical problems, the purpose of this application is to propose a stacked via and disk chip package structure for transmitting high-speed signals. By merging multiple impedance discontinuities on the high-speed signal transmission path into three parts and controlling the impedance of each part, the overall impedance consistency on the transmission path is ensured. Furthermore, by stacking vias and merging various avoidance and anti-solder pads, space is effectively saved, allowing for the dense addition of micro-ground vias for high-speed signal return and mutual isolation, thus ensuring the transmission effect of high-speed signals.

[0005] This was achieved through the following technical solutions:

[0006] A stacked via and stacked disk chip package structure for transmitting high-speed signals includes at least BGA solder balls and a package substrate with n layers from L_1 to L_n, where n=2k and k is an integer not less than 5; L_1 to L_n / 2 is the bottom layer region, and L_n-4 to L_n is the top layer region. Each layer between L_n-4 and L_n / 2 is provided with PTH expansion vias for via alignment; wherein each layer from L_n-4 to L_n-1 and each layer in the bottom layer region is provided with ground copper avoidance, and the boundary I of the avoidance area is the same for each layer in the bottom layer region, B GA solder balls connect to L_1, and the connected area is located within the avoidance area boundary I in L_1. The avoidance area boundary II of each layer from L_n-4 to L_n-1 is the same. In L_1 to L_n / 2, micro-holes are stacked according to every t adjacent layers starting from L_1, where t is an integer not less than 3. The micro-holes of each layer from L_n-3 to L_n are overlapped. A micro-hole partition avoidance area is set in L_n-4, and the micro-hole partition avoidance area overlaps with the micro-holes in L_n-3. BUMP bumps are also set in the overlapping micro-holes from L_n to L_n-3.

[0007] Preferably, overlapping ground copper avoidance areas are provided in L_n-4 to L_n-1 of the top layer area, and the expansion via is located in the ground copper avoidance area in L_n-4. Since the dielectric of each layer is relatively thin in actual chip packaging, the use of overlapping multi-layer ground copper avoidance areas reduces parasitic capacitance caused by the thin dielectric, which helps to ensure the quality of high-speed signal transmission.

[0008] Preferably, the microvia between L_n-4 and L_n-3 is located within the ground copper strip clearance area of ​​L_n-4. This microvia's location within the corresponding ground copper strip clearance area reduces impedance changes and minimizes impedance fluctuations.

[0009] Preferably, the anti-pad of the microvia in L_n-4 between L_n-4 and L_n-3 is directly connected to the via pad in L_n-4. The direct connection between the anti-pad of the microvia and the via pad forms a low-impedance vertical channel, which reduces impedance fluctuations, improves space utilization, and saves more space.

[0010] Preferably, a reserved copper layer serves as a spacer between the micropores and the micropore partition clearance area in L_n-4. This reserved spacer can suppress any crosstalk that may exist between them.

[0011] Preferably, each expanded-layer hole and each micro-hole is provided with multiple micro-ground vias or multiple high-speed differential signal vias. Providing multiple high-speed differential signal vias can support the transmission of multiple high-speed differential signals, while multiple micro-ground vias can reduce ground bounce noise.

[0012] The advantages of this application compared to the prior art are:

[0013] The technical solution of this application combines multiple impedance discontinuities on the high-speed signal transmission path into three parts, controls the impedance of each part, reduces impedance fluctuations, and thus ensures the consistency of the overall impedance on the transmission path. In addition, by stacking vias and merging various avoidance and anti-pads, space is effectively saved, so that micro-ground vias can be densely added for high-speed signal return and mutual isolation, ensuring the transmission effect of high-speed signals. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a stacked via and disk chip package structure for transmitting high-speed signals.

[0015] Figure 2 This is a comparative schematic diagram of high-speed differential signal vias and micro-ground vias. Detailed Implementation

[0016] The following will refer to the appendices in the embodiments of this application. Figure 1 and 2 The technical solutions in the embodiments of this application will be described in detail.

[0017] like Figure 1 The diagram shows a stacked via and disk chip package structure for transmitting high-speed signals. It illustrates an n-layer package substrate, which is connected to the BGA solder balls at the bottom and the BUMP bumps at the top. By stacking and merging multiple holes and regions on the multi-layer package substrate, a stacked via and disk package structure consisting of BGA solder balls, bottom layer region, PTH expansion holes, top layer region, and BUMP bumps is finally formed, which effectively reduces impedance fluctuations and saves more unused space.

[0018] In this stacked via and disk chip packaging structure, the n layers of the packaging substrate are L_1, L_2, L_3, ..., L_n, where n = 2k and k is an integer not less than 5. Each layer uses the same ground copper trace for laying, and then the ground copper trace of each layer is designed separately. L_1 to L_n / 2 is the bottom layer area, and L_n-4 to L_n is the top layer area. Each layer between L_n-4 and L_n / 2 is provided with PTH expansion vias for via alignment.

[0019] In this embodiment, each layer in the top layer (L_n-4 to L_n-1) and each layer in the bottom layer (L_1 to L_n / 2) has a ground copper strip avoidance area, which is an empty space. The boundary of the avoidance area is the region boundary. In the bottom layer (L_1 to L_n / 2), the boundary I of the avoidance area is the same for each layer, which facilitates alignment for subsequent structural design. The microvias are stacked according to every t adjacent layers starting from L_1, where t is an integer not less than 3. For example, if t is 3, the microvias in L_1, L_2, and L_3 are stacked and share a microvia channel A; then, the microvias in L_3, L_4, and L_5 are stacked and share another microvia channel B; and so on, up to the L_n / 2 layer. At the same time, there is also an avoidance area between every two adjacent microvia channels on the boundary layer. For example, in the L_3 layer, there is a corresponding avoidance area between microvia channels A and B to suppress crosstalk.

[0020] Furthermore, if n / 2 cannot satisfy the stacking of micropores in every three adjacent layers, for example, when n=12, then the micropore channel connected by L_6 will only be the micropore between L_6 and L_5.

[0021] Furthermore, for the parameter t when stacking micropores, in order to increase the impedance continuity between different layers, the number of t should be at least 3.

[0022] In this embodiment, the BGA solder ball connects to L_1 and the connected area is located within the boundary I of the avoidance area in L_1. The microvias between L_1 and L_3 are also located within the range where the BGA solder ball connects to the boundary I of the area. Thus, each area used for avoidance from L_1 to the via expansion layer can be shared by the via expansion layer and each microvia, thereby saving a lot of space and making the connection of each part of the bottom layer more orderly and the impedance fluctuation smaller.

[0023] In this embodiment, in the top layer L_n-4 to L_n-1, the boundary II of the avoidance area is the same for each layer. Boundary II and boundary I are independent of each other and do not require forced alignment. The microvias in each layer from L_n-3 to L_n overlap to form a microvia channel C, and the BUMP bump is inserted into this microvia channel C. Furthermore, a microvia barrier avoidance area is provided in L_n-4, which overlaps with the microvias in L_n-3. This allows the BUMP bump and the microvia channel C to share anti-pads during actual packaging and soldering. Anti-pads are areas around each microvia where ground copper is intentionally omitted, i.e., the avoidance areas, used for insulation.

[0024] Furthermore, in the top layer region L_n-4 to L_n-1, the expansion vias are located within the ground copper avoidance area in L_n-4. Since the dielectric material of each layer is relatively thin in actual chip packaging, for example, it may be less than 30 micrometers or between 30 and 60 micrometers, overlapping multi-layer ground copper avoidance areas are used to reduce parasitic capacitance that may be caused by the thin dielectric material, thus ensuring the quality of high-speed signal transmission.

[0025] In this embodiment, the microvia between L_n-4 and L_n-3 is located within the ground copper avoidance area of ​​L_n-4. Furthermore, the anti-pad of the microvia between L_n-4 and L_n-3 in L_n-4 directly connects to the via pad of the expansion layer in L_n-4. Thus, the expansion layer, top layer area, and BUMP bumps can share the corresponding avoidance area between L_n-4 and L_n. Simultaneously, the anti-pad of the microvia directly connects to the via pad, forming a low-impedance vertical channel, which reduces impedance fluctuations, improves space utilization, and saves more space.

[0026] In this embodiment, a reserved copper layer is used as a spacer between the microvias and the microvia partition avoidance area in L_n-4. This reserved spacer can suppress any crosstalk that may exist between them.

[0027] In this embodiment, multiple micro-ground vias or multiple high-speed differential signal vias are provided in each expanded-layer via and each micro-via. Providing multiple high-speed differential signal vias can support the transmission of multiple high-speed differential signals, while multiple micro-ground vias can reduce ground bounce noise.

[0028] In summary, this application combines multiple impedance discontinuities in the high-speed signal transmission path into three parts and controls the impedance of each part, thereby ensuring the consistency of the overall impedance along the transmission path and effectively reducing impedance fluctuations. In addition, by stacking vias and merging various avoidance and anti-pads, space is effectively saved, allowing for the dense addition of micro-ground vias for high-speed signal return and mutual isolation, ensuring the transmission effect of high-speed signals, which is a significant improvement.

[0029] The above embodiments are only for illustrating the technical concept of this application and should not be used to limit the scope of protection of this application. Any modifications made to the technical solution based on the technical concept proposed in this application shall fall within the scope of protection of this application.

Claims

1. A stacked via / disk chip package structure for transmitting high-speed signals, characterized in that, It includes at least BGA solder balls and a package substrate with n layers from L_1 to L_n, where n=2k and k is an integer not less than 5; L_1 to L_n / 2 is the bottom layer area, L_n-4 to L_n is the top layer area, and each layer between L_n-4 and L_n / 2 is provided with PTH expansion holes for stacking via alignment. In this design, each layer from L_n-4 to L_n-1 and each layer in the bottom layer have a ground copper shielding. The boundary I of the shielding area is the same for each layer in the bottom layer. The BGA solder ball connects to L_1 and the connected area is located within the boundary I of the shielding area in L_1. The boundary II of the shielding area is the same for each layer from L_n-4 to L_n-1. In L_1 to L_n / 2, the microvias are stacked according to every t adjacent layers starting from L_1, where t is an integer not less than 3. The microvias in each layer from L_n-3 to L_n are overlapped. A microvia partition layer shielding area is set in L_n-4, and the microvia partition layer shielding area overlaps with the microvias in L_n-3. BUMP bumps are also set in the overlapping microvias in L_n to L_n-3.

2. The stacked via and stacked disk chip packaging structure for transmitting high-speed signals according to claim 1, characterized in that, In the top layer area, from L_n-4 to L_n-1, there are overlapping ground copper sheet avoidance areas. The expansion hole is located in the ground copper sheet avoidance area in L_n-4.

3. The stacked via and stacked disk chip packaging structure for transmitting high-speed signals according to claim 2, characterized in that, The micropores between L_n-4 and L_n-3 are located within the copper sheet avoidance area in L_n-4.

4. The stacked via and stacked disk chip packaging structure for transmitting high-speed signals according to claim 1, characterized in that, The microvias between L_n-4 and L_n-3 have anti-pads in L_n-4, which are directly connected to the vias in L_n-4.

5. The stacked via and stacked disk chip packaging structure for transmitting high-speed signals according to claim 1, characterized in that, In L_n-4, a copper sheet is reserved between the micropores and the micropore partition clearance area as a spacer.

6. The stacked via and stacked disk chip packaging structure for transmitting high-speed signals according to claim 1, characterized in that, Multiple micro-ground vias or multiple high-speed differential signal vias are provided in each expansion hole and each micro-via.

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