PCB circuit boards, layout methods and chips

Abstract

This application relates to a PCB circuit board, a layout method, and a chip. The PCB circuit board includes a board body and vias. The board body includes multiple layers connected by vias. The vias include signal vias and ground vias. In the trace extension direction of the PCB circuit board, the spacing between each signal via and an adjacent ground via, and the spacing between each signal via and other adjacent signal vias, are defined as a first spacing. The spacing between each ground via and other ground vias is defined as a second spacing. Both the first and second spacings are less than a reference spacing and greater than or equal to a minimum process spacing. The reference spacing is the spacing between solder balls in the ball array layer of the ball grid array package structure corresponding to the PCB circuit board. Using this PCB circuit board can reduce signal line crosstalk.

Description

Technical Field

[0001] This application relates to the field of printed circuit technology, and in particular to a PCB circuit board, layout method, and chip. Background Technology

[0002] With the continuous development of chip technology, various chips, such as PCIe chips, are becoming increasingly larger. In order to cope with the challenges of the surge in chip I / O numbers and product miniaturization, via-in-pad has become a key technology for high-density interconnects. Among them, for chips in ball grid array packages, via-in-pad is a design method that integrates vias directly under the pads.

[0003] However, the traditional via design suffers from severe crosstalk on high-speed signal lines. Summary of the Invention

[0004] Based on this, a PCB circuit board, layout method, and chip that can reduce the impact of signal line crosstalk are provided.

[0005] In a first aspect, this application provides a PCB circuit board. The PCB circuit board includes a board body and vias. The board body includes multiple board layers, which are connected to each other through vias. The vias include signal vias and ground vias. In the trace extension direction of the PCB circuit board, the spacing between each signal via and an adjacent ground via, and the spacing between each signal via and other adjacent signal vias, are a first spacing. The spacing between each ground via and other ground vias is a second spacing. Both the first spacing and the second spacing are less than a reference spacing and greater than or equal to a minimum process spacing. The reference spacing is the spacing between solder balls in the ball array layer of the ball grid array package structure corresponding to the PCB circuit board.

[0006] In one embodiment, the solder balls in the ball array layer are arranged in a grid pattern; the spacing between each solder ball and its adjacent solder balls is equal.

[0007] In one embodiment, the first spacing is determined according to the anti-signal crosstalk requirements of the PCB circuit board; the first spacing includes: the spacing between each signal via and the adjacent ground via, and the spacing between each signal via and other adjacent signal vias; the second spacing is determined according to the minimum spacing achievable by the PCB circuit board manufacturing process; wherein, the difference between the second spacing and the minimum spacing is less than a first difference threshold, and the second spacing includes: the spacing between each ground via and other ground vias.

[0008] In one embodiment, the reference spacing is determined based on the layout space size and layout requirements of the target chip to which the ball grid array package structure and PCB board belong.

[0009] In one embodiment, the first spacing is greater than the second spacing.

[0010] In one embodiment, the first spacing is in the range of 0.665 mm to 0.735 mm; the second spacing is in the range of 0.618 mm to 0.683 mm; and the reference spacing is in the range of 0.9 mm to 1.0 mm.

[0011] In one embodiment, the multiple board layers include multiple signal line layers, multiple ground plane layers, and other board layers; the two adjacent layers of each signal line layer are ground plane layers.

[0012] In one embodiment, the plurality of signal line layers include a plurality of first signal line layers and a plurality of second signal line layers, wherein the number of layers in which each first signal line layer is located is symmetrical with respect to the center plane of the board; the plurality of ground plane layers include a plurality of first ground plane layers and a plurality of second ground plane layers, wherein the number of layers in which each first ground plane layer is located is symmetrical with respect to the center plane of the board.

[0013] In one embodiment, the signal line layer includes signal traces connected to signal vias; the distance between the signal traces and other vias is greater than or equal to a preset distance threshold; the preset distance threshold is determined based on the anti-signal crosstalk requirements between the signal traces and other vias.

[0014] In one embodiment, the difference between a preset distance threshold and 2 mil is less than a second difference threshold.

[0015] Secondly, this application also provides a PCB circuit board layout method. This method is used to determine the layout of the PCB circuit board in any of the embodiments of the first aspect described above. The method includes: obtaining a reference spacing, the reference spacing being the spacing between solder balls in the ball array layer of a ball grid array package structure corresponding to the PCB circuit board; determining a first spacing and a second spacing based on the reference spacing; determining the layout position of each signal hole on the PCB circuit board based on the first spacing; determining the layout position of each ground hole on the PCB circuit board based on the first spacing and the second spacing; wherein, in the trace extension direction of the PCB circuit board, the spacing between each signal hole and an adjacent ground hole, and the spacing between each signal hole and other adjacent signal holes are the first spacing; and the spacing between each ground hole and other ground holes is the second spacing.

[0016] Thirdly, this application also provides a chip, which includes a PCB circuit board as described in any of the embodiments of the first aspect above and a ball grid array package structure corresponding to the PCB circuit board as described in any of the embodiments of the first aspect above.

[0017] The aforementioned PCB circuit board, layout method, and chip include a PCB circuit board comprising a board body and vias. The board body comprises multiple layers connected by vias. The vias include signal vias and ground vias. In the trace extension direction of the PCB circuit board, the spacing between each signal via and an adjacent ground via, and the spacing between each signal via and other adjacent signal vias, constitute a first spacing. The spacing between each ground via and other ground vias constitutes a second spacing. Both the first and second spacings are less than a reference spacing and greater than or equal to the minimum process spacing. The reference spacing is the spacing of solder balls in the ball array layer of the ball grid array package structure corresponding to the PCB circuit board. That is, the distribution position of the vias is offset relative to the distribution position of the solder balls. Therefore, in the non-trace extension direction, the spacing between a pair of signal lines corresponding to adjacent signal vias will increase, thereby reducing crosstalk between signal lines. Furthermore, since the distribution position of the vias is offset relative to the distribution position of the solder balls, more ground vias can be placed in the same size PCB board, increasing the isolation between signal lines and further reducing the impact of crosstalk.

[0018] Other beneficial effects of this application will be further explained and illustrated in detail when combined with the accompanying drawings and specific embodiments. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a top view of the via distribution on a PCB circuit board in one embodiment;

[0021] Figure 2 This is a top view schematic diagram of the relative positions of the solder balls and vias in one embodiment;

[0022] Figure 3 This is a schematic diagram of the via spacing in one embodiment;

[0023] Figure 4 This is a side view of the PCB circuit board traces in one embodiment;

[0024] Figure 5 This is a 3D side view of a PCB circuit board in one embodiment;

[0025] Figure 6 This is a wiring diagram in one embodiment;

[0026] Figure 7 This is a schematic diagram comparing crosstalk results in one embodiment. Detailed Implementation

[0027] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that many specific details are set forth in the following description in order to provide a full understanding of this application, but this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0029] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0030] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0031] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0032] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0033] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0034] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0035] With the continuous development of chip technology, various chips, such as PCIe chips, are becoming increasingly larger. Since its initial release in 2003, PCIExpress (PCIe) has become an indispensable high-speed data transmission interface in modern computers and embedded systems. From the initial PCIe 1.0 single lane 2.5Gbps to the latest PCIe 6.0 single lane 64Gbps, PCIe technology has undergone several evolutions, each version achieving significant improvements in transmission rate and bandwidth. In order to support the PCIe protocol, the SerDes (serializer / deserializer) rate of chips has also increased, and the chip size has become larger. The more channels there are for high-speed signals, the denser the arrangement on the chip's BGA (Ball Grid Array) becomes. For PCB design, how to orderly fan out all high-speed signal lines from the dense BGA area while maintaining good impedance matching and crosstalk control is a factor that needs special consideration during PCB design.

[0036] Chips such as PCIe switches typically support hundreds of high-speed signal lines. These high-speed signal lines are distributed across the entire perimeter of the chip on the BGA and are arranged in multiple rows. The more and denser the high-speed signals, the greater the crosstalk effect. At the same time, more signals require more routing layers on the PCB for fan-out. The more layers there are, the thicker the PCB becomes, which leads to deeper signal vias. The depth and distance of the vias both affect crosstalk between signals.

[0037] PCB BGA signal layout is generally arranged in a matrix grid pattern. In order to cope with the challenges of the surge in chip I / O and product miniaturization, the traditional drilling method is to punch holes in the form of dog-bone or Via-in-pad. Among them, Via-in-Pad has become a key technology for high-density interconnection.

[0038] Both of these methods are limited by the distribution of the ball map in dense signal arrangements, leading to significant crosstalk, especially when calculating the PowerSum of all surrounding signals. For BGA packaged chips, the Via-in-Pad (VIP) PCB design is a PCB design technique that integrates microvias directly under the BGA pads to achieve high-density interconnection. Its core purpose is to save PCB space and optimize electrical and thermal performance. Its technical characteristics are mainly reflected in the following aspects:

[0039] 1. Space and cabling revolution: In space-constrained designs (such as high-density I / O), it allows more I / O to be accommodated in the same area, and is a key technology for realizing complex, multi-layer interconnect systems.

[0040] 2. Optimized electrical performance: Compared with the traditional "dog bone" fan-out, it can provide the shortest electrical path, effectively reducing parasitic inductance and capacitance, which is crucial for processing high-speed signals (such as DDR memory bus and high-speed serial links).

[0041] 3. Enhanced thermal management: Placing an array of filled vias under the large thermal pads of the power chip or processor can provide an efficient heat conduction channel for the chip, which is a standard practice to improve heat dissipation performance.

[0042] The inventors of this application discovered through research that traditional Via-in-Pad designs typically involve drilling vias in the exact center of the BGA pad, with the number of vias matching the number of BGA pads. The via spacing depends on the pad center-to-center distance, and high-speed signals are routed on the inner layer of the PCB in the center of two rows of vias. While this approach facilitates signal fan-out, it also has some drawbacks. Taking the common GSSG signal arrangement as an example, firstly, in traditional Via-in-Pad designs, the spacing between signals (S1 and S2) and between signals and ground (G) is the same. The specific value depends on the chip size; a larger or smaller value will affect the signal impedance design and crosstalk. Secondly, the number of ground vias matches the number of BGA GND pads, leading to insufficient GND isolation. Furthermore, fan-out traces pass through other signal and ground vias, and the distance between the traces and other signal and ground vias also contributes to crosstalk.

[0043] In summary, the traditional via design suffers from severe crosstalk on high-speed signal lines.

[0044] In view of this, to address the severe crosstalk issue in the BGA region caused by multiple rows of high-speed signals fanning out under dense BGA solder ball distribution, this application provides a PCB circuit board in which the vias are offset from the solder ball distribution. This increases the spacing between a pair of signal lines corresponding to adjacent signal vias in the non-trace extension direction, thereby reducing crosstalk between signal lines. Furthermore, because the vias are offset from the solder ball distribution, more ground vias can be placed on the same PCB board size, increasing the isolation between signal lines and further reducing the impact of crosstalk.

[0045] In one embodiment, such as Figure 1 This diagram shows a top view of a PCB circuit board with vias. The PCB circuit board includes a board body and vias. The board body comprises multiple layers connected by vias. The vias include signal vias and ground vias. It should be understood that the multiple layers are not shown in the top view.

[0046] In the routing direction of the PCB circuit board, the spacing between each signal hole and the adjacent ground hole, and the spacing between each signal hole and other adjacent signal holes are the first spacing; and the spacing between each ground hole and other ground holes is the second spacing; both the first spacing and the second spacing are less than the reference spacing and greater than or equal to the minimum process spacing; the reference spacing is the spacing of the solder balls in the ball array layer of the ball grid array package structure corresponding to the PCB circuit board.

[0047] The routing direction refers to the main extension trend and direction of signal lines on the circuit board during layout design, such as... Figure 1A schematic diagram showing the direction of the trace extension is provided. It can be understood that... Figure 1 This is just an example.

[0048] A via is a through-hole or non-through-hole metallized via formed through drilling, electroplating, or other processes in a multilayer PCB, used to achieve electrical connections between different conductive layers. Vias include signal vias and ground vias. Signal vias are used to transmit high-speed digital signals, analog signals, or radio frequency signals. Their main function is to provide a vertical conductive path for signals from one board layer to another, ensuring that signals pass through different layers of the PCB intact and with low loss. Ground vias are used to provide a low-impedance grounding path and ensure the integrity of the reference plane in the PCB. In multilayer PCBs, ground vias are used to reliably connect the ground planes of different layers together to form an equipotential body, avoiding ground potential differences caused by the segmentation of ground planes. Densely arranged ground vias can be used as shielding walls to isolate circuits in different areas and prevent crosstalk. In an optional embodiment of this application, the signal vias include high-speed differential signal vias. High-speed differential signal vias are metallized through-holes used to connect signal lines on different layers.

[0049] Optionally, the first spacing is not equal to the second spacing, but it is understood that both are smaller than the reference spacing.

[0050] The reference spacing refers to the spacing of the solder balls (BGA Balls) in the ball array layer of the ball grid array package structure corresponding to the PCB circuit board. The ball array layer of a ball grid array package (BGA) is a layer of solder balls arranged in an array at the bottom of the package substrate. It serves as the electrical connection and mechanical support structure between the chip and the PCB, enabling signal transmission, power distribution, and grounding between the chip and the PCB. Each solder ball can be directly electrically connected to signal lines or ground lines fanned out from the PCB, and based on this, they can be divided into signal BGA Balls and GND Balls.

[0051] Since both the first and second spacings are smaller than the reference spacing, the signal holes and ground holes are offset from the solder balls by a certain distance towards the center of the PCB board.

[0052] Based on this, for example, taking high-speed differential signal vias as an example, the PCB circuit board can provide multiple sets of GSSG vias and multiple sets of GGGG vias. A set of GSSG vias may include ground vias, P-type differential signal vias, N-type differential signal vias, and ground vias, with the spacing between vias within the set being the first spacing mentioned above. Similarly, a set of GGGG vias includes four ground vias, with the spacing between vias within the set being the second spacing mentioned above.

[0053] Therefore, compared to the traditional method of vertically corresponding vias and solder balls, in this embodiment, because the via positions are offset relative to the solder ball positions, the distance between signal holes in adjacent rows increases, thereby increasing the spacing between high-speed differential signal pairs and reducing crosstalk. The signal holes distributed along the trace extension direction are in the same row.

[0054] The aforementioned PCB circuit board includes a board body and vias. The board body comprises multiple layers connected by vias. The vias include signal vias and ground vias. In the trace extension direction of the PCB circuit board, the spacing between each signal via and an adjacent ground via, and the spacing between each signal via and other adjacent signal vias, constitute a first spacing. The spacing between each ground via and other ground vias constitutes a second spacing. Both the first and second spacings are less than a reference spacing and greater than or equal to the minimum process spacing. The reference spacing is the spacing of solder balls in the ball array layer of the ball grid array package structure corresponding to the PCB circuit board. That is, the distribution position of the vias is offset relative to the distribution position of the solder balls. Therefore, in the non-trace extension direction, the spacing between a pair of signal lines corresponding to adjacent signal vias will increase, thereby reducing crosstalk between signal lines. Furthermore, since the distribution position of the vias is offset relative to the distribution position of the solder balls, more ground vias can be placed in the same size PCB board, increasing the isolation between signal lines and further reducing the impact of crosstalk.

[0055] In one embodiment, the solder balls in the ball array layer are arranged in a grid pattern. The spacing between each solder ball and its four adjacent solder balls is equal. That is, the spacing between each solder ball and its four surrounding adjacent solder balls is a reference spacing.

[0056] In an optional embodiment of this application, the reference spacing is determined based on the layout space and layout requirements of the target chip to which the ball grid array packaging structure and PCB circuit board belong.

[0057] The spacing between solder balls in the ball array layer is determined based on the ball grid array package structure and the layout space and requirements of the target chip on the PCB. For example, the layout space is determined by the size of the BGA package substrate and the size of the physical area allocated to the chip on the PCB; layout requirements include signal integrity requirements (such as the spacing of high-speed signal lines), power / ground network distribution, thermal via locations, and clearance distances between adjacent components, etc. This is not a complete example, and can be selected according to actual needs, as long as the above arrangement is met.

[0058] Optionally, the reference pitch is in the range of 0.9 mm to 1.0 mm. For example, this range can be used for the solder ball spacing in a ball grid array package structure for PCIe chips. Preferably, the reference pitch is 0.95 mm. Figure 2The diagram shows a top view of the relative positions of the solder balls and vias. It should be noted that the two balls in the elliptical ring are a pair of signal balls, such as the P and N balls of a pair of high-speed differential signals. All other balls are GND balls.

[0059] In this embodiment, the uniform spacing between solder balls ensures a balanced stress distribution at the solder joints, reducing the risk of cracking or failure due to stress concentration. This allows the solder joints to more effectively distribute loads and maintain structural integrity when subjected to mechanical stress, thereby improving the overall stability and long-term reliability of the soldering. The regular grid arrangement provides a uniform channel for heat transfer, facilitating the rapid and uniform dissipation of heat generated during chip operation, avoiding localized overheating, and ensuring device performance.

[0060] In one embodiment, the first spacing is determined based on the signal crosstalk prevention requirements of the PCB board. As mentioned above, the first spacing includes the spacing between each signal via and the adjacent ground via, and the spacing between each signal via and other adjacent signal vias.

[0061] In an optional embodiment of this application, the requirement to prevent signal crosstalk includes the requirement of not affecting stable signal transmission. A first spacing that meets the requirement to prevent signal crosstalk can be determined in advance through experiments.

[0062] In one embodiment, the second spacing is determined based on the minimum spacing achievable by the PCB board manufacturing process.

[0063] As mentioned above, the second spacing includes the spacing between local boreholes and other boreholes.

[0064] Specifically, the difference between the second spacing and the minimum process spacing is less than the first gap threshold. The first gap threshold can be determined according to actual needs. It can be set relatively small, allowing the second spacing to approach the minimum process spacing, thus enabling the placement of more ground vias on the PCB and increasing signal line isolation. For example, if the minimum process spacing achievable based on the controllable deviation limit of the current board-level manufacturing process is 0.6mm, then the second spacing needs to be greater than or equal to 0.6mm.

[0065] Optionally, the first spacing is in the range of 0.665mm to 0.735mm. Preferably, the first spacing is 0.7mm, that is, the signal hole is offset towards the center by 0.125mm, so that the hole spacing of a set of GSSGs remains at 0.7mm.

[0066] Optionally, the second spacing is in the range of 0.618 mm to 0.683 mm. Preferably, the second spacing is 0.65 mm.

[0067] In an optional embodiment of this application, the first spacing is greater than the second spacing. For example, the first spacing is 0.7 mm and the second spacing is 0.65 mm.

[0068] Taking this as an example, such as Figure 3 A schematic diagram of the via spacing is shown. It should be noted that... Figure 3 The diagram shows the via spacing of the smallest unit, 5T5R. Both GSSG and GGGG vias can exist in the same row. Optionally, as... Figure 3 As shown, the fan-out signal traces of the PCB circuit board are connected to signal balls in different columns in sequence. From right to left, they are routed to signal layer 1, signal layer 2, signal layer 3, and signal layer 4 respectively. The layer numbers of signal layer 1, signal layer 2, signal layer 3, and signal layer 4 increase or decrease in sequence, for example, L3, L5, L10, and L12 respectively.

[0069] In this embodiment, by optimizing the via spacing, the spacing between adjacent high-speed differential signal pairs can be increased. Furthermore, optimizing the ground via spacing increases the number of ground vias, thereby increasing signal line isolation and reducing crosstalk.

[0070] In one embodiment, the multiple board layers include multiple signal line layers, multiple ground plane layers, and other board layers. The two adjacent layers of each signal line layer are ground plane layers.

[0071] The signal layer is a conductive layer in a PCB that can be used to transmit electrical signals, data signals, or control signals. Optionally, the signal layer is a differential signal layer, in which high-speed differential signal lines are provided for high-speed transmission.

[0072] The ground plane is a large copper foil layer in a PCB used to provide a stable reference potential, reduce electromagnetic interference (EMI), and improve signal integrity. It can provide a common return path for the circuit through a low-impedance path, reduce signal loop area, suppress common-mode noise, and can also act as a shielding layer to isolate crosstalk between different signal layers.

[0073] Other layers are for laying power supply lines or other wiring, and are not specifically limited here.

[0074] In this embodiment, the two adjacent layers of each signal line layer are set as ground plane layers. The ground plane forms electromagnetic shielding for the adjacent signal line layers, effectively isolating the coupling between signals. Especially for high-speed signals, their return current forms a low-impedance path through the adjacent ground plane, reducing the loop area to a minimum, significantly reducing electromagnetic radiation and sensitivity to external interference, and greatly reducing the impact of crosstalk.

[0075] In one embodiment, the plurality of signal line layers includes a plurality of first signal line layers and a plurality of second signal line layers, wherein the number of layers in which each first signal line layer is located is symmetrical about the center plane of the board to the number of layers in which one of the second signal line layers is located.

[0076] In one embodiment, the plurality of ground plane layers include a plurality of first ground plane layers and a plurality of second ground plane layers, wherein the number of layers in which each first ground plane layer is located is symmetrical with respect to the center plane of the plate.

[0077] It can be understood that when the number of layers is odd, the center surface is the middle layer; when the number of layers is even, the center surface is the center surface between the two middle layers or the center surface between the two middle layers.

[0078] For example, a PCB circuit board includes 14 layers. Excluding the top and bottom layers, L3, L5, L10, and L12 can be designated as signal line layers. L3 and L5 are the first signal line layers, and L10 and L12 are the second signal line layers. It can be understood that L3 and L12 are symmetrical about the center plane of the board; L5 and L10 are symmetrical about the center plane of the board. Furthermore, L2, L4, L6, L9, L11, and L13 can be designated as ground plane layers. L2 and L13 are symmetrical about the center plane of the board; L4 and L11 are symmetrical about the center plane of the board; L6 and L9 are symmetrical about the center plane of the board. Moreover, L2 and L4 are two adjacent ground plane layers of L3, L4 and L6 are two adjacent ground plane layers of L5, L9 and L11 are two adjacent ground plane layers of L10, and L11 and L13 are two adjacent ground plane layers of L12. Using this as an example... Figure 4 A side view of the PCB circuit board output is shown, as follows: Figure 5 A 3D side view of the PCB circuit board is shown.

[0079] In one embodiment, the signal line layer includes signal traces connected to signal vias. The spacing between the signal traces and other vias is greater than or equal to a preset distance threshold. The preset distance threshold is determined based on the anti-signal crosstalk requirements between the signal traces and other vias. The preset distance threshold that satisfies the anti-signal crosstalk requirements can be determined experimentally in advance.

[0080] In an optional embodiment of this application, the difference between a preset distance threshold and 2 mil is less than a second distance threshold. The second distance threshold can be a small value, that is, the preset distance threshold is close to 2 mil. In other words, the spacing between the signal trace and other vias is greater than or equal to 2 mil. Figure 6The schematic diagram of the routing is shown. It can be seen that in this embodiment, the position of the high-speed signal trace on the inner PCB is optimized and improved from the traditional pure straight line design to a small broken line design. The broken line is 2 mil away from the center position when the trace passes through other signal holes. This increases the distance between the trace and other signal holes by 2 mil, thereby reducing the coupling crosstalk between the trace and the via.

[0081] Simulation tests were performed on the crosstalk of the BGA RX and BGA TX signals in the PCB circuit board provided in the embodiments of this application, and the results are as follows: Figure 7 The results shown Figure 7 The diagram illustrates the crosstalk results of the PCB circuit board provided in this application embodiment and the power comparison of a conventional PCB circuit board. Specifically, the conventional technology has a combined far-end crosstalk PSFEXT of -51.498dB for the TX signal, while the solution in this application has a combined far-end crosstalk PSFEXT of -55.752dB. The conventional technology has a combined far-end crosstalk PSFEXT of -40.121dB and a combined near-end crosstalk PSNEXT of -59.023dB for the RX signal, while the solution in this application has a combined far-end crosstalk PSFEXT of -49.634dB and a combined near-end crosstalk PSNEXT of -69.872dB. That is, the TX signal power and (PowerSum) far-end crosstalk immunity are improved by approximately 10%; the RX signal power and far-end crosstalk immunity are improved by approximately 23%; and the RX signal power and near-end crosstalk immunity are improved by approximately 18%. Therefore, the PCB circuit board provided in this application mainly uses signal vias and isolation ground vias to significantly improve signal crosstalk in the PCB BGA fan-out area and enhance the anti-interference capability of high-speed signals. The design is reconstructed by optimizing the position and structure of signal vias, ground vias, and fan-out traces, and by increasing the number of ground vias, thereby significantly improving signal crosstalk. All of the above designs take into account the actual PCB manufacturing process precision and errors, thus ensuring that mass production of this PCB circuit board is achievable.

[0082] In this embodiment of the application, if the chip package size allows, the distance between high-speed signal balls and the number of balls between signals can be increased during the chip package ball map design to further increase isolation and reduce crosstalk.

[0083] In one embodiment, a PCB layout method is provided for fabricating the PCB described in any of the above embodiments. The method includes: obtaining a reference spacing, the reference spacing being the spacing between solder balls in the ball array layer of a ball grid array package structure corresponding to the PCB; determining a first spacing and a second spacing based on the reference spacing; determining the layout position of each signal hole on the PCB based on the first spacing; and determining the layout position of each ground hole on the PCB based on the first spacing and the second spacing. The first spacing is defined as the spacing between each signal hole and an adjacent ground hole, and the spacing between each signal hole and other adjacent signal holes, along with the spacing between each ground hole and other ground holes, in the trace extension direction of the PCB.

[0084] Other limitations of this method can be found in the limitations on PCB circuit boards mentioned above, and will not be repeated here.

[0085] In one embodiment, a chip is provided, the chip including a PCB circuit board as described in any of the above embodiments and a ball grid array package structure corresponding to the PCB circuit board in any of the above embodiments.

[0086] Alternatively, the chip can be a PCIe chip. Or, it can be other chips, which are not fully exemplified here.

[0087] PCIe chips can be used in network switching devices. Network switching devices are communication devices specifically designed for receiving, processing, and forwarding data packets in a network, such as, but not limited to, Ethernet switches, routers, switching chips, smart NICs, and forwarding engines in data processing units (DPUs).

[0088] In one embodiment, a computer system is provided, which includes the chip described in the above embodiments. Optionally, the computer system refers to a system capable of performing computing and data processing tasks, including at least one processor and memory. The system can be a standalone device, such as a server integrated with a smart network card, or a system composed of multiple devices interconnected via a network, such as a data center including switches, servers, and storage devices.

[0089] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A PCB circuit board, characterized in that, The PCB circuit board includes a board body and vias. The board body includes multiple board layers, which are connected to each other through the vias. The vias include signal vias and ground vias. In the trace extension direction of the PCB circuit board, the spacing between each signal hole and the adjacent ground hole, and the spacing between each signal hole and the other adjacent signal holes, is the first spacing; Furthermore, the spacing between each of the aforementioned boreholes and the other aforementioned boreholes is a second spacing; Both the first spacing and the second spacing are less than the reference spacing and greater than or equal to the minimum process spacing; The reference spacing is the spacing between solder balls in the ball array layer of the ball grid array package structure corresponding to the PCB circuit board.

2. The PCB circuit board according to claim 1, characterized in that, The solder balls in the ball array layer are arranged in a grid pattern; the spacing between each solder ball and other adjacent solder balls is equal.

3. The PCB circuit board according to claim 1, characterized in that, The first spacing is determined based on the anti-signal crosstalk requirements of the PCB circuit board; The second spacing is determined based on the minimum spacing achievable by the manufacturing process of the PCB circuit board; wherein the difference between the second spacing and the minimum spacing is less than a first difference threshold.

4. The PCB circuit board according to claim 1, characterized in that, The reference spacing is determined based on the ball grid array packaging structure and the layout space and layout requirements of the target chip to which the PCB circuit board belongs.

5. The PCB circuit board according to claim 3, characterized in that, The first spacing is greater than the second spacing.

6. The PCB circuit board according to claim 3, characterized in that, The first spacing is within the range of 0.665 mm to 0.735 mm; The second spacing is within the range of 0.618 mm to 0.683 mm; The reference spacing is in the range of 0.9 mm to 1.0 mm.

7. The PCB circuit board according to any one of claims 1 to 6, characterized in that, The multiple board layers include multiple signal line layers, multiple ground plane layers, and other board layers; The two adjacent layers of each of the signal line layers are the ground plane layers.

8. The PCB circuit board according to claim 7, characterized in that, The plurality of signal line layers includes a plurality of first signal line layers and a plurality of second signal line layers, wherein the number of each first signal line layer and the number of one of the second signal line layers are symmetrical about the center plane of the plate. The plurality of ground plane layers include a plurality of first ground plane layers and a plurality of second ground plane layers, wherein the number of each first ground plane layer and the number of one of the second ground plane layers are symmetrical about the center plane of the plate.

9. The PCB circuit board according to claim 7, characterized in that, The signal line layer includes signal traces connected to the signal aperture; The distance between the signal trace and other vias is greater than or equal to a preset distance threshold; the preset distance threshold is determined based on the anti-signal crosstalk requirements between the signal trace and other vias.

10. The PCB circuit board according to claim 9, characterized in that, The difference between the preset distance threshold and 2mil is less than the second difference threshold.

11. A layout method for a PCB circuit board, characterized in that, The method is used to determine the layout of a PCB circuit board as described in any one of claims 1 to 10; the method includes: Obtain a reference spacing, wherein the reference spacing is the spacing between solder balls in the ball array layer of the ball grid array package structure corresponding to the PCB circuit board; The first spacing and the second spacing are determined based on the reference spacing; Based on the first spacing, the layout positions of each signal hole on the PCB circuit board are determined; The layout positions of the holes on the PCB circuit board are determined based on the first spacing and the second spacing. Wherein, in the trace extension direction of the PCB circuit board, the spacing between each signal hole and the adjacent ground hole, and the spacing between each signal hole and the other adjacent signal holes are the first spacing; and the spacing between each ground hole and the other ground holes is the second spacing.

12. A chip, characterized in that, The chip includes a PCB circuit board as described in any one of claims 1 to 10 and a ball grid array package structure corresponding to the PCB circuit board as described in any one of claims 1 to 10.

Images